chip/atxmega128a1/include/chip/sysclk.h

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#ifndef CHIP_SYSCLK_H_INCLUDED
#define CHIP_SYSCLK_H_INCLUDED

#include <compiler.h>
#include <clk/pll.h>
#include <regs/xmega_pr.h>
#include <regs/xmega_clk.h>
#include <stdint.h>
#include <stdbool.h>


#define SYSCLK_SRC_RC2MHZ       0x00
#define SYSCLK_SRC_RC32MHZ      0x01
#define SYSCLK_SRC_RC32KHZ      0x02
#define SYSCLK_SRC_XOSC         0x03
#define SYSCLK_SRC_PLL          0x04



#define SYSCLK_PORT_GEN         XMEGA_PR_PRGEN  //!< No particular port
#define SYSCLK_PORT_A           XMEGA_PR_PRPA   //!< Devices on PORTA
#define SYSCLK_PORT_B           XMEGA_PR_PRPB   //!< Devices on PORTB
#define SYSCLK_PORT_C           XMEGA_PR_PRPC   //!< Devices on PORTC
#define SYSCLK_PORT_D           XMEGA_PR_PRPD   //!< Devices on PORTD
#define SYSCLK_PORT_E           XMEGA_PR_PRPE   //!< Devices on PORTE
#define SYSCLK_PORT_F           XMEGA_PR_PRPF   //!< Devices on PORTF



#define SYSCLK_DMA              (1U << PR_DMA_BIT)      //!< DMA Controller
#define SYSCLK_EVSYS            (1U << PR_EVSYS_BIT)    //!< Event System
#define SYSCLK_RTC              (1U << PR_RTC_BIT)      //!< Real-Time Counter
#define SYSCLK_EBI              (1U << PR_EBI_BIT)      //!< Ext Bus Interface
#define SYSCLK_AES              (1U << PR_AES_BIT)      //!< AES Module
#ifdef CONFIG_XMEGA_USB
# define SYSCLK_USB             (1U << PR_USB_BIT)      //!< USB Module
#endif



#define SYSCLK_AC               (1U << PR_AC_BIT)       //!< Analog Comparator
#define SYSCLK_ADC              (1U << PR_ADC_BIT)      //!< A/D Converter
#define SYSCLK_DAC              (1U << PR_DAC_BIT)      //!< D/A Converter



#define SYSCLK_TC0              (1U << PR_TC0_BIT)      //!< Timer/Counter 0
#define SYSCLK_TC1              (1U << PR_TC1_BIT)      //!< Timer/Counter 1
#define SYSCLK_HIRES            (1U << PR_HIRES_BIT)    //!< Hi-Res Extension
#define SYSCLK_SPI              (1U << PR_SPI_BIT)      //!< SPI controller
#define SYSCLK_USART0           (1U << PR_USART0_BIT)   //!< USART 0
#define SYSCLK_USART1           (1U << PR_USART1_BIT)   //!< USART 1
#define SYSCLK_TWI              (1U << PR_TWI_BIT)      //!< TWI controller


#ifndef __ASSEMBLY__

#include <assert.h>
#include <chip/memory-map.h>
#include <io.h>


static inline uint32_t sysclk_get_main_hz(void)
{
        switch (CONFIG_SYSCLK_SOURCE) {
        case SYSCLK_SRC_RC2MHZ:
                return 2000000UL;
        case SYSCLK_SRC_RC32MHZ:
                return 32000000UL;
        case SYSCLK_SRC_RC32KHZ:
                return 32768UL;
#ifdef BOARD_XOSC_HZ
        case SYSCLK_SRC_XOSC:
                return BOARD_XOSC_HZ;
#endif
#ifdef CONFIG_PLL0_SOURCE
        case SYSCLK_SRC_PLL:
                return pll_get_default_rate(0);
#endif
        default:
                unhandled_case(CONFIG_SYSCLK_SOURCE);
                return 0;
        }
}

static inline uint32_t sysclk_get_per4_hz(void)
{
        uint8_t shift = 0;

        if (CONFIG_SYSCLK_PSADIV & 0x01)
                shift = (CONFIG_SYSCLK_PSADIV >> 1) + 1;

        return sysclk_get_main_hz() >> shift;
}

static inline uint32_t sysclk_get_per2_hz(void)
{
        switch (CONFIG_SYSCLK_PSBCDIV) {
        case XMEGA_CLK_PSBCDIV_1_1:
        case XMEGA_CLK_PSBCDIV_1_2:
                return sysclk_get_per4_hz();
        case XMEGA_CLK_PSBCDIV_4_1:
                return sysclk_get_per4_hz() / 4;
        case XMEGA_CLK_PSBCDIV_2_2:
                return sysclk_get_per4_hz() / 2;
        default:
                unhandled_case(CONFIG_SYSCLK_PSBCDIV);
                return 0;
        }
}

static inline uint32_t sysclk_get_per_hz(void)
{
        if (CONFIG_SYSCLK_PSBCDIV & 0x01)
                return sysclk_get_per2_hz() / 2;
        else
                return sysclk_get_per2_hz();
}

static inline uint32_t sysclk_get_cpu_hz(void)
{
        return sysclk_get_per_hz();
}




extern void sysclk_enable_module(uint8_t port, uint8_t id);
extern void sysclk_disable_module(uint8_t port, uint8_t id);


__always_inline static bool sysclk_module_is_enabled(uint8_t port, uint8_t id)
{
        uint8_t mask = mmio_read8((void *)(PR_BASE + port));
        return (mask & id) == 0;
}



extern void sysclk_init(void);


#endif /* !__ASSEMBLY__ */


#endif /* CHIP_SYSCLK_H_INCLUDED */

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