include/spi/spi_xmega.h

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#ifndef SPI_SPI_XMEGA_H_INCLUDED
#define SPI_SPI_XMEGA_H_INCLUDED

#include <clk/sys.h>
#include <spi/spi_polled.h>


struct spi_master_priv {
        struct spi_master_polled        base;
        void                            *regs;
};

#define SPI_MASTER_NATIVE_TYPE spi_master_priv

#define SPI_MASTER_NATIVE_GET_BASE(spim_p) \
        (&((struct spi_master_priv *)spim_p)->base.base)

struct spi_device_priv {
        struct spi_device       base;
        uint8_t                 ctrl;
};

#define SPI_DEVICE_NATIVE_TYPE spi_device_priv

#define SPI_DEVICE_NATIVE_GET_BASE(spid_p) \
        (&((struct spi_device_priv *)spid_p)->base)

typedef uint8_t spi_id_t;

typedef uint8_t spi_flags_t;

static inline struct spi_master_priv *spi_master_priv_of(
                struct spi_master *spim)
{
        return container_of(spim, struct spi_master_priv, base.base);
}

static inline struct spi_device_priv *spi_device_priv_of(
                struct spi_device *spid)
{
        return container_of(spid, struct spi_device_priv, base);
}

static inline void spi_priv_enable(spi_id_t spi_id)
{
        sysclk_enable_module(spi_get_sysclk_port(spi_id), SYSCLK_SPI);
        spi_write_reg(spi_get_base(spi_id), CTRL, SPI_BIT(CTRL_ENABLE));
}

static inline void spi_priv_disable(spi_id_t spi_id)
{
        spi_write_reg(spi_get_base(spi_id), CTRL, 0);
        sysclk_disable_module(spi_get_sysclk_port(spi_id), SYSCLK_SPI);
}

static inline bool spi_priv_is_enabled(spi_id_t spi_id)
{
        return spi_read_reg(spi_get_base(spi_id), CTRL) &
                SPI_BIT(CTRL_ENABLE);
}

static inline bool spi_priv_is_int_flag_set(struct spi_master *spim)
{
        struct spi_master_priv *spim_p = spi_master_priv_of(spim);

        return spi_read_reg(spim_p->regs, STATUS) & SPI_BIT(STATUS_IF);
}

static inline uint8_t spi_priv_read_data(struct spi_master *spim)
{
        struct spi_master_priv *spim_p = spi_master_priv_of(spim);

        return spi_read_reg(spim_p->regs, DATA);
}

static inline void spi_priv_write_data(struct spi_master *spim, uint8_t data)
{
        struct spi_master_priv *spim_p = spi_master_priv_of(spim);

        spi_write_reg(spim_p->regs, DATA, data);
}

static inline void spi_priv_master_setup_device_regs(struct spi_device *device,
                spi_flags_t flags, unsigned long baud_rate)
{
        struct spi_device_priv  *spid_p = spi_device_priv_of(device);
        uint8_t                 i;
        uint32_t                prescaled_hz = CONFIG_CPU_HZ >> 1;
        uint8_t                 ctrl;

        // Set enable bit, master bit and mode
        ctrl = SPI_BIT(CTRL_ENABLE) | SPI_BIT(CTRL_MASTER) |
                SPI_BF(CTRL_MODE, flags);

        for (i = 0; i < 7; i++) {
                if (prescaled_hz <= baud_rate)
                        break;
                prescaled_hz >>= 1;
        }
        if (!(i & 1))
                ctrl |= SPI_BIT(CTRL_CLK2X);
        ctrl |= SPI_BF(CTRL_PRESCALER, i >> 1);

        spid_p->ctrl = ctrl;
}

static inline void spi_priv_select_device_regs(struct spi_master *spim,
                struct spi_device *device)
{
        struct spi_master_priv  *spim_p = spi_master_priv_of(spim);
        struct spi_device_priv  *spid_p = spi_device_priv_of(device);

        spi_write_reg(spim_p->regs, CTRL, spid_p->ctrl);
}

static inline void spi_priv_deselect_device_regs(struct spi_master *spim,
                struct spi_device *device)
{
}

static inline void spi_priv_master_init_regs(spi_id_t spi_id,
                struct spi_master *spim)
{
        struct spi_master_priv *spim_p = spi_master_priv_of(spim);

        spim_p->regs = spi_get_base(spi_id);

        spi_write_reg(spim_p->regs, CTRL,
                SPI_BIT(CTRL_ENABLE) | SPI_BIT(CTRL_MASTER));

        // Make sure any interrupt flag is cleared
        spi_read_reg(spim_p->regs, STATUS);
        spi_read_reg(spim_p->regs, DATA);
}

#endif /* SPI_SPI_XMEGA_H_INCLUDED */

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