board/xplain/include/board/sdram.h

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#ifndef BOARD_SDRAM_H_INCLUDED
#define BOARD_SDRAM_H_INCLUDED

#include <util.h>
#include <interrupt.h>

#include <clk/sys.h>

#include <regs/xmega_ebi.h>


#define BOARD_SDRAM_INITDLY     (100 * 2 * CONFIG_CPU_HZ / 1000000)

#define BOARD_SDRAM_REFRESH     (16 * 2 * CONFIG_CPU_HZ / 1000000)

#define BOARD_SDRAM_BASE        CONFIG_EXTRAM_BASE

#define BOARD_SDRAM_SIZE        (CONFIG_EXTRAM_END - CONFIG_EXTRAM_BASE + 1)

static inline void board_enable_sdram(void)
{
        sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EBI);

        // Configure SDRAM mode (4 bit data width, 3 port interface).
        ebi_write_reg(CTRL, EBI_BF(SDDATAW, EBI_SDDATAW_4BIT)
                        | EBI_BF(IFMODE, EBI_IFMODE_3PORT));

        // Configure SDRAM interface and timing.
        ebi_write_reg(SDRAMCTRLA, EBI_BIT(SDCAS) | EBI_BIT(SDROW)
                        | EBI_BF(SDCOL, EBI_SDCOL_10BIT));
        ebi_write_reg(SDRAMCTRLB, EBI_BF(MRDLY, 2) | EBI_BF(ROWCYCDLY, 7)
                        | EBI_BF(RPDLY, 7));
        ebi_write_reg(SDRAMCTRLC, EBI_BF(WRDLY, 1) | EBI_BF(ESRDLY, 7)
                        | EBI_BF(ROWCOLDLY, 7));
        ebi_write_word_reg(REFRESH, EBI_BF(REFRESH, BOARD_SDRAM_REFRESH));
        ebi_write_word_reg(INITDLY, EBI_BF(INITDLY, BOARD_SDRAM_INITDLY));

        // Configure CS module 3 in normal SDRAM mode.
        ebics_write_reg(CS3, CTRLB, EBICS_BF(SDMODE, EBICS_SDMODE_NORMAL));
        ebics_write_word_reg(CS3, BASEADDR, EBICS_BF(BASEADDR,
                        (BOARD_SDRAM_BASE >> 12)));
        ebics_write_reg(CS3, CTRLA, EBICS_BF(ASIZE,
                        ilog2(BOARD_SDRAM_SIZE) - 8)
                        | EBICS_BF(MODE, EBICS_MODE_SDRAM));

        do {
                // Wait for SDRAM to initialize.
        } while (!(ebics_read_reg(CS3, CTRLB) & EBICS_BIT(SDINITDONE)));
}

static inline void board_disable_sdram(void)
{
        // Disable CS module.
        ebics_write_reg(CS3, CTRLA, EBICS_BF(MODE, EBICS_MODE_DISABLE));

        // Disable EBI.
        ebi_write_reg(CTRL, EBI_BF(IFMODE, EBI_IFMODE_DISABLED));

        sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_EBI);
}

static inline void board_enable_sdram_selfrefresh(void)
{
        irqflags_t      flags;
        uint8_t         val;

        flags = cpu_irq_save();

        val = ebics_read_reg(CS3, CTRLB);
        val |= EBICS_BIT(SDSREN);
        ebics_write_reg(CS3, CTRLB, val);

        cpu_irq_restore(flags);
}

static inline void board_disable_sdram_selfrefresh(void)
{
        irqflags_t      flags;
        uint8_t         val;

        flags = cpu_irq_save();

        val = ebics_read_reg(CS3, CTRLB);
        val &= ~EBICS_BIT(SDSREN);
        ebics_write_reg(CS3, CTRLB, val);

        cpu_irq_restore(flags);
}


#endif /* BOARD_SDRAM_H_INCLUDED */

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