SPI Register Defintions
[Internal Register Definitions]

Collaboration diagram for SPI Register Defintions:

Register Offset
#define	SPI_CTRL   0
	Control Register.
#define	SPI_INTCTRL   1
	Interrupt Control Register.
#define	SPI_STATUS   2
	Status Register.
#define	SPI_DATA   3
	Data Register.
#define	SPI_CTRL_PRESCALER_START   0
	Clock Prescaler.
#define	SPI_CTRL_PRESCALER_SIZE   2
	Clock Prescaler.
#define	SPI_CTRL_MODE_START   2
	Mode.
#define	SPI_CTRL_MODE_SIZE   2
	Mode.
#define	SPI_CTRL_MASTER_BIT   4
	Master/Slave Select.
#define	SPI_CTRL_DORD_BIT   5
	Data Order.
#define	SPI_CTRL_ENABLE_BIT   6
	Enable.
#define	SPI_CTRL_CLK2X_BIT   7
	Clock Double.
#define	SPI_INTCTRL_INTLVL_START   0
	Interrupt Level.
#define	SPI_INTCTRL_INTLVL_SIZE   2
	Interrupt Level.
#define	SPI_STATUS_WRCOL_BIT   6
	Write Collision Flag.
#define	SPI_STATUS_IF_BIT   7
	Interrupt Flag.
Bit manipulation macros
#define	SPI_BIT(name)   (1 << SPI_##name##_BIT)
	Create a mask with bit name set.
#define	SPI_BF(name, value)
	Create a mask with bitfield name set to value.
#define	SPI_BFEXT(name, value)
	Extract the value of bitfield name from regval.
#define	SPI_BFINS(name, value, old)
	Return regval with bitfield name set to value.
Register access macros
#define	spi_write_reg(spi, reg, value)   mmio_write8((void *)((uintptr_t)(spi) + SPI_##reg), value)
	Write value to SPI register reg.
#define	spi_read_reg(spi, reg)   mmio_read8((void *)((uintptr_t)(spi) + SPI_##reg))
	Read the value of SPI register reg.

---

Define Documentation

#define SPI_BF	(	name,
		value		)

Value:

(((value) & ((1 << SPI_##name##_SIZE) - 1))     \
         << SPI_##name##_START)

Create a mask with bitfield name set to value.

Definition at line 88 of file xmega_spi.h.

Referenced by spi_priv_master_setup_device_regs().

#define SPI_BFEXT	(	name,
		value		)

Value:

(((value) >> USART_##name##_START)              \
         & ((1 << USART_##name##_SIZE) - 1))

Extract the value of bitfield name from regval.

Definition at line 92 of file xmega_spi.h.

#define SPI_BFINS	(	name,
		value,
		old		)

Value:

(((old) & ~(((1 << SPI_##name##_SIZE) - 1)      \
                    << SPI_##name##_START))             \
         | SPI_BF(name,value))

Return regval with bitfield name set to value.

Definition at line 96 of file xmega_spi.h.

#define SPI_BIT

(

name

)

(1 << SPI_##name##_BIT)

Create a mask with bit name set.

Definition at line 85 of file xmega_spi.h.

Referenced by spi_priv_enable(), spi_priv_is_enabled(), spi_priv_is_int_flag_set(), spi_priv_master_init_regs(), and spi_priv_master_setup_device_regs().

#define SPI_CTRL   0

Control Register.

Definition at line 52 of file xmega_spi.h.

#define SPI_CTRL_CLK2X_BIT   7

Clock Double.

Definition at line 67 of file xmega_spi.h.

#define SPI_CTRL_DORD_BIT   5

Data Order.

Definition at line 65 of file xmega_spi.h.

#define SPI_CTRL_ENABLE_BIT   6

Enable.

Definition at line 66 of file xmega_spi.h.

#define SPI_CTRL_MASTER_BIT   4

Master/Slave Select.

Definition at line 64 of file xmega_spi.h.

#define SPI_CTRL_MODE_SIZE   2

Mode.

Definition at line 63 of file xmega_spi.h.

#define SPI_CTRL_MODE_START   2

Mode.

Definition at line 62 of file xmega_spi.h.

#define SPI_CTRL_PRESCALER_SIZE   2

Clock Prescaler.

Definition at line 61 of file xmega_spi.h.

#define SPI_CTRL_PRESCALER_START   0

Clock Prescaler.

Definition at line 60 of file xmega_spi.h.

#define SPI_DATA   3

Data Register.

Definition at line 55 of file xmega_spi.h.

#define SPI_INTCTRL   1

Interrupt Control Register.

Definition at line 53 of file xmega_spi.h.

#define SPI_INTCTRL_INTLVL_SIZE   2

Interrupt Level.

Definition at line 73 of file xmega_spi.h.

#define SPI_INTCTRL_INTLVL_START   0

Interrupt Level.

Definition at line 72 of file xmega_spi.h.

#define spi_read_reg	(	spi,
		reg		)	mmio_read8((void *)((uintptr_t)(spi) + SPI_##reg))

Read the value of SPI register reg.

Definition at line 108 of file xmega_spi.h.

Referenced by spi_priv_is_enabled(), spi_priv_is_int_flag_set(), spi_priv_master_init_regs(), and spi_priv_read_data().

#define SPI_STATUS   2

Status Register.

Definition at line 54 of file xmega_spi.h.

#define SPI_STATUS_IF_BIT   7

Interrupt Flag.

Definition at line 79 of file xmega_spi.h.

#define SPI_STATUS_WRCOL_BIT   6

Write Collision Flag.

Definition at line 78 of file xmega_spi.h.

#define spi_write_reg	(	spi,
		reg,
		value		)	mmio_write8((void *)((uintptr_t)(spi) + SPI_##reg), value)

Write value to SPI register reg.

Definition at line 105 of file xmega_spi.h.

Referenced by spi_priv_disable(), spi_priv_enable(), spi_priv_master_init_regs(), spi_priv_select_device_regs(), and spi_priv_write_data().