PLL Management
[Clock Management]

Collaboration diagram for PLL Management:

Data Structures
struct	pll_config
	Hardware-specific representation of PLL configuration. More...
Enumerations
enum	pll_source { PLL_SRC_RC2MHZ = 0, PLL_SRC_RC32MHZ = 2, PLL_SRC_XOSC = 3, PLL_NR_SOURCES }
	PLL clock source. More...
PLL configuration

static void	pll_config_init (struct pll_config *cfg, enum pll_source src, unsigned int div, unsigned int mul)
	Initialize PLL configuration from standard parameters.
#define	pll_config_defaults(cfg, pll_id)
	Initialize PLL configuration using default parameters.
#define	pll_get_default_rate(pll_id)
	Get the default rate in Hz of pll_id.
Interaction with the PLL hardware

static void	pll_config_read (struct pll_config *cfg, unsigned int pll_id)
	Read the currently active configuration of pll_id.
static void	pll_config_write (const struct pll_config *cfg, unsigned int pll_id)
	Activate the configuration cfg on pll_id.
static void	pll_enable (const struct pll_config *cfg, unsigned int pll_id)
	Activate the configuration cfg and enable PLL pll_id.
static void	pll_disable (unsigned int pll_id)
	Disable the PLL identified by pll_id.
static status_t	pll_wait_for_lock (unsigned int pll_id)
	Wait for PLL pll_id to become locked.
Chip-specific PLL characteristics

#define	NR_PLLS 1
	Number of on-chip PLLs.
#define	PLL_MIN_HZ 10000000UL
	Minimum frequency that the PLL can generate.
#define	PLL_MAX_HZ 200000000UL
	Maximum frequency that the PLL can generate.

Detailed Description

This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs. A PLL will take an input signal (the source), optionally divide the frequency by a configurable divider, and then multiply the frequency by a configurable multiplier.

Some devices don't support input dividers; specifying any other divisor than 1 on these devices will result in an assertion failure. Other devices may have various restrictions to the frequency range of the input and output signals.

Configuration Symbols

Each PLL has a set of default parameters determined by the following configuration symbols in the application's configuration file:

CONFIG_PLLn_SOURCE: The default clock source connected to the input of PLL n. Must be one of the values defined by the pll_source enum.
CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL n.
CONFIG_PLLn_DIV: The default input divider of PLL n.

These configuration symbols determine the result of calling pll_config_defaults() and pll_get_default_rate().

Example: Setting up PLL0 with default parameters

The following example shows how to configure and enable PLL0 using the default parameters specified using the configuration symbols listed above, and with Wide Bandwidth Mode disabled (a UC3A3-specific PLL option.)

        struct pll_config pllcfg;

        pll_config_defaults(&pllcfg, 0);
        pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
        pll_config_write(&pllcfg, 0);
        pll_wait_for_lock(0);

When the last function call returns, PLL0 is ready to be used as the main system clock source.

Define Documentation

#define NR_PLLS 1

Number of on-chip PLLs.

Definition at line 52 of file pll.h.

Referenced by pll_config_read(), pll_config_write(), pll_disable(), and pll_wait_for_lock().

#define pll_config_defaults	(	cfg,
		pll_id		)

Value:

pll_config_init(cfg,                                            \
                        CONFIG_PLL##pll_id##_SOURCE,                    \
                        CONFIG_PLL##pll_id##_DIV,                       \
                        CONFIG_PLL##pll_id##_MUL)

Initialize PLL configuration using default parameters.

Parameters:

	cfg	The PLL configuration to be initialized.
	pll_id	Use defaults for this PLL.

Returns:: A configuration which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) times the frequency of CONFIG_PLLx_SOURCE.

Definition at line 97 of file pll.h.

#define pll_get_default_rate ( pll_id )

Value:

((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE)             \
                        * CONFIG_PLL##pll_id##_MUL)             \
                / CONFIG_PLL##pll_id##_DIV)

Get the default rate in Hz of pll_id.

Definition at line 64 of file pll.h.

Referenced by sysclk_get_main_hz().

#define PLL_MAX_HZ 200000000UL

Maximum frequency that the PLL can generate.

Definition at line 55 of file pll.h.

Referenced by pll_config_init().

#define PLL_MIN_HZ 10000000UL

Minimum frequency that the PLL can generate.

Definition at line 54 of file pll.h.

Enumeration Type Documentation

enum pll_source

PLL clock source.

Enumerator:

PLL_SRC_RC2MHZ	2 MHz Internal RC Oscillator
PLL_SRC_RC32MHZ	32 MHz Internal RC Oscillator
PLL_SRC_XOSC	External Clock Source.
PLL_NR_SOURCES	Number of PLL sources.

Definition at line 57 of file pll.h.

Function Documentation

void pll_config_init	(	struct pll_config *	cfg,
		enum pll_source	src,
		unsigned int	div,
		unsigned int	mul
	)			`[inline, static]`

Initialize PLL configuration from standard parameters.

Note:

The XMEGA PLL hardware uses hard-wired input dividers, so the user must ensure that div is set as follows:

If src is PLL_SRC_32MHZ, div must be set to 4.
Otherwise, div must be set to 1.

This function may be defined inline because it is assumed to be called very few times, and usually with constant parameters. Inlining it will in such cases reduce the code size significantly.

Parameters:

	cfg	The PLL configuration to be initialized.
	src	The oscillator to be used as input to the PLL.
	div	PLL input divider.
	mul	PLL loop divider (i.e. multiplier).

Returns:: A configuration which will make the PLL run at (mul / div) times the frequency of src

Definition at line 79 of file pll.h.

References assert, OSC_BF, osc_get_rate(), PLL_MAX_HZ, PLL_NR_SOURCES, and PLL_SRC_RC32MHZ.

void pll_config_read	(	struct pll_config *	cfg,
		unsigned int	pll_id
	)			`[inline, static]`

Read the currently active configuration of pll_id.

Parameters:

	cfg	The configuration object into which to store the currently active configuration.
	pll_id	The ID of the PLL to be accessed.

Definition at line 103 of file pll.h.

References assert, NR_PLLS, and osc_read_reg.

void pll_config_write	(	const struct pll_config *	cfg,
		unsigned int	pll_id
	)			`[inline, static]`

Activate the configuration cfg on pll_id.

Parameters:

	cfg	The configuration object representing the PLL configuration to be activated.
	pll_id	The ID of the PLL to be updated.

Definition at line 110 of file pll.h.

References assert, NR_PLLS, and osc_write_reg.

Referenced by pll_enable().

void pll_disable ( unsigned int pll_id ) [inline, static]

Disable the PLL identified by pll_id.

After this function is called, the PLL identified by pll_id will be disabled. The PLL configuration stored in hardware may be affected by this, so if the caller needs to restore the same configuration later, it should either do a pll_config_read() before disabling the PLL, or remember the last configuration written to the PLL.

Parameters:

pll_id

The ID of the PLL to be disabled.

Definition at line 129 of file pll.h.

References assert, NR_PLLS, OSC_BIT, osc_read_reg, and osc_write_reg.

void pll_enable	(	const struct pll_config *	cfg,
		unsigned int	pll_id
	)			`[inline, static]`

Activate the configuration cfg and enable PLL pll_id.

Parameters:

	cfg	The PLL configuration to be activated.
	pll_id	The ID of the PLL to be enabled.

Definition at line 118 of file pll.h.

References OSC_BIT, osc_read_reg, osc_write_reg, and pll_config_write().

status_t pll_wait_for_lock ( unsigned int pll_id ) [inline, static]

Wait for PLL pll_id to become locked.

Todo:: Use a timeout to avoid waiting forever and hanging the system

Parameters:

pll_id

The ID of the PLL to wait for.

Return values:

	STATUS_OK	The PLL is now locked.
	ERR_TIMEOUT	Timed out waiting for PLL to become locked.

Definition at line 140 of file pll.h.

References assert, NR_PLLS, OSC_BIT, osc_read_reg, and STATUS_OK.

PLL Management [Clock Management]

Data Structures

Enumerations

PLL configuration

Interaction with the PLL hardware

Chip-specific PLL characteristics

Detailed Description

Configuration Symbols

Define Documentation

Enumeration Type Documentation

Function Documentation

PLL Management
[Clock Management]