EBI Chip Select Register Definitions
[Internal Register Definitions]
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Channel register group offsets | |
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| #define | EBICS_CS0 0x10 |
| EBI Chip Select 0. | |
| #define | EBICS_CS1 0x14 |
| EBI Chip Select 1. | |
| #define | EBICS_CS2 0x18 |
| EBI Chip Select 2. | |
| #define | EBICS_CS3 0x1c |
| EBI Chip Select 3. | |
Chip Select register offsets | |
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| #define | EBICS_CTRLA 0x00 |
| Control register A. | |
| #define | EBICS_CTRLB 0x01 |
| Control register B. | |
| #define | EBICS_BASEADDRL 0x02 |
| Base address low byte. | |
| #define | EBICS_BASEADDRH 0x03 |
| Base address high byte. | |
Bitfields in channel CTRLA | |
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| #define | EBICS_MODE_START 0 |
| CS mode. | |
| #define | EBICS_MODE_SIZE 2 |
| CS mode. | |
| #define | EBICS_ASIZE_START 2 |
| CS address size in number of bits, minus 8. | |
| #define | EBICS_ASIZE_SIZE 5 |
| CS address size in number of bits, minus 8. | |
MODE bitfield values | |
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| #define | EBICS_MODE_DISABLE 0 |
| CS disabled. | |
| #define | EBICS_MODE_SRAM 1 |
| CS enabled for SRAM. | |
| #define | EBICS_MODE_LPC 2 |
| CS enabled for low pin-count SRAM. | |
| #define | EBICS_MODE_SDRAM 3 |
| CS enabled for SDRAM. | |
Bitfields in channel CTRLB (SRAM) | |
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| #define | EBICS_SRWS_START 0 |
| SRAM wait states in number of CLKper2 cycles. | |
| #define | EBICS_SRWS_SIZE 3 |
| SRAM wait states in number of CLKper2 cycles. | |
Bitfields in channel CTRLB (SDRAM) | |
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| #define | EBICS_SDMODE_START 0 |
| SDRAM mode. | |
| #define | EBICS_SDMODE_SIZE 2 |
| SDRAM mode. | |
| #define | EBICS_SDSREN_BIT 2 |
| SDRAM self-refresh enable. | |
| #define | EBICS_SDINITDONE_BIT 7 |
| SDRAM initialization done. | |
SDMODE bitfield values | |
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| #define | EBICS_SDMODE_NORMAL 0 |
| Normal mode. | |
| #define | EBICS_SDMODE_LOAD 1 |
| Load mode. | |
Bitfields in BASEADDR | |
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| #define | EBICS_BASEADDR_START 4 |
| CS base address in number of 4 kB pages. | |
| #define | EBICS_BASEADDR_SIZE 12 |
| CS base address in number of 4 kB pages. | |
Bitfields in BASEADDRL | |
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| #define | EBICS_BASEADDRL_START 4 |
| CS base address in number of 4 kB pages (LSB). | |
| #define | EBICS_BASEADDRL_SIZE 4 |
| CS base address in number of 4 kB pages (LSB). | |
Bitfields in BASEADDRH | |
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| #define | EBICS_BASEADDRH_START 0 |
| CS base address in number of 4 kB pages (MSB). | |
| #define | EBICS_BASEADDRH_SIZE 8 |
| CS base address in number of 4 kB pages (MSB). | |
Chip Select bit manipulation macros | |
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| #define | EBICS_BIT(name) (1U << EBICS_##name##_BIT) |
| Create a mask with bit name set. | |
| #define | EBICS_BF(name, value) ((value) << EBICS_##name##_START) |
| Create a mask with bitfield name set to value. | |
| #define | EBICS_BFMASK(name) (((1U << EBICS_##name##_SIZE) - 1) << EBICS_##name##_START) |
| Create a mask of the bitfield name. | |
| #define | EBICS_BFEXT(name, regval) |
| Extract the value of bitfield name from regval. | |
| #define | EBICS_BFINS(name, value, regval) |
| Return regval with bitfield name set to value. | |
Chip Select line register access macros | |
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| #define | ebics_read_reg(cs, reg) mmio_read8((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs + EBICS_##reg)) |
| Read value of EBI register reg for CS cs. | |
| #define | ebics_write_reg(cs, reg, value) |
| Write value to EBI register reg for CS cs. | |
| #define | ebics_read_word_reg(cs, reg) |
| Read value of EBI word-register reg for CS cs. | |
| #define | ebics_write_word_reg(cs, reg, value) |
| Write value to EBI word-register reg for CS cs. | |
Define Documentation
| #define EBICS_ASIZE_SIZE 5 |
CS address size in number of bits, minus 8.
Definition at line 284 of file xmega_ebi.h.
| #define EBICS_ASIZE_START 2 |
CS address size in number of bits, minus 8.
Definition at line 282 of file xmega_ebi.h.
| #define EBICS_BASEADDR_SIZE 12 |
CS base address in number of 4 kB pages.
Definition at line 322 of file xmega_ebi.h.
| #define EBICS_BASEADDR_START 4 |
CS base address in number of 4 kB pages.
Definition at line 320 of file xmega_ebi.h.
| #define EBICS_BASEADDRH 0x03 |
Base address high byte.
Definition at line 271 of file xmega_ebi.h.
| #define EBICS_BASEADDRH_SIZE 8 |
CS base address in number of 4 kB pages (MSB).
Definition at line 338 of file xmega_ebi.h.
| #define EBICS_BASEADDRH_START 0 |
CS base address in number of 4 kB pages (MSB).
Definition at line 336 of file xmega_ebi.h.
| #define EBICS_BASEADDRL 0x02 |
Base address low byte.
Definition at line 270 of file xmega_ebi.h.
| #define EBICS_BASEADDRL_SIZE 4 |
CS base address in number of 4 kB pages (LSB).
Definition at line 330 of file xmega_ebi.h.
| #define EBICS_BASEADDRL_START 4 |
CS base address in number of 4 kB pages (LSB).
Definition at line 328 of file xmega_ebi.h.
| #define EBICS_BF | ( | name, | |||
| value | ) | ((value) << EBICS_##name##_START) |
Create a mask with bitfield name set to value.
Definition at line 347 of file xmega_ebi.h.
Referenced by board_disable_sdram(), and board_enable_sdram().
| #define EBICS_BFEXT | ( | name, | |||
| regval | ) |
(((regval) >> EBICS_##name##_START) \
& ((1U << EBICS_##name##_SIZE) - 1))
Extract the value of bitfield name from regval.
Definition at line 353 of file xmega_ebi.h.
| #define EBICS_BFINS | ( | name, | |||
| value, | |||||
| regval | ) |
(((regval) & ~(((1U << EBICS_##name##_SIZE) - 1) \
<< EBICS_##name##_START)) \
| EBICS_BF(name, value))
Return regval with bitfield name set to value.
Definition at line 357 of file xmega_ebi.h.
| #define EBICS_BFMASK | ( | name | ) | (((1U << EBICS_##name##_SIZE) - 1) << EBICS_##name##_START) |
Create a mask of the bitfield name.
Definition at line 350 of file xmega_ebi.h.
| #define EBICS_BIT | ( | name | ) | (1U << EBICS_##name##_BIT) |
Create a mask with bit name set.
Definition at line 344 of file xmega_ebi.h.
Referenced by board_disable_sdram_selfrefresh(), board_enable_sdram(), and board_enable_sdram_selfrefresh().
| #define EBICS_CS0 0x10 |
EBI Chip Select 0.
Definition at line 260 of file xmega_ebi.h.
| #define EBICS_CS1 0x14 |
EBI Chip Select 1.
Definition at line 261 of file xmega_ebi.h.
| #define EBICS_CS2 0x18 |
EBI Chip Select 2.
Definition at line 262 of file xmega_ebi.h.
| #define EBICS_CS3 0x1c |
EBI Chip Select 3.
Definition at line 263 of file xmega_ebi.h.
| #define EBICS_CTRLA 0x00 |
Control register A.
Definition at line 268 of file xmega_ebi.h.
| #define EBICS_CTRLB 0x01 |
Control register B.
Definition at line 269 of file xmega_ebi.h.
| #define EBICS_MODE_DISABLE 0 |
| #define EBICS_MODE_LPC 2 |
CS enabled for low pin-count SRAM.
Definition at line 291 of file xmega_ebi.h.
| #define EBICS_MODE_SDRAM 3 |
CS enabled for SDRAM.
Definition at line 292 of file xmega_ebi.h.
Referenced by board_enable_sdram().
| #define EBICS_MODE_SIZE 2 |
CS mode.
Definition at line 280 of file xmega_ebi.h.
| #define EBICS_MODE_SRAM 1 |
CS enabled for SRAM.
Definition at line 290 of file xmega_ebi.h.
| #define EBICS_MODE_START 0 |
CS mode.
Definition at line 278 of file xmega_ebi.h.
| #define ebics_read_reg | ( | cs, | |||
| reg | ) | mmio_read8((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs + EBICS_##reg)) |
Read value of EBI register reg for CS cs.
Definition at line 366 of file xmega_ebi.h.
Referenced by board_disable_sdram_selfrefresh(), board_enable_sdram(), and board_enable_sdram_selfrefresh().
| #define ebics_read_word_reg | ( | cs, | |||
| reg | ) |
mmio_read16((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs \ + EBICS_##reg##L))
Read value of EBI word-register reg for CS cs.
For use with BASEADDR.
Definition at line 377 of file xmega_ebi.h.
| #define EBICS_SDINITDONE_BIT 7 |
SDRAM initialization done.
Definition at line 308 of file xmega_ebi.h.
| #define EBICS_SDMODE_LOAD 1 |
Load mode.
Definition at line 314 of file xmega_ebi.h.
| #define EBICS_SDMODE_NORMAL 0 |
| #define EBICS_SDMODE_SIZE 2 |
SDRAM mode.
Definition at line 306 of file xmega_ebi.h.
| #define EBICS_SDMODE_START 0 |
SDRAM mode.
Definition at line 305 of file xmega_ebi.h.
| #define EBICS_SDSREN_BIT 2 |
SDRAM self-refresh enable.
Definition at line 307 of file xmega_ebi.h.
| #define EBICS_SRWS_SIZE 3 |
SRAM wait states in number of CLKper2 cycles.
Definition at line 300 of file xmega_ebi.h.
| #define EBICS_SRWS_START 0 |
SRAM wait states in number of CLKper2 cycles.
Definition at line 298 of file xmega_ebi.h.
| #define ebics_write_reg | ( | cs, | |||
| reg, | |||||
| value | ) |
mmio_write8((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs \ + EBICS_##reg), (value))
Write value to EBI register reg for CS cs.
Definition at line 369 of file xmega_ebi.h.
Referenced by board_disable_sdram(), board_disable_sdram_selfrefresh(), board_enable_sdram(), and board_enable_sdram_selfrefresh().
| #define ebics_write_word_reg | ( | cs, | |||
| reg, | |||||
| value | ) |
mmio_write16((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs \ + EBICS_##reg##L), (value))
Write value to EBI word-register reg for CS cs.
For use with BASEADDR.
Definition at line 385 of file xmega_ebi.h.
Referenced by board_enable_sdram().
