ADC Channel Register Definitions
[Internal Register Definitions]
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Channel register group offsets | |
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| #define | ADCCH_CH0 0x20 |
| ADC channel 0 register group. | |
| #define | ADCCH_CH1 0x28 |
| ADC channel 1 register group. | |
| #define | ADCCH_CH2 0x30 |
| ADC channel 2 register group. | |
| #define | ADCCH_CH3 0x38 |
| ADC channel 3 register group. | |
Channel register offsets | |
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| #define | ADCCH_CTRL 0x00 |
| ADC channel control. | |
| #define | ADCCH_MUXCTRL 0x01 |
| ADC channel MUX control. | |
| #define | ADCCH_INTCTRL 0x02 |
| ADC channel interrupt control. | |
| #define | ADCCH_INTFLAG 0x03 |
| ADC channel interrupt flag. | |
| #define | ADCCH_RESL 0x04 |
| ADC channel result low byte. | |
| #define | ADCCH_RESH 0x05 |
| ADC channel result high byte. | |
Bitfields in channel CTRL | |
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| #define | ADCCH_INPUTMODE_START 0 |
| Channel input mode. | |
| #define | ADCCH_INPUTMODE_SIZE 2 |
| Channel input mode. | |
| #define | ADCCH_GAIN_START 2 |
| Channel gain setting. | |
| #define | ADCCH_GAIN_SIZE 3 |
| Channel gain setting. | |
| #define | ADCCH_START_BIT 7 |
| Start conversion on channel. | |
INPUTMODE bitfield values | |
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| #define | ADCCH_INPUTMODE_INTERNAL 0 |
| Internal input signal. | |
| #define | ADCCH_INPUTMODE_SINGLEENDED 1 |
| Single-ended input signal. | |
| #define | ADCCH_INPUTMODE_DIFF 2 |
| Differential input signal. | |
| #define | ADCCH_INPUTMODE_DIFFWGAIN 3 |
| Differential input signal with gain. | |
GAIN bitfield values | |
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| #define | ADCCH_GAIN_1X 0 |
| Unity gain for differential signal. | |
| #define | ADCCH_GAIN_2X 1 |
| 2x gain for differential signal | |
| #define | ADCCH_GAIN_4X 2 |
| 4x gain for differential signal | |
| #define | ADCCH_GAIN_8X 3 |
| 8x gain for differential signal | |
| #define | ADCCH_GAIN_16X 4 |
| 16x gain for differential signal | |
| #define | ADCCH_GAIN_32X 5 |
| 32x gain for differential signal | |
| #define | ADCCH_GAIN_64X 6 |
| 64x gain for differential signal | |
Bitfields in channel MUXCTRL | |
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| #define | ADCCH_MUXNEG_START 0 |
| Negative input signal MUX selection. | |
| #define | ADCCH_MUXNEG_SIZE 2 |
| Negative input signal MUX selection. | |
| #define | ADCCH_MUXPOS_START 3 |
| Positive input signal MUX selection. | |
| #define | ADCCH_MUXPOS_SIZE 3 |
| Positive input signal MUX selection. | |
| #define | ADDCH_MUXPOS3_BIT 6 |
| Use pin on secondary port. | |
MUXNEG bitfield values | |
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| #define | ADCCH_MUXNEG_PIN0 0 |
| ADC0 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN1 1 |
| ADC1 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN2 2 |
| ADC2 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN3 3 |
| ADC3 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN4 4 |
| ADC4 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN5 5 |
| ADC5 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN6 6 |
| ADC6 pin as negative input. | |
| #define | ADCCH_MUXNEG_PIN7 7 |
| ADC7 pin as negative input. | |
MUXPOS bitfield values | |
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| #define | ADCCH_MUXPOS_TEMP 0 |
| Temperature reference as positive input. | |
| #define | ADCCH_MUXPOS_BANDGAP 1 |
| Bandgap reference as positive input. | |
| #define | ADCCH_MUXPOS_SCALEDVCC 2 |
| VCC/10 as as positive input. | |
| #define | ADCCH_MUXPOS_DAC 3 |
| DAC output as positive input. | |
| #define | ADCCH_MUXPOS_PIN0 0 |
| ADC0 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN1 1 |
| ADC1 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN2 2 |
| ADC2 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN3 3 |
| ADC3 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN4 4 |
| ADC4 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN5 5 |
| ADC5 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN6 6 |
| ADC6 pin as positive input. | |
| #define | ADCCH_MUXPOS_PIN7 7 |
| ADC7 pin as positive input. | |
Bitfields in channel INTCTRL | |
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| #define | ADCCH_INTLVL_START 0 |
| ADC channel interrupt level. | |
| #define | ADCCH_INTLVL_SIZE 2 |
| ADC channel interrupt level. | |
| #define | ADCCH_INTMODE_START 2 |
| ADC channel interrupt mode. | |
| #define | ADCCH_INTMODE_SIZE 2 |
| ADC channel interrupt mode. | |
INTLVL bitfield values | |
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| #define | ADCCH_INTLVL_OFF 0 |
| Interrupt disabled. | |
| #define | ADCCH_INTLVL_LO 1 |
| Low level interrupt. | |
| #define | ADCCH_INTLVL_MED 2 |
| Medium level interrupt. | |
| #define | ADCCH_INTLVL_HI 3 |
| High level interrupt. | |
INTMODE bitfield values | |
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| #define | ADCCH_INTMODE_COMPLETE 0 |
| Interrupt on conversion completion. | |
| #define | ADCCH_INTMODE_BELOW 1 |
| Interrupt if conversion result is below comparison value. | |
| #define | ADCCH_INTMODE_ABOVE 3 |
| Interrupt if conversion result is above comparison value. | |
Bitfields in channel INTFLAG | |
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| #define | ADCCH_IF_BIT 0 |
| ADC channel interrupt flag. | |
Channel bit manipulation macros | |
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| #define | ADCCH_BIT(name) (1U << ADCCH_##name##_BIT) |
| Create a mask with bit name set. | |
| #define | ADCCH_BF(name, value) ((value) << ADCCH_##name##_START) |
| Create a mask with bitfield name set to value. | |
| #define | ADCCH_BFMASK(name) (((1U << ADCCH_##name##_SIZE) - 1) << ADCCH_##name##_START) |
| Create a mask of the bitfield name. | |
| #define | ADCCH_BFEXT(name, regval) |
| Extract the value of bitfield name from regval. | |
| #define | ADCCH_BFINS(name, value, regval) |
| Return regval with bitfield name set to value. | |
Channel register access macros | |
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| #define | adcch_read_reg(base, ch, reg) mmio_read8((void *)((uintptr_t)(base) + ADCCH_##ch + ADCCH_##reg)) |
| Read value of register reg of channel ch on ADC with base address base. | |
| #define | adcch_write_reg(base, ch, reg, value) mmio_write8((void *)((uintptr_t)(base) + ADCCH_##ch + ADCCH_##reg), (value)) |
| Write value to register reg of channel ch on ADC with base address base. | |
Define Documentation
| #define ADCCH_BF | ( | name, | |||
| value | ) | ((value) << ADCCH_##name##_START) |
Create a mask with bitfield name set to value.
Definition at line 373 of file xmega_adc.h.
Referenced by touch_priv_adc_disable_int(), touch_priv_adc_enable_int(), touch_priv_adc_init(), touch_priv_adc_set_surface_x(), and touch_priv_adc_set_surface_y().
| #define ADCCH_BFEXT | ( | name, | |||
| regval | ) |
(((regval) >> ADCCH_##name##_START) \
& ((1U << ADCCH_##name##_SIZE) - 1))
Extract the value of bitfield name from regval.
Definition at line 379 of file xmega_adc.h.
| #define ADCCH_BFINS | ( | name, | |||
| value, | |||||
| regval | ) |
(((regval) & ~(((1U << ADCCH_##name##_SIZE) - 1) \
<< ADCCH_##name##_START)) \
| ADCCH_BF(name, value))
Return regval with bitfield name set to value.
Definition at line 383 of file xmega_adc.h.
| #define ADCCH_BFMASK | ( | name | ) | (((1U << ADCCH_##name##_SIZE) - 1) << ADCCH_##name##_START) |
Create a mask of the bitfield name.
Definition at line 376 of file xmega_adc.h.
| #define ADCCH_BIT | ( | name | ) | (1U << ADCCH_##name##_BIT) |
Create a mask with bit name set.
Definition at line 370 of file xmega_adc.h.
| #define ADCCH_CH0 0x20 |
ADC channel 0 register group.
Definition at line 253 of file xmega_adc.h.
| #define ADCCH_CH1 0x28 |
ADC channel 1 register group.
Definition at line 254 of file xmega_adc.h.
| #define ADCCH_CH2 0x30 |
ADC channel 2 register group.
Definition at line 255 of file xmega_adc.h.
| #define ADCCH_CH3 0x38 |
ADC channel 3 register group.
Definition at line 256 of file xmega_adc.h.
| #define ADCCH_CTRL 0x00 |
ADC channel control.
Definition at line 261 of file xmega_adc.h.
| #define ADCCH_GAIN_16X 4 |
16x gain for differential signal
Definition at line 292 of file xmega_adc.h.
| #define ADCCH_GAIN_1X 0 |
Unity gain for differential signal.
Definition at line 288 of file xmega_adc.h.
| #define ADCCH_GAIN_2X 1 |
2x gain for differential signal
Definition at line 289 of file xmega_adc.h.
| #define ADCCH_GAIN_32X 5 |
32x gain for differential signal
Definition at line 293 of file xmega_adc.h.
| #define ADCCH_GAIN_4X 2 |
4x gain for differential signal
Definition at line 290 of file xmega_adc.h.
| #define ADCCH_GAIN_64X 6 |
64x gain for differential signal
Definition at line 294 of file xmega_adc.h.
| #define ADCCH_GAIN_8X 3 |
8x gain for differential signal
Definition at line 291 of file xmega_adc.h.
| #define ADCCH_GAIN_SIZE 3 |
Channel gain setting.
Definition at line 274 of file xmega_adc.h.
| #define ADCCH_GAIN_START 2 |
Channel gain setting.
Definition at line 273 of file xmega_adc.h.
| #define ADCCH_IF_BIT 0 |
ADC channel interrupt flag.
Definition at line 364 of file xmega_adc.h.
| #define ADCCH_INPUTMODE_DIFF 2 |
Differential input signal.
Definition at line 282 of file xmega_adc.h.
| #define ADCCH_INPUTMODE_DIFFWGAIN 3 |
Differential input signal with gain.
Definition at line 283 of file xmega_adc.h.
| #define ADCCH_INPUTMODE_INTERNAL 0 |
Internal input signal.
Definition at line 280 of file xmega_adc.h.
| #define ADCCH_INPUTMODE_SINGLEENDED 1 |
Single-ended input signal.
Definition at line 281 of file xmega_adc.h.
Referenced by touch_priv_adc_init().
| #define ADCCH_INPUTMODE_SIZE 2 |
Channel input mode.
Definition at line 272 of file xmega_adc.h.
| #define ADCCH_INPUTMODE_START 0 |
Channel input mode.
Definition at line 271 of file xmega_adc.h.
| #define ADCCH_INTCTRL 0x02 |
ADC channel interrupt control.
Definition at line 263 of file xmega_adc.h.
| #define ADCCH_INTFLAG 0x03 |
ADC channel interrupt flag.
Definition at line 264 of file xmega_adc.h.
| #define ADCCH_INTLVL_HI 3 |
High level interrupt.
Definition at line 349 of file xmega_adc.h.
| #define ADCCH_INTLVL_LO 1 |
Low level interrupt.
Definition at line 347 of file xmega_adc.h.
| #define ADCCH_INTLVL_MED 2 |
Medium level interrupt.
Definition at line 348 of file xmega_adc.h.
| #define ADCCH_INTLVL_OFF 0 |
Interrupt disabled.
Definition at line 346 of file xmega_adc.h.
Referenced by touch_priv_adc_disable_int().
| #define ADCCH_INTLVL_SIZE 2 |
ADC channel interrupt level.
Definition at line 339 of file xmega_adc.h.
| #define ADCCH_INTLVL_START 0 |
ADC channel interrupt level.
Definition at line 338 of file xmega_adc.h.
| #define ADCCH_INTMODE_ABOVE 3 |
Interrupt if conversion result is above comparison value.
Definition at line 359 of file xmega_adc.h.
| #define ADCCH_INTMODE_BELOW 1 |
Interrupt if conversion result is below comparison value.
Definition at line 357 of file xmega_adc.h.
| #define ADCCH_INTMODE_COMPLETE 0 |
Interrupt on conversion completion.
Definition at line 355 of file xmega_adc.h.
| #define ADCCH_INTMODE_SIZE 2 |
ADC channel interrupt mode.
Definition at line 341 of file xmega_adc.h.
| #define ADCCH_INTMODE_START 2 |
ADC channel interrupt mode.
Definition at line 340 of file xmega_adc.h.
| #define ADCCH_MUXCTRL 0x01 |
ADC channel MUX control.
Definition at line 262 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN0 0 |
ADC0 pin as negative input.
Definition at line 308 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN1 1 |
ADC1 pin as negative input.
Definition at line 309 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN2 2 |
ADC2 pin as negative input.
Definition at line 310 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN3 3 |
ADC3 pin as negative input.
Definition at line 311 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN4 4 |
ADC4 pin as negative input.
Definition at line 312 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN5 5 |
ADC5 pin as negative input.
Definition at line 313 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN6 6 |
ADC6 pin as negative input.
Definition at line 314 of file xmega_adc.h.
| #define ADCCH_MUXNEG_PIN7 7 |
ADC7 pin as negative input.
Definition at line 315 of file xmega_adc.h.
| #define ADCCH_MUXNEG_SIZE 2 |
Negative input signal MUX selection.
Definition at line 300 of file xmega_adc.h.
| #define ADCCH_MUXNEG_START 0 |
Negative input signal MUX selection.
Definition at line 299 of file xmega_adc.h.
| #define ADCCH_MUXPOS_BANDGAP 1 |
Bandgap reference as positive input.
Definition at line 322 of file xmega_adc.h.
| #define ADCCH_MUXPOS_DAC 3 |
DAC output as positive input.
Definition at line 324 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN0 0 |
ADC0 pin as positive input.
Definition at line 326 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN1 1 |
ADC1 pin as positive input.
Definition at line 327 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN2 2 |
ADC2 pin as positive input.
Definition at line 328 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN3 3 |
ADC3 pin as positive input.
Definition at line 329 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN4 4 |
ADC4 pin as positive input.
Definition at line 330 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN5 5 |
ADC5 pin as positive input.
Definition at line 331 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN6 6 |
ADC6 pin as positive input.
Definition at line 332 of file xmega_adc.h.
| #define ADCCH_MUXPOS_PIN7 7 |
ADC7 pin as positive input.
Definition at line 333 of file xmega_adc.h.
| #define ADCCH_MUXPOS_SCALEDVCC 2 |
VCC/10 as as positive input.
Definition at line 323 of file xmega_adc.h.
| #define ADCCH_MUXPOS_SIZE 3 |
Positive input signal MUX selection.
Definition at line 302 of file xmega_adc.h.
| #define ADCCH_MUXPOS_START 3 |
Positive input signal MUX selection.
Definition at line 301 of file xmega_adc.h.
| #define ADCCH_MUXPOS_TEMP 0 |
Temperature reference as positive input.
Definition at line 321 of file xmega_adc.h.
| #define adcch_read_reg | ( | base, | |||
| ch, | |||||
| reg | ) | mmio_read8((void *)((uintptr_t)(base) + ADCCH_##ch + ADCCH_##reg)) |
Read value of register reg of channel ch on ADC with base address base.
Definition at line 395 of file xmega_adc.h.
| #define ADCCH_RESH 0x05 |
ADC channel result high byte.
Definition at line 266 of file xmega_adc.h.
| #define ADCCH_RESL 0x04 |
ADC channel result low byte.
Definition at line 265 of file xmega_adc.h.
| #define ADCCH_START_BIT 7 |
Start conversion on channel.
Definition at line 275 of file xmega_adc.h.
| #define adcch_write_reg | ( | base, | |||
| ch, | |||||
| reg, | |||||
| value | ) | mmio_write8((void *)((uintptr_t)(base) + ADCCH_##ch + ADCCH_##reg), (value)) |
Write value to register reg of channel ch on ADC with base address base.
Definition at line 401 of file xmega_adc.h.
Referenced by touch_priv_adc_disable_int(), touch_priv_adc_enable_int(), touch_priv_adc_init(), touch_priv_adc_set_surface_x(), and touch_priv_adc_set_surface_y().
| #define ADDCH_MUXPOS3_BIT 6 |
Use pin on secondary port.
Definition at line 303 of file xmega_adc.h.
