ADC Register Definitions
[Internal Register Definitions]
|
Register offsets | |
|
| |
| #define | ADC_CTRLA 0x00 |
| Control register A. | |
| #define | ADC_CTRLB 0x01 |
| Control register B. | |
| #define | ADC_REFCTRL 0x02 |
| Reference control. | |
| #define | ADC_EVCTRL 0x03 |
| Event control. | |
| #define | ADC_PRESCALER 0x04 |
| ADC clock prescaling. | |
| #define | ADC_INTFLAGS 0x06 |
| Interrupt flags for ADC channels. | |
| #define | ADC_TEMP 0x07 |
| Temporary register for 16-bit reads. | |
| #define | ADC_CALL 0x0C |
| ADC calibration low byte. | |
| #define | ADC_CALH 0x0D |
| ADC calibration high byte. | |
| #define | ADC_CH0RESL 0x10 |
| ADC channel 0 result low byte. | |
| #define | ADC_CH0RESH 0x11 |
| ADC channel 0 result high byte. | |
| #define | ADC_CH1RESL 0x12 |
| ADC channel 1 result low byte. | |
| #define | ADC_CH1RESH 0x13 |
| ADC channel 1 result high byte. | |
| #define | ADC_CH2RESL 0x14 |
| ADC channel 2 result low byte. | |
| #define | ADC_CH2RESH 0x15 |
| ADC channel 2 result high byte. | |
| #define | ADC_CH3RESL 0x16 |
| ADC channel 3 result low byte. | |
| #define | ADC_CH3RESH 0x17 |
| ADC channel 3 result high byte. | |
| #define | ADC_CMPL 0x18 |
| ADC compare low byte. | |
| #define | ADC_CMPH 0x19 |
| ADC compare high byte. | |
Bitfields in CTRLA | |
|
| |
| #define | ADC_ENABLE_BIT 0 |
| ADC enable. | |
| #define | ADC_FLUSH_BIT 1 |
| ADC flush. | |
| #define | ADC_CHSTART_START 2 |
| ADC channel start single conversion. | |
| #define | ADC_CHSTART_SIZE 4 |
| ADC channel start single conversion. | |
| #define | ADC_DMASEL_START 6 |
| ADC channel DMA request selection. | |
| #define | ADC_DMASEL_SIZE 2 |
| ADC channel DMA request selection. | |
CHSTART bitfield values | |
|
| |
| #define | ADC_CHSTART_0 1 |
| Start conversion on ADC channel 0. | |
| #define | ADC_CHSTART_1 2 |
| Start conversion on ADC channel 1. | |
| #define | ADC_CHSTART_2 4 |
| Start conversion on ADC channel 2. | |
| #define | ADC_CHSTART_3 8 |
| Start conversion on ADC channel 3. | |
DMASEL bitfield values | |
|
| |
| #define | ADC_DMASEL_OFF 0 |
| No combined DMA request. | |
| #define | ADC_DMASEL_CH01 1 |
| ADC channel 0 and 1 can trigger DMA. | |
| #define | ADC_DMASEL_CH012 2 |
| ADC channel 0, 1 and 2 can trigger DMA. | |
| #define | ADC_DMASEL_CH0123 3 |
| All ADC channels can trigger DMA. | |
Bitfields in CTRLB | |
|
| |
| #define | ADC_RESOLUTION_START 1 |
| ADC conversion resolution. | |
| #define | ADC_RESOLUTION_SIZE 2 |
| ADC conversion resolution. | |
| #define | ADC_FREERUN_BIT 3 |
| ADC free running mode. | |
| #define | ADC_CONVMODE_BIT 4 |
| ADC signed/unsigned conversion mode. | |
RESOLUTION bitfield values | |
|
| |
| #define | ADC_RESOLUTION_12BIT 0 |
| 12-bit result, right adjusted | |
| #define | ADC_RESOLUTION_8BIT 2 |
| 8-bit result, right adjusted | |
| #define | ADC_RESOLUTION_LEFT12BIT 3 |
| 12-bit result, left adjusted | |
Bitfields in REFCTRL | |
|
| |
| #define | ADC_TEMPREF_BIT 0 |
| Enable temperature reference for measurement. | |
| #define | ADC_BANDGAP_BIT 1 |
| Enable bandgap for measurement. | |
| #define | ADC_REFSEL_START 4 |
| ADC reference selection. | |
| #define | ADC_REFSEL_SIZE 2 |
| ADC reference selection. | |
REFSEL bitfield values | |
|
| |
| #define | ADC_REFSEL_INT1V 0 |
| Internal 1.00 V as reference. | |
| #define | ADC_REFSEL_INTVCC 1 |
| Internal VCC/1.6 V as reference. | |
| #define | ADC_REFSEL_AREFA 2 |
| External reference from AREFA. | |
| #define | ADC_REFSEL_AREFB 3 |
| External reference from AREFB. | |
Bitfields in EVCTRL | |
|
| |
| #define | ADC_EVACT_START 0 |
| ADC event mode. | |
| #define | ADC_EVACT_SIZE 3 |
| ADC event mode. | |
| #define | ADC_EVSEL_START 3 |
| ADC event line selection. | |
| #define | ADC_EVSEL_SIZE 3 |
| ADC event line selection. | |
| #define | ADC_SWEEP_START 6 |
| ADC channel sweep selection. | |
| #define | ADC_SWEEP_SIZE 2 |
| ADC channel sweep selection. | |
EVACT bitfield values | |
|
| |
| #define | ADC_EVACT_NONE 0 |
| < No event action | |
| #define | ADC_EVACT_CH0 1 |
| Lowest event line triggers conversion on ADC channel 0. | |
| #define | ADC_EVACT_CH01 2 |
| Two lowest event lines trigger conversions on ADC channels 0 and 1. | |
| #define | ADC_EVACT_CH012 3 |
| Three lowest event lines trigger conversions on ADC channels 0, 1 and 2. | |
| #define | ADC_EVACT_CH0123 4 |
| All event lines trigger conversions on the respective ADC channels. | |
| #define | ADC_EVACT_SWEEP 5 |
| Lowest event line triggers channel sweep. | |
| #define | ADC_EVACT_SYNCSWEEP 6 |
| Lowest event line triggers channel sweep with synchronization. | |
EVSEL bitfield values | |
|
| |
| #define | ADC_EVSEL_0123 0 |
| Event channels 0, 1, 2 and 3 as event lines. | |
| #define | ADC_EVSEL_1234 1 |
| Event channels 1, 2, 3 and 4 as event lines. | |
| #define | ADC_EVSEL_2345 2 |
| Event channels 2, 3, 4 and 5 as event lines. | |
| #define | ADC_EVSEL_3456 3 |
| Event channels 3, 4, 5 and 6 as event lines. | |
| #define | ADC_EVSEL_4567 4 |
| Event channels 4, 5, 6 and 7 as event lines. | |
| #define | ADC_EVSEL_567 5 |
| Event channels 5, 6, and 7 as event lines. | |
| #define | ADC_EVSEL_67 6 |
| Event channels 6 and 7 as event lines. | |
| #define | ADC_EVSEL_7 7 |
| Event channel 7 as event line. | |
SWEEP bitfield values | |
|
| |
| #define | ADC_SWEEP_0 0 |
| Sweep ADC channel 0 only. | |
| #define | ADC_SWEEP_01 1 |
| Sweep ADC channels 0 and 1. | |
| #define | ADC_SWEEP_012 2 |
| Sweep ADC channels 0, 1 and 2. | |
| #define | ADC_SWEEP_0123 3 |
| Sweep all ADC channels. | |
Bitfields in PRESCALER | |
|
| |
| #define | ADC_PRESCALER_START 0 |
| ADC clock prescaling. | |
| #define | ADC_PRESCALER_SIZE 3 |
| ADC clock prescaling. | |
PRESCALER bitfield values | |
|
| |
| #define | ADC_PRESCALER_DIV4 0 |
| Prescale peripheral clock by 4. | |
| #define | ADC_PRESCALER_DIV8 1 |
| Prescale peripheral clock by 8. | |
| #define | ADC_PRESCALER_DIV16 2 |
| Prescale peripheral clock by 16. | |
| #define | ADC_PRESCALER_DIV32 3 |
| Prescale peripheral clock by 32. | |
| #define | ADC_PRESCALER_DIV64 4 |
| Prescale peripheral clock by 64. | |
| #define | ADC_PRESCALER_DIV128 5 |
| Prescale peripheral clock by 128. | |
| #define | ADC_PRESCALER_DIV256 6 |
| Prescale peripheral clock by 256. | |
| #define | ADC_PRESCALER_DIV512 7 |
| Prescale peripheral clock by 512. | |
Bitfields in INTFLAGS | |
|
| |
| #define | ADC_CH0IF_BIT 0 |
| ADC channel 0 interrupt flag. | |
| #define | ADC_CH1IF_BIT 1 |
| ADC channel 1 interrupt flag. | |
| #define | ADC_CH2IF_BIT 2 |
| ADC channel 2 interrupt flag. | |
| #define | ADC_CH3IF_BIT 4 |
| ADC channel 3 interrupt flag. | |
Bit manipulation macros | |
|
| |
| #define | ADC_BIT(name) (1U << ADC_##name##_BIT) |
| Create a mask with bit name set. | |
| #define | ADC_BF(name, value) ((value) << ADC_##name##_START) |
| Create a mask with bitfield name set to value. | |
| #define | ADC_BFMASK(name) (((1U << ADC_##name##_SIZE) - 1) << ADC_##name##_START) |
| Create a mask of the bitfield name. | |
| #define | ADC_BFEXT(name, regval) |
| Extract the value of bitfield name from regval. | |
| #define | ADC_BFINS(name, value, regval) |
| Return regval with bitfield name set to value. | |
Register access macros | |
|
| |
| #define | adc_read_reg(base, reg) mmio_read8((void *)((uintptr_t)(base) + ADC_##reg)) |
| Read the value of register reg on ADC with base address base. | |
| #define | adc_write_reg(base, reg, value) mmio_write8((void *)((uintptr_t)(base) + ADC_##reg), (value)) |
| Write value to register reg on ADC with base address base. | |
Define Documentation
| #define ADC_BANDGAP_BIT 1 |
Enable bandgap for measurement.
Definition at line 122 of file xmega_adc.h.
| #define ADC_BF | ( | name, | |||
| value | ) | ((value) << ADC_##name##_START) |
Create a mask with bitfield name set to value.
Definition at line 216 of file xmega_adc.h.
Referenced by touch_priv_adc_init(), and touch_priv_adc_start().
| #define ADC_BFEXT | ( | name, | |||
| regval | ) |
(((regval) >> ADC_##name##_START) \
& ((1U << ADC_##name##_SIZE) - 1))
Extract the value of bitfield name from regval.
Definition at line 222 of file xmega_adc.h.
| #define ADC_BFINS | ( | name, | |||
| value, | |||||
| regval | ) |
(((regval) & ~(((1U << ADC_##name##_SIZE) - 1) \
<< ADC_##name##_START)) \
| ADC_BF(name, value))
Return regval with bitfield name set to value.
Definition at line 226 of file xmega_adc.h.
| #define ADC_BFMASK | ( | name | ) | (((1U << ADC_##name##_SIZE) - 1) << ADC_##name##_START) |
Create a mask of the bitfield name.
Definition at line 219 of file xmega_adc.h.
Referenced by board_disable_touch_adc().
| #define ADC_BIT | ( | name | ) | (1U << ADC_##name##_BIT) |
Create a mask with bit name set.
Definition at line 213 of file xmega_adc.h.
Referenced by board_disable_touch_adc(), touch_priv_adc_clear_int_flag(), touch_priv_adc_init(), and touch_priv_adc_start().
| #define ADC_CALH 0x0D |
ADC calibration high byte.
Definition at line 63 of file xmega_adc.h.
| #define ADC_CALL 0x0C |
ADC calibration low byte.
Definition at line 62 of file xmega_adc.h.
| #define ADC_CH0IF_BIT 0 |
ADC channel 0 interrupt flag.
Definition at line 204 of file xmega_adc.h.
| #define ADC_CH0RESH 0x11 |
ADC channel 0 result high byte.
Definition at line 66 of file xmega_adc.h.
| #define ADC_CH0RESL 0x10 |
ADC channel 0 result low byte.
Definition at line 65 of file xmega_adc.h.
| #define ADC_CH1IF_BIT 1 |
ADC channel 1 interrupt flag.
Definition at line 205 of file xmega_adc.h.
| #define ADC_CH1RESH 0x13 |
ADC channel 1 result high byte.
Definition at line 68 of file xmega_adc.h.
| #define ADC_CH1RESL 0x12 |
ADC channel 1 result low byte.
Definition at line 67 of file xmega_adc.h.
| #define ADC_CH2IF_BIT 2 |
ADC channel 2 interrupt flag.
Definition at line 206 of file xmega_adc.h.
| #define ADC_CH2RESH 0x15 |
ADC channel 2 result high byte.
Definition at line 70 of file xmega_adc.h.
| #define ADC_CH2RESL 0x14 |
ADC channel 2 result low byte.
Definition at line 69 of file xmega_adc.h.
| #define ADC_CH3IF_BIT 4 |
ADC channel 3 interrupt flag.
Definition at line 207 of file xmega_adc.h.
| #define ADC_CH3RESH 0x17 |
ADC channel 3 result high byte.
Definition at line 72 of file xmega_adc.h.
| #define ADC_CH3RESL 0x16 |
ADC channel 3 result low byte.
Definition at line 71 of file xmega_adc.h.
| #define ADC_CHSTART_0 1 |
Start conversion on ADC channel 0.
Definition at line 90 of file xmega_adc.h.
Referenced by touch_priv_adc_start().
| #define ADC_CHSTART_1 2 |
Start conversion on ADC channel 1.
Definition at line 91 of file xmega_adc.h.
Referenced by touch_priv_adc_start().
| #define ADC_CHSTART_2 4 |
Start conversion on ADC channel 2.
Definition at line 92 of file xmega_adc.h.
| #define ADC_CHSTART_3 8 |
Start conversion on ADC channel 3.
Definition at line 93 of file xmega_adc.h.
| #define ADC_CHSTART_SIZE 4 |
ADC channel start single conversion.
Definition at line 83 of file xmega_adc.h.
| #define ADC_CHSTART_START 2 |
ADC channel start single conversion.
Definition at line 82 of file xmega_adc.h.
| #define ADC_CMPH 0x19 |
ADC compare high byte.
Definition at line 74 of file xmega_adc.h.
| #define ADC_CMPL 0x18 |
ADC compare low byte.
Definition at line 73 of file xmega_adc.h.
| #define ADC_CONVMODE_BIT 4 |
ADC signed/unsigned conversion mode.
Definition at line 109 of file xmega_adc.h.
| #define ADC_CTRLA 0x00 |
Control register A.
Definition at line 53 of file xmega_adc.h.
| #define ADC_CTRLB 0x01 |
Control register B.
Definition at line 54 of file xmega_adc.h.
| #define ADC_DMASEL_CH01 1 |
ADC channel 0 and 1 can trigger DMA.
Definition at line 99 of file xmega_adc.h.
| #define ADC_DMASEL_CH012 2 |
ADC channel 0, 1 and 2 can trigger DMA.
Definition at line 100 of file xmega_adc.h.
| #define ADC_DMASEL_CH0123 3 |
All ADC channels can trigger DMA.
Definition at line 101 of file xmega_adc.h.
| #define ADC_DMASEL_OFF 0 |
No combined DMA request.
Definition at line 98 of file xmega_adc.h.
| #define ADC_DMASEL_SIZE 2 |
ADC channel DMA request selection.
Definition at line 85 of file xmega_adc.h.
| #define ADC_DMASEL_START 6 |
ADC channel DMA request selection.
Definition at line 84 of file xmega_adc.h.
| #define ADC_ENABLE_BIT 0 |
ADC enable.
Definition at line 79 of file xmega_adc.h.
| #define ADC_EVACT_CH0 1 |
Lowest event line triggers conversion on ADC channel 0.
Definition at line 151 of file xmega_adc.h.
| #define ADC_EVACT_CH01 2 |
Two lowest event lines trigger conversions on ADC channels 0 and 1.
Definition at line 153 of file xmega_adc.h.
| #define ADC_EVACT_CH012 3 |
Three lowest event lines trigger conversions on ADC channels 0, 1 and 2.
Definition at line 155 of file xmega_adc.h.
| #define ADC_EVACT_CH0123 4 |
All event lines trigger conversions on the respective ADC channels.
Definition at line 157 of file xmega_adc.h.
| #define ADC_EVACT_NONE 0 |
< No event action
Definition at line 149 of file xmega_adc.h.
| #define ADC_EVACT_SIZE 3 |
ADC event mode.
Definition at line 139 of file xmega_adc.h.
| #define ADC_EVACT_START 0 |
ADC event mode.
Definition at line 138 of file xmega_adc.h.
| #define ADC_EVACT_SWEEP 5 |
Lowest event line triggers channel sweep.
Definition at line 159 of file xmega_adc.h.
| #define ADC_EVACT_SYNCSWEEP 6 |
Lowest event line triggers channel sweep with synchronization.
Definition at line 161 of file xmega_adc.h.
| #define ADC_EVCTRL 0x03 |
Event control.
Definition at line 56 of file xmega_adc.h.
| #define ADC_EVSEL_0123 0 |
Event channels 0, 1, 2 and 3 as event lines.
Definition at line 166 of file xmega_adc.h.
| #define ADC_EVSEL_1234 1 |
Event channels 1, 2, 3 and 4 as event lines.
Definition at line 167 of file xmega_adc.h.
| #define ADC_EVSEL_2345 2 |
Event channels 2, 3, 4 and 5 as event lines.
Definition at line 168 of file xmega_adc.h.
| #define ADC_EVSEL_3456 3 |
Event channels 3, 4, 5 and 6 as event lines.
Definition at line 169 of file xmega_adc.h.
| #define ADC_EVSEL_4567 4 |
Event channels 4, 5, 6 and 7 as event lines.
Definition at line 170 of file xmega_adc.h.
| #define ADC_EVSEL_567 5 |
Event channels 5, 6, and 7 as event lines.
Definition at line 171 of file xmega_adc.h.
| #define ADC_EVSEL_67 6 |
Event channels 6 and 7 as event lines.
Definition at line 172 of file xmega_adc.h.
| #define ADC_EVSEL_7 7 |
Event channel 7 as event line.
Definition at line 173 of file xmega_adc.h.
| #define ADC_EVSEL_SIZE 3 |
ADC event line selection.
Definition at line 141 of file xmega_adc.h.
| #define ADC_EVSEL_START 3 |
ADC event line selection.
Definition at line 140 of file xmega_adc.h.
| #define ADC_FLUSH_BIT 1 |
ADC flush.
Definition at line 80 of file xmega_adc.h.
| #define ADC_FREERUN_BIT 3 |
ADC free running mode.
Definition at line 108 of file xmega_adc.h.
| #define ADC_INTFLAGS 0x06 |
Interrupt flags for ADC channels.
Definition at line 59 of file xmega_adc.h.
| #define ADC_PRESCALER 0x04 |
ADC clock prescaling.
Definition at line 57 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV128 5 |
Prescale peripheral clock by 128.
Definition at line 197 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV16 2 |
Prescale peripheral clock by 16.
Definition at line 194 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV256 6 |
Prescale peripheral clock by 256.
Definition at line 198 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV32 3 |
Prescale peripheral clock by 32.
Definition at line 195 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV4 0 |
Prescale peripheral clock by 4.
Definition at line 192 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV512 7 |
Prescale peripheral clock by 512.
Definition at line 199 of file xmega_adc.h.
Referenced by touch_priv_adc_init().
| #define ADC_PRESCALER_DIV64 4 |
Prescale peripheral clock by 64.
Definition at line 196 of file xmega_adc.h.
| #define ADC_PRESCALER_DIV8 1 |
Prescale peripheral clock by 8.
Definition at line 193 of file xmega_adc.h.
| #define ADC_PRESCALER_SIZE 3 |
ADC clock prescaling.
Definition at line 187 of file xmega_adc.h.
| #define ADC_PRESCALER_START 0 |
ADC clock prescaling.
Definition at line 186 of file xmega_adc.h.
| #define adc_read_reg | ( | base, | |||
| reg | ) | mmio_read8((void *)((uintptr_t)(base) + ADC_##reg)) |
Read the value of register reg on ADC with base address base.
Definition at line 235 of file xmega_adc.h.
Referenced by board_disable_touch_adc(), and touch_priv_adc_get_x().
| #define ADC_REFCTRL 0x02 |
Reference control.
Definition at line 55 of file xmega_adc.h.
| #define ADC_REFSEL_AREFA 2 |
External reference from AREFA.
Definition at line 132 of file xmega_adc.h.
| #define ADC_REFSEL_AREFB 3 |
External reference from AREFB.
Definition at line 133 of file xmega_adc.h.
| #define ADC_REFSEL_INT1V 0 |
Internal 1.00 V as reference.
Definition at line 130 of file xmega_adc.h.
| #define ADC_REFSEL_INTVCC 1 |
Internal VCC/1.6 V as reference.
Definition at line 131 of file xmega_adc.h.
Referenced by touch_priv_adc_init().
| #define ADC_REFSEL_SIZE 2 |
ADC reference selection.
Definition at line 125 of file xmega_adc.h.
| #define ADC_REFSEL_START 4 |
ADC reference selection.
Definition at line 124 of file xmega_adc.h.
| #define ADC_RESOLUTION_12BIT 0 |
12-bit result, right adjusted
Definition at line 114 of file xmega_adc.h.
Referenced by touch_priv_adc_init().
| #define ADC_RESOLUTION_8BIT 2 |
8-bit result, right adjusted
Definition at line 115 of file xmega_adc.h.
| #define ADC_RESOLUTION_LEFT12BIT 3 |
12-bit result, left adjusted
Definition at line 116 of file xmega_adc.h.
| #define ADC_RESOLUTION_SIZE 2 |
ADC conversion resolution.
Definition at line 107 of file xmega_adc.h.
| #define ADC_RESOLUTION_START 1 |
ADC conversion resolution.
Definition at line 106 of file xmega_adc.h.
| #define ADC_SWEEP_0 0 |
Sweep ADC channel 0 only.
Definition at line 178 of file xmega_adc.h.
| #define ADC_SWEEP_01 1 |
Sweep ADC channels 0 and 1.
Definition at line 179 of file xmega_adc.h.
| #define ADC_SWEEP_012 2 |
Sweep ADC channels 0, 1 and 2.
Definition at line 180 of file xmega_adc.h.
| #define ADC_SWEEP_0123 3 |
Sweep all ADC channels.
Definition at line 181 of file xmega_adc.h.
| #define ADC_SWEEP_SIZE 2 |
ADC channel sweep selection.
Definition at line 143 of file xmega_adc.h.
| #define ADC_SWEEP_START 6 |
ADC channel sweep selection.
Definition at line 142 of file xmega_adc.h.
| #define ADC_TEMP 0x07 |
Temporary register for 16-bit reads.
Definition at line 60 of file xmega_adc.h.
| #define ADC_TEMPREF_BIT 0 |
Enable temperature reference for measurement.
Definition at line 121 of file xmega_adc.h.
| #define adc_write_reg | ( | base, | |||
| reg, | |||||
| value | ) | mmio_write8((void *)((uintptr_t)(base) + ADC_##reg), (value)) |
Write value to register reg on ADC with base address base.
Definition at line 238 of file xmega_adc.h.
Referenced by board_disable_touch_adc(), touch_priv_adc_clear_int_flag(), touch_priv_adc_init(), and touch_priv_adc_start().
