chip/atxmega128a1/include/chip/pll.h

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#ifndef CHIP_PLL_H_INCLUDED
#define CHIP_PLL_H_INCLUDED

#include <assert.h>
#include <clk/osc.h>
#include <regs/xmega_osc.h>
#include <status_codes.h>
#include <stdint.h>

#define NR_PLLS                         1

#define PLL_MIN_HZ                      10000000UL
#define PLL_MAX_HZ                      200000000UL

enum pll_source {
        PLL_SRC_RC2MHZ          = 0,    
        PLL_SRC_RC32MHZ         = 2,    
        PLL_SRC_XOSC            = 3,    
        PLL_NR_SOURCES,                 
};

#define pll_get_default_rate(pll_id)                            \
        ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE)             \
                        * CONFIG_PLL##pll_id##_MUL)             \
                / CONFIG_PLL##pll_id##_DIV)

struct pll_config {
        uint8_t ctrl;
};

static inline void pll_config_init(struct pll_config *cfg,
                enum pll_source src, unsigned int div, unsigned int mul)
{
        /* Verify that all parameters are supported by hardware */
        assert(src < PLL_NR_SOURCES && src != 1);
        assert(mul >= 1 && mul <= 31);
        assert(osc_get_rate(src) >= 400000);
        assert(osc_get_rate(src) * mul <= PLL_MAX_HZ);

        if (src == PLL_SRC_RC32MHZ)
                assert(div == 4);
        else
                assert(div == 1);

        /* Initialize the configuration */
        cfg->ctrl = OSC_BF(PLLSRC, src) | OSC_BF(PLLFAC, mul);
}

#define pll_config_defaults(cfg, pll_id)                                \
        pll_config_init(cfg,                                            \
                        CONFIG_PLL##pll_id##_SOURCE,                    \
                        CONFIG_PLL##pll_id##_DIV,                       \
                        CONFIG_PLL##pll_id##_MUL)

static inline void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
{
        assert(pll_id < NR_PLLS);

        cfg->ctrl = osc_read_reg(PLLCTRL);
}

static inline void pll_config_write(const struct pll_config *cfg,
                unsigned int pll_id)
{
        assert(pll_id < NR_PLLS);

        osc_write_reg(PLLCTRL, cfg->ctrl);
}

static inline void pll_enable(const struct pll_config *cfg,
                unsigned int pll_id)
{
        uint8_t osc_ctrl;

        pll_config_write(cfg, pll_id);
        osc_ctrl = osc_read_reg(CTRL);
        osc_ctrl |= OSC_BIT(PLLEN);
        osc_write_reg(CTRL, osc_ctrl);
}

static inline void pll_disable(unsigned int pll_id)
{
        uint8_t osc_ctrl;

        assert(pll_id < NR_PLLS);

        osc_ctrl = osc_read_reg(CTRL);
        osc_ctrl &= ~OSC_BIT(PLLEN);
        osc_write_reg(CTRL, osc_ctrl);
}

static inline status_t pll_wait_for_lock(unsigned int pll_id)
{
        assert(pll_id < NR_PLLS);

        while (!(osc_read_reg(STATUS) & OSC_BIT(PLLRDY))) {
                /* Do nothing */
        }

        return STATUS_OK;
}


#endif /* CHIP_PLL_H_INCLUDED */

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