00001
00038 #ifndef FLASH_AT45_H_INCLUDED
00039 #define FLASH_AT45_H_INCLUDED
00040
00065 #define AT45_PS_256 (0 << 0) //!< Page size 256 bytes
00066 #define AT45_PS_512 (1 << 0) //!< Page size 512 bytes
00067 #define AT45_PS_1024 (2 << 0) //!< Page size 1024 bytes
00068 #define AT45_PS_MASK (7 << 0) //!< Page size mask bits
00069 #define AT45_SS_128P (0 << 3) //!< Sector size 128 pages
00070 #define AT45_SS_256P (1 << 3) //!< Sector size 256 bytes
00071 #define AT45_SS_MASK (3 << 3) //!< Sector size mask bits
00072 #define AT45_DS_4S (0 << 4) //!< Device size 4 sectors
00073 #define AT45_DS_8S (1 << 4) //!< Device size 8 sectors
00074 #define AT45_DS_16S (2 << 4) //!< Device size 16 sectors
00075 #define AT45_DS_32S (3 << 4) //!< Device size 32 sectors
00076 #define AT45_DS_64S (4 << 4) //!< Device size 64 sectors
00077 #define AT45_DS_MASK (7 << 4) //!< Device size mask bits
00078
00079
00087
00088 #define AT45DB011D (AT45_PS_256 | AT45_SS_128P | AT45_DS_4S)
00089
00090 #define AT45DB021D (AT45_PS_256 | AT45_SS_128P | AT45_DS_8S)
00091
00092 #define AT45DB041D (AT45_PS_256 | AT45_SS_256P | AT45_DS_8S)
00093
00094 #define AT45DB081D (AT45_PS_256 | AT45_SS_256P | AT45_DS_16S)
00095
00096 #define AT45DB161D (AT45_PS_512 | AT45_SS_256P | AT45_DS_16S)
00097
00098 #define AT45DB321D (AT45_PS_512 | AT45_SS_128P | AT45_DS_64S)
00099
00100 #define AT45DB642D (AT45_PS_1024 | AT45_SS_256P | AT45_DS_32S)
00101
00102
00104 enum at45_cmd {
00106 AT45_CMD_CONTINOUS_ARRAY_READ = 0x0b,
00108 AT45_CMD_MAIN_MEMORY_TO_BUFFER_1_TRANSFER = 0x53,
00110 AT45_CMD_BUFFER_1_MAIN_MEMORY_PROGRAM_WITH_ERASE = 0x83,
00112 AT45_CMD_BUFFER_1_WRITE = 0x84,
00114 AT45_CMD_READ_ID = 0x9f,
00116 AT45_CMD_READ_STATUS_REG = 0xd7,
00117 };
00118
00120 enum at45_status_bit {
00121 AT45_STATUS_PAGE_SIZE = 0,
00122 AT45_STATUS_PROTECT = 1,
00123 AT45_STATUS_COMP = 6,
00124 AT45_STATUS_RDY = 7,
00125 };
00126
00128 #define AT45_PAGE_ADDR_MASK ((1 << 13) - 1)
00129
00131 #define AT45_PAGE_POS_MASK ((1 << 11) - 1)
00132
00134 #define AT45_ATMEL_JEDEC_ID 0x1f
00135
00137 #define AT45_DATAFLASH_FAMILY_CODE 0x20
00138
00140 #define AT45_FAMILY_CODE_MASK 0xe0
00141
00143 #define AT45_DENSITY_CODE_MIN 2
00144
00146 #define AT45_DENSITY_CODE_MAX 8
00147
00149 #define AT45_DENSITY_CODE_MASK 0x1f
00150
00158 #define AT45_DENSITY_CODE_0_DEVICE_SIZE 0x8000L
00159
00161 #define AT45_PAGE_SIZE_ID_0_SIZE 256
00162
00169 static const uint8_t at45_density_table[] = {
00170 [2] = AT45DB011D,
00171 [3] = AT45DB021D,
00172 [4] = AT45DB041D,
00173 [5] = AT45DB081D,
00174 [6] = AT45DB161D,
00175 [7] = AT45DB321D,
00176 [8] = AT45DB642D,
00177 };
00178
00186 static inline bool at45_is_atmel_jedec_id(uint8_t manuf_id)
00187 {
00188 return manuf_id == AT45_ATMEL_JEDEC_ID;
00189 }
00190
00198 static inline bool at45_is_dataflash_family_code(uint8_t device_id1)
00199 {
00200 return (device_id1 & AT45_FAMILY_CODE_MASK)
00201 == AT45_DATAFLASH_FAMILY_CODE;
00202 }
00203
00210 static inline uint8_t at45_get_density_code(uint8_t device_id1)
00211 {
00212 return device_id1 & AT45_DENSITY_CODE_MASK;
00213 }
00214
00222 static inline bool at45_is_valid_density_code(uint8_t device_id1)
00223 {
00224 uint8_t density_code = at45_get_density_code(device_id1);
00225
00226 return (density_code >= AT45_DENSITY_CODE_MIN)
00227 && (density_code <= AT45_DENSITY_CODE_MAX);
00228 }
00229
00238 static inline bool at45_is_valid_id(uint8_t manuf_id, uint8_t device_id1)
00239 {
00240 return at45_is_atmel_jedec_id(manuf_id)
00241 && at45_is_dataflash_family_code(device_id1)
00242 && at45_is_valid_density_code(device_id1);
00243 }
00244
00251 static inline uint32_t at45_get_size(uint8_t device_id1)
00252 {
00253
00254 return AT45_DENSITY_CODE_0_DEVICE_SIZE
00255 << at45_get_density_code(device_id1);
00256 }
00257
00264 static inline uint32_t at45_get_page_size(uint8_t device_id1)
00265 {
00266 uint8_t density;
00267
00268 density = at45_density_table[at45_get_density_code(device_id1)];
00269
00270
00271
00272
00273 return AT45_PAGE_SIZE_ID_0_SIZE << (density & AT45_PS_MASK);
00274 }
00275
00277
00278 #endif