00001 00039 #ifndef TC_TC_XMEGA_H_INCLUDED 00040 #define TC_TC_XMEGA_H_INCLUDED 00041 00042 #include <assert.h> 00043 #include <stdint.h> 00044 #include <chip/memory-map.h> 00045 #include <chip/tc.h> 00046 00066 #define tc_get_regs(id) ((void *) (TC##id##_BASE)) 00067 00084 static inline uint8_t tc_select_clock(uint8_t tc_id, uint32_t resolution) 00085 { 00086 uint32_t tc_clk_rate = tc_get_pclk_hz(tc_id); 00087 00088 if (resolution <= (tc_clk_rate / 1024)) 00089 return TC_CLKSEL_DIV1024; 00090 else if (resolution <= (tc_clk_rate / 256)) 00091 return TC_CLKSEL_DIV256; 00092 else if (resolution <= (tc_clk_rate / 64)) 00093 return TC_CLKSEL_DIV64; 00094 else if (resolution <= (tc_clk_rate / 8)) 00095 return TC_CLKSEL_DIV8; 00096 else if (resolution <= (tc_clk_rate / 4)) 00097 return TC_CLKSEL_DIV4; 00098 else if (resolution <= (tc_clk_rate / 2)) 00099 return TC_CLKSEL_DIV2; 00100 else 00101 return TC_CLKSEL_DIV1; 00102 } 00103 00118 static inline uint32_t tc_get_resolution(uint8_t tc_id, uint8_t clksel) 00119 { 00120 uint32_t clock_rate = tc_get_pclk_hz(tc_id); 00121 00122 switch(clksel) { 00123 case TC_CLKSEL_OFF: 00124 clock_rate = 0; 00125 break; 00126 00127 case TC_CLKSEL_DIV1024: 00128 clock_rate /= 1024; 00129 break; 00130 00131 case TC_CLKSEL_DIV256: 00132 clock_rate /= 256; 00133 break; 00134 00135 case TC_CLKSEL_DIV64: 00136 clock_rate /= 64; 00137 break; 00138 00139 case TC_CLKSEL_DIV8: 00140 clock_rate /= 8; 00141 break; 00142 00143 case TC_CLKSEL_DIV4: 00144 clock_rate /= 4; 00145 break; 00146 00147 case TC_CLKSEL_DIV2: 00148 clock_rate /= 2; 00149 break; 00150 00151 case TC_CLKSEL_DIV1: 00152 break; 00153 00154 default: 00155 unhandled_case(clksel); 00156 break; 00157 } 00158 00159 return clock_rate; 00160 } 00161 00163 #endif /* TC_TC_XMEGA_H_INCLUDED */
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