drivers/tc/timer/tc_timer_xmega.c

Go to the documentation of this file.

#include <timer/tc_timer_xmega.h>
#include <assert.h>
#include <interrupt.h>
#include <intc.h>
#include <regs/xmega_tc.h>
#include <chip/tc.h>
#include <pmic.h>

static void tc_timer_irq_handler(void *int_data)
{
        struct timer *timer = (struct timer *)int_data;

        assert(timer);

        tc_write_reg8(timer->regs, INTCTRLB, TC_BF(INTCTRLB_CCAINTLVL,
                        PMIC_INTLVL_OFF));

        if (timer->callback)
                timer->callback(timer);
}

// Set interrupt handler for the available and configured compare interrupts.
#if (defined(TC0_BASE) && defined(CONFIG_TIMER_0)) || defined(__DOXYGEN__)
INTC_DEFINE_HANDLER(PMIC_TC0_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC0_CCA);
#endif

#if defined(TC1_BASE) && defined(CONFIG_TIMER_1)
INTC_DEFINE_HANDLER(PMIC_TC1_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC1_CCA);
#endif

#if defined(TC2_BASE) && defined(CONFIG_TIMER_2)
INTC_DEFINE_HANDLER(PMIC_TC2_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC2_CCA);
#endif

#if defined(TC3_BASE) && defined(CONFIG_TIMER_3)
INTC_DEFINE_HANDLER(PMIC_TC3_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC3_CCA);
#endif

#if defined(TC4_BASE) && defined(CONFIG_TIMER_4)
INTC_DEFINE_HANDLER(PMIC_TC4_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC4_CCA);
#endif

#if defined(TC5_BASE) && defined(CONFIG_TIMER_5)
INTC_DEFINE_HANDLER(PMIC_TC5_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC5_CCA);
#endif

#if defined(TC6_BASE) && defined(CONFIG_TIMER_6)
INTC_DEFINE_HANDLER(PMIC_TC6_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC6_CCA);
#endif

#if defined(TC7_BASE) && defined(CONFIG_TIMER_7)
INTC_DEFINE_HANDLER(PMIC_TC7_CCA_IRQ, tc_timer_irq_handler,
                CONFIG_INTLVL_TC7_CCA);
#endif

void tc_timer_init(uint8_t tc_id, void *regs, struct timer *timer,
                timer_callback_t callback)
{
        assert(regs);
        assert(timer);

        timer->regs = regs;
        timer->callback = callback;
        timer->clksel = tc_select_clock(tc_id,
                        (uint32_t)CONFIG_TIMER_RESOLUTION);

        tc_enable_pclk(tc_id);
        tc_write_reg8(regs, CTRLA, TC_CLKSEL_OFF);
        tc_write_reg8(regs, CTRLFSET, TC_BF(CMD, TC_CMD_RESET));
        tc_write_reg8(regs, CTRLB, TC_BIT(CTRLB_CCAEN));
        tc_disable_pclk(tc_id);

        switch (tc_id) {
#if (defined(TC0_BASE) && defined(CONFIG_TIMER_0)) || defined(__DOXYGEN__)
        case 0:
                intc_set_irq_data(PMIC_TC0_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC0_CCA;
                break;
#endif

#if defined(TC1_BASE) && defined(CONFIG_TIMER_1)
        case 1:
                intc_set_irq_data(PMIC_TC1_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC1_CCA;
                break;
#endif

#if defined(TC2_BASE) && defined(CONFIG_TIMER_2)
        case 2:
                intc_set_irq_data(PMIC_TC2_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC2_CCA;
                break;
#endif

#if defined(TC3_BASE) && defined(CONFIG_TIMER_3)
        case 3:
                intc_set_irq_data(PMIC_TC3_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC3_CCA;
                break;
#endif

#if defined(TC4_BASE) && defined(CONFIG_TIMER_4)
        case 4:
                intc_set_irq_data(PMIC_TC4_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC4_CCA;
                break;
#endif

#if defined(TC5_BASE) && defined(CONFIG_TIMER_5)
        case 5:
                intc_set_irq_data(PMIC_TC5_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC5_CCA;
                break;
#endif

#if defined(TC6_BASE) && defined(CONFIG_TIMER_6)
        case 6:
                intc_set_irq_data(PMIC_TC6_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC6_CCA;
                break;
#endif

#if defined(TC7_BASE) && defined(CONFIG_TIMER_7)
        case 7:
                intc_set_irq_data(PMIC_TC7_CCA_IRQ, timer);
                timer->intlvl = CONFIG_INTLVL_TC7_CCA;
                break;
#endif

        default:
                unhandled_case(tc_id);
        }
}

timer_res_t tc_timer_set_resolution(uint8_t tc_id, uint32_t resolution)
{
        return tc_select_clock(tc_id, resolution);
}

uint32_t tc_timer_get_resolution(uint8_t tc_id, timer_res_t timer_res)
{
        return tc_get_resolution(tc_id, timer_res);
}

void tc_timer_write_resolution(uint8_t tc_id, struct timer *timer,
                timer_res_t timer_res)
{
        assert(timer);
        assert(timer->regs);

        timer->clksel = timer_res;
        tc_write_reg8(timer->regs, CTRLA, timer_res);
}

void tc_timer_start(uint8_t tc_id, struct timer *timer)
{
        assert(timer->regs);

        tc_enable_pclk(tc_id);

        // Reset TC value, then start counting.
        tc_write_reg8(timer->regs, CTRLFSET, TC_BF(CMD, TC_CMD_RESTART));
        tc_write_reg8(timer->regs, CTRLA, timer->clksel);
}

void tc_timer_set_alarm(uint8_t tc_id, struct timer *timer, uint16_t delay)
{
        irqflags_t flags;
        bool enabled;
        uint16_t start;

        assert(timer);
        assert(timer->regs);

        // Disable any current alarms.
        tc_write_reg8(timer->regs, INTCTRLB, TC_BF(INTCTRLB_CCAINTLVL,
                        PMIC_INTLVL_OFF));

        // TC must be stopped to be sure to avoid "overshoots" of delays.
        enabled = tc_pclk_is_enabled(tc_id);
        if (!enabled)
                tc_enable_pclk(tc_id);
        else
                tc_write_reg8(timer->regs, CTRLA, TC_CLKSEL_OFF);

        // Disable interrupts to prevent corruption of 16-bit read and writes.
        flags = cpu_irq_save();

        tc_write_reg8(timer->regs, INTFLAGS, TC_BIT(INTFLAGS_CCAIF));

        /* TC must be reset and started with \ref tc_timer_start() if disabled.
         * Set compare value accordingly.
         */
        if (!enabled)
                tc_write_reg16(timer->regs, CCA, delay);
        else {
                start = tc_read_reg16(timer->regs, CNT);
                tc_write_reg16(timer->regs, CCA, start + delay);
        }

        cpu_irq_restore(flags);

        tc_write_reg8(timer->regs, INTCTRLB, TC_BF(INTCTRLB_CCAINTLVL,
                        timer->intlvl));

        // Leave the TC in the state it was upon entry of this function.
        if (!enabled)
                tc_disable_pclk(tc_id);
        else
                tc_write_reg8(timer->regs, CTRLA, timer->clksel);
}

void tc_timer_stop(uint8_t tc_id, struct timer *timer)
{
        assert(timer);
        assert(timer->regs);

        // Disable compare interrupt, then stop and disable the TC.
        tc_write_reg8(timer->regs, INTCTRLB, TC_BF(INTCTRLB_CCAINTLVL,
                        PMIC_INTLVL_OFF));
        tc_write_reg8(timer->regs, CTRLA, TC_BF(CTRLA_CLKSEL, TC_CLKSEL_OFF));
        tc_disable_pclk(tc_id);
}

uint16_t tc_timer_get_time(uint8_t tc_id, struct timer *timer)
{
        bool enabled;
        irqflags_t flags;
        uint16_t time;

        assert(timer);
        assert(timer->regs);

        enabled = tc_pclk_is_enabled(tc_id);

        if (enabled) {
                // Disable interrupts to prevent corruption of 16-bit read.
                flags = cpu_irq_save();
                time = tc_read_reg16(timer->regs, CNT);
                cpu_irq_restore(flags);
        } else {
                time = 0;
        }

        return time;
}

---