XMEGA TC Register Definitions
[Internal Register Definitions]
|
Register Offsets | |
|
| |
| #define | TC_CTRLA 0x00 |
| Control Register A. | |
| #define | TC_CTRLB 0x01 |
| Control Register B. | |
| #define | TC_CTRLC 0x02 |
| Control Register C. | |
| #define | TC_CTRLD 0x03 |
| Control Register D. | |
| #define | TC_CTRLE 0x04 |
| Control Register E. | |
| #define | TC_INTCTRLA 0x06 |
| Interrupt Enable Register A. | |
| #define | TC_INTCTRLB 0x07 |
| Interrupt Enable Register B. | |
| #define | TC_CTRLFCRL 0x08 |
| Control Register F Clear. | |
| #define | TC_CTRLFSET 0x09 |
| Control Register F Set. | |
| #define | TC_CTRLGCLR 0x0a |
| Control Register G Clear. | |
| #define | TC_CTRLGSET 0x0b |
| Control Register G Set. | |
| #define | TC_INTFLAGS 0x0c |
| Interrupt Flag Register. | |
| #define | TC_TEMP 0x0f |
| Temporary Register for 16-bit Access. | |
| #define | TC_CNTL 0x20 |
| Counter Register H. | |
| #define | TC_CNTH 0x21 |
| Counter Register L. | |
| #define | TC_PERL 0x26 |
| Period Register H. | |
| #define | TC_PERH 0x27 |
| Period Register L. | |
| #define | TC_CCAL 0x28 |
| Compare or Capture Register A L. | |
| #define | TC_CCAH 0x29 |
| Compare or Capture Register A H. | |
| #define | TC_CCBL 0x2a |
| Compare or Capture Register B L. | |
| #define | TC_CCBH 0x2b |
| Compare or Capture Register B H. | |
| #define | TC_CCCL 0x2c |
| Compare or Capture Register C L. | |
| #define | TC_CCCH 0x2d |
| Compare or Capture Register C H. | |
| #define | TC_CCDL 0x2e |
| Compare or Capture Register D L. | |
| #define | TC_CCDH 0x2f |
| Compare or Capture Register D H. | |
| #define | TC_PERBUFL 0x36 |
| Timer/Counter Period Buffer L. | |
| #define | TC_PERBUFH 0x37 |
| Timer/Counter Period Buffer H. | |
| #define | TC_CCABUFL 0x38 |
| Compare or Capture A Buffer Register L. | |
| #define | TC_CCABUFH 0x39 |
| Compare or Capture A Buffer Register H. | |
| #define | TC_CCBBUFL 0x3a |
| Compare or Capture B Buffer Register L. | |
| #define | TC_CCBBUFH 0x3b |
| Compare or Capture B Buffer Register H. | |
| #define | TC_CCCBUFL 0x3c |
| Compare or Capture C Buffer Register L. | |
| #define | TC_CCCBUFH 0x3d |
| Compare or Capture C Buffer Register H. | |
| #define | TC_CCDBUFL 0x3e |
| Compare or Capture D Buffer Register L. | |
| #define | TC_CCDBUFH 0x3f |
| Compare or Capture D Buffer Register H. | |
CTRLA register bits | |
|
| |
| #define | TC_CTRLA_CLKSEL_START 0 |
| Clock Select. | |
| #define | TC_CTRLA_CLKSEL_SIZE 4 |
| Clock Select. | |
CTRLB register bits | |
|
| |
| #define | TC_CTRLB_WGMODE_START 0 |
| Waveform Generation Mode. | |
| #define | TC_CTRLB_WGMODE_SIZE 3 |
| Waveform Generation Mode. | |
| #define | TC_CTRLB_CCAEN_BIT 4 |
| Compare or Capture A Enable. | |
| #define | TC_CTRLB_CCBEN_BIT 5 |
| Compare or Capture B Enable. | |
| #define | TC_CTRLB_CCCEN_BIT 6 |
| Compare or Capture C Enable. | |
| #define | TC_CTRLB_CCDEN_BIT 7 |
| Compare or Capture D Enable. | |
CTRLC register bits | |
|
| |
| #define | TC_CTRLC_CMPA_BIT 0 |
| Compare Output Value A. | |
| #define | TC_CTRLC_CMPB_BIT 1 |
| Compare Output Value B. | |
| #define | TC_CTRLC_CMPC_BIT 2 |
| Compare Output Value C. | |
| #define | TC_CTRLC_CMPD_BIT 3 |
| Compare Output Value D. | |
CTRLD register bits | |
|
| |
| #define | TC_CTRLD_EVSEL_START 0 |
| Event Source Select. | |
| #define | TC_CTRLD_EVSEL_SIZE 4 |
| Event Source Select. | |
| #define | TC_CTRLD_EVDLY_BIT 4 |
| Timer Delay Event. | |
| #define | TC_CTRLD_EVACT_START 5 |
| Event Action. | |
| #define | TC_CTRLD_EVACT_SIZE 3 |
| Event Action. | |
CTRLE register bits | |
|
| |
| #define | TC_CTRLE_BYTEM_BIT 0 |
| Byte Mode. | |
INTCTRLA register bits | |
|
| |
| #define | TC_INTCTRLA_OVFINTLVL_START 0 |
| Timer Overflow/Underflow Interrupt Level. | |
| #define | TC_INTCTRLA_OVFINTLVL_SIZE 2 |
| Timer Overflow/Underflow Interrupt Level. | |
| #define | TC_INTCTRLA_ERRINTLVL_START 2 |
| Timer Error Interrupt Level. | |
| #define | TC_INTCTRLA_ERRINTLVL_SIZE 2 |
| Timer Error Interrupt Level. | |
INTCTRLB register bits | |
|
| |
| #define | TC_INTCTRLB_CCAINTLVL_START 0 |
| Compare or Capture A Interrupt Level. | |
| #define | TC_INTCTRLB_CCAINTLVL_SIZE 2 |
| Compare or Capture A Interrupt Level. | |
| #define | TC_INTCTRLB_CCBINTLVL_START 2 |
| Compare or Capture B Interrupt Level. | |
| #define | TC_INTCTRLB_CCBINTLVL_SIZE 2 |
| Compare or Capture B Interrupt Level. | |
| #define | TC_INTCTRLB_CCCINTLVL_START 4 |
| Compare or Capture C Interrupt Level. | |
| #define | TC_INTCTRLB_CCCINTLVL_SIZE 2 |
| Compare or Capture C Interrupt Level. | |
| #define | TC_INTCTRLB_CCDINTLVL_START 6 |
| Compare or Capture D Interrupt Level. | |
| #define | TC_INTCTRLB_CCDINTLVL_SIZE 2 |
| Compare or Capture D Interrupt Level. | |
CTRLFCLR and CTRLCSET register bits | |
|
| |
| #define | TC_DIR_BIT 0 |
| Counter Direction. | |
| #define | TC_LUPD_BIT 1 |
| Lock Update. | |
| #define | TC_CMD_START 2 |
| Timer/Counter Command. | |
| #define | TC_CMD_SIZE 2 |
| Timer/Counter Command. | |
CTRLGCLR and CTRLGSET register bits | |
|
| |
| #define | TC_PERBV_BIT 0 |
| Period Buffer Valid. | |
| #define | TC_CCABV_BIT 1 |
| Compare or Capture A Buffer Valid. | |
| #define | TC_CCBBV_BIT 2 |
| Compare or Capture B Buffer Valid. | |
| #define | TC_CCCBV_BIT 3 |
| Compare or Capture C Buffer Valid. | |
| #define | TC_CCDBV_BIT 4 |
| Compare or Capture D Buffer Valid. | |
INTFLAGS register bits | |
|
| |
| #define | TC_INTFLAGS_OVFIF_BIT 0 |
| #define | TC_INTFLAGS_ERRIF_BIT 1 |
| #define | TC_INTFLAGS_CCAIF_BIT 4 |
| #define | TC_INTFLAGS_CCBIF_BIT 5 |
| #define | TC_INTFLAGS_CCCIF_BIT 6 |
| #define | TC_INTFLAGS_CCDIF_BIT 7 |
CTRLA_CLKSEL Bitfield Values | |
|
| |
| #define | TC_CLKSEL_OFF 0x0 |
| None, Timer/Counter is in off state. | |
| #define | TC_CLKSEL_DIV1 0x1 |
| Prescaler: clk. | |
| #define | TC_CLKSEL_DIV2 0x2 |
| Prescaler: clk/2. | |
| #define | TC_CLKSEL_DIV4 0x3 |
| Prescaler: clk/4. | |
| #define | TC_CLKSEL_DIV8 0x4 |
| Prescaler: clk/8. | |
| #define | TC_CLKSEL_DIV64 0x5 |
| Prescaler: clk/64. | |
| #define | TC_CLKSEL_DIV256 0x6 |
| Prescaler: clk/256. | |
| #define | TC_CLKSEL_DIV1024 0x7 |
| Prescaler: clk/1024. | |
| #define | TC_CLKSEL_EVCHAN0 0x8 |
| Event Channel 0. | |
| #define | TC_CLKSEL_EVCHAN1 0x9 |
| Event Channel 1. | |
| #define | TC_CLKSEL_EVCHAN2 0xa |
| Event Channel 2. | |
| #define | TC_CLKSEL_EVCHAN3 0xb |
| Event Channel 3. | |
| #define | TC_CLKSEL_EVCHAN4 0xc |
| Event Channel 4. | |
| #define | TC_CLKSEL_EVCHAN5 0xd |
| Event Channel 5. | |
| #define | TC_CLKSEL_EVCHAN6 0xe |
| Event Channel 6. | |
| #define | TC_CLKSEL_EVCHAN7 0xf |
| Event Channel 7. | |
CTRLB_WGMODE Bitfield Values | |
|
| |
| #define | TC_WGMODE_NORMAL 0x0 |
| Normal. | |
| #define | TC_WGMODE_FRQ 0x1 |
| Frequency. | |
| #define | TC_WGMODE_SS 0x3 |
| Single Slope PWM. | |
| #define | TC_WGMODE_DS_T 0x5 |
| Dual Slope PWM, Event on TOP. | |
| #define | TC_WGMODE_DS_TB 0x6 |
| Dual Slope PWM, Event on TOP and BOTTOM. | |
| #define | TC_WGMODE_DS_B 0x7 |
| Dual Slope PWM, Event on BOTTOM. | |
CTRLFCLR_CMD, CTRLFSET_CMD Bitfield Values | |
|
| |
| #define | TC_CMD_NONE 0x0 |
| None. | |
| #define | TC_CMD_UPDATE 0x1 |
| Force Update. | |
| #define | TC_CMD_RESTART 0x2 |
| Force Restart. | |
| #define | TC_CMD_RESET 0x3 |
| Force Hard Reset. | |
CTRLD_EVACT Bitfield Values | |
|
| |
| #define | TC_EVACT_OFF 0x0 |
| None. | |
| #define | TC_EVACT_CAPT 0x1 |
| Input Capture. | |
| #define | TC_EVACT_UPDOWN 0x2 |
| Externally Controlled Up/Down Count. | |
| #define | TC_EVACT_QDEC 0x3 |
| Quadrature Decode. | |
| #define | TC_EVACT_RESTART 0x4 |
| Restart Waveform Periode. | |
| #define | TC_EVACT_FRQ 0x5 |
| Frequency Capture. | |
| #define | TC_EVACT_PW 0x6 |
| Pulse Width Capture. | |
CTRLD_EVSEL Bitfield Values | |
|
| |
| #define | TC_EVSEL_OFF 0x0 |
| Off. | |
| #define | TC_EVSEL_CH0 0x8 |
| Channel 0. | |
| #define | TC_EVSEL_CH1 0x9 |
| Channel 1. | |
| #define | TC_EVSEL_CH2 0xa |
| Channel 2. | |
| #define | TC_EVSEL_CH3 0xb |
| Channel 3. | |
| #define | TC_EVSEL_CH4 0xc |
| Channel 4. | |
| #define | TC_EVSEL_CH5 0xd |
| Channel 5. | |
| #define | TC_EVSEL_CH6 0xe |
| Channel 6. | |
| #define | TC_EVSEL_CH7 0xf |
| Channel 7. | |
Bit manipulation macros | |
|
| |
| #define | TC_BIT(name) (1U << TC_##name##_BIT) |
| Create a mask with bit name set. | |
| #define | TC_BF(name, value) ((value) << TC_##name##_START) |
| Create a mask with bitfield name set to value. | |
| #define | TC_BFMASK(name) (((1U << TC_##name##_SIZE) - 1) << TC_##name##_START) |
| Create a mask of bitfield with name. | |
| #define | TC_BFEXT(name, regval) |
| Extract the value of bitfield name from regval. | |
| #define | TC_BFINS(name, value, regval) |
| Return regval with bitfield name set to value. | |
Register access macros | |
|
| |
| #define | tc_write_reg8(tc, reg, value) mmio_write8((void *) ((uintptr_t)(tc) + TC_##reg), value) |
| Write value to 8-bit TC register reg. | |
| #define | tc_read_reg8(tc, reg) mmio_read8((void *) ((uintptr_t)(tc) + TC_##reg)) |
| Read the value of 8-bit TC register reg. | |
| #define | tc_write_reg16(tc, reg, value) mmio_write16((void *) ((uintptr_t)(tc) + TC_##reg##L), value) |
| Write value to 16-bit TC register reg. | |
| #define | tc_read_reg16(tc, reg) mmio_read16((void *) ((uintptr_t)(tc) + TC_##reg##L)) |
| Read the value of 16-bit TC register reg. | |
Detailed Description
This is the register interface to the XMEGA TC. The registers are defined as offsets relative to the base address of the module, so they may be easily reused across several modules on the same chip, or across different types of chips.
Define Documentation
| #define TC_BF | ( | name, | |||
| value | ) | ((value) << TC_##name##_START) |
Create a mask with bitfield name set to value.
Definition at line 260 of file xmega_tc.h.
Referenced by tc_timer_init(), tc_timer_irq_handler(), tc_timer_set_alarm(), tc_timer_start(), and tc_timer_stop().
| #define TC_BFEXT | ( | name, | |||
| regval | ) |
(((regval) >> TC_##name##_START) \
& ((1U << TC_##name##_SIZE) - 1))
Extract the value of bitfield name from regval.
Definition at line 266 of file xmega_tc.h.
| #define TC_BFINS | ( | name, | |||
| value, | |||||
| regval | ) |
(((regval) & ~(((1U << TC_##name##_SIZE) - 1) \
<< TC_##name##_START)) \
| TC_BF(name, value))
Return regval with bitfield name set to value.
Definition at line 270 of file xmega_tc.h.
| #define TC_BFMASK | ( | name | ) | (((1U << TC_##name##_SIZE) - 1) << TC_##name##_START) |
Create a mask of bitfield with name.
Definition at line 263 of file xmega_tc.h.
| #define TC_BIT | ( | name | ) | (1U << TC_##name##_BIT) |
Create a mask with bit name set.
Definition at line 257 of file xmega_tc.h.
Referenced by tc_timer_init(), and tc_timer_set_alarm().
| #define TC_CCABUFH 0x39 |
Compare or Capture A Buffer Register H.
Definition at line 86 of file xmega_tc.h.
| #define TC_CCABUFL 0x38 |
Compare or Capture A Buffer Register L.
Definition at line 85 of file xmega_tc.h.
| #define TC_CCABV_BIT 1 |
Compare or Capture A Buffer Valid.
Definition at line 176 of file xmega_tc.h.
| #define TC_CCAH 0x29 |
Compare or Capture Register A H.
Definition at line 76 of file xmega_tc.h.
| #define TC_CCAL 0x28 |
Compare or Capture Register A L.
Definition at line 75 of file xmega_tc.h.
| #define TC_CCBBUFH 0x3b |
Compare or Capture B Buffer Register H.
Definition at line 88 of file xmega_tc.h.
| #define TC_CCBBUFL 0x3a |
Compare or Capture B Buffer Register L.
Definition at line 87 of file xmega_tc.h.
| #define TC_CCBBV_BIT 2 |
Compare or Capture B Buffer Valid.
Definition at line 177 of file xmega_tc.h.
| #define TC_CCBH 0x2b |
Compare or Capture Register B H.
Definition at line 78 of file xmega_tc.h.
| #define TC_CCBL 0x2a |
Compare or Capture Register B L.
Definition at line 77 of file xmega_tc.h.
| #define TC_CCCBUFH 0x3d |
Compare or Capture C Buffer Register H.
Definition at line 90 of file xmega_tc.h.
| #define TC_CCCBUFL 0x3c |
Compare or Capture C Buffer Register L.
Definition at line 89 of file xmega_tc.h.
| #define TC_CCCBV_BIT 3 |
Compare or Capture C Buffer Valid.
Definition at line 178 of file xmega_tc.h.
| #define TC_CCCH 0x2d |
Compare or Capture Register C H.
Definition at line 80 of file xmega_tc.h.
| #define TC_CCCL 0x2c |
Compare or Capture Register C L.
Definition at line 79 of file xmega_tc.h.
| #define TC_CCDBUFH 0x3f |
Compare or Capture D Buffer Register H.
Definition at line 92 of file xmega_tc.h.
| #define TC_CCDBUFL 0x3e |
Compare or Capture D Buffer Register L.
Definition at line 91 of file xmega_tc.h.
| #define TC_CCDBV_BIT 4 |
Compare or Capture D Buffer Valid.
Definition at line 179 of file xmega_tc.h.
| #define TC_CCDH 0x2f |
Compare or Capture Register D H.
Definition at line 82 of file xmega_tc.h.
| #define TC_CCDL 0x2e |
Compare or Capture Register D L.
Definition at line 81 of file xmega_tc.h.
| #define TC_CLKSEL_DIV1 0x1 |
Prescaler: clk.
Definition at line 195 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_DIV1024 0x7 |
Prescaler: clk/1024.
Definition at line 201 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_DIV2 0x2 |
Prescaler: clk/2.
Definition at line 196 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_DIV256 0x6 |
Prescaler: clk/256.
Definition at line 200 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_DIV4 0x3 |
Prescaler: clk/4.
Definition at line 197 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_DIV64 0x5 |
Prescaler: clk/64.
Definition at line 199 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_DIV8 0x4 |
Prescaler: clk/8.
Definition at line 198 of file xmega_tc.h.
Referenced by tc_get_resolution(), and tc_select_clock().
| #define TC_CLKSEL_EVCHAN0 0x8 |
Event Channel 0.
Definition at line 202 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN1 0x9 |
Event Channel 1.
Definition at line 203 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN2 0xa |
Event Channel 2.
Definition at line 204 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN3 0xb |
Event Channel 3.
Definition at line 205 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN4 0xc |
Event Channel 4.
Definition at line 206 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN5 0xd |
Event Channel 5.
Definition at line 207 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN6 0xe |
Event Channel 6.
Definition at line 208 of file xmega_tc.h.
| #define TC_CLKSEL_EVCHAN7 0xf |
Event Channel 7.
Definition at line 209 of file xmega_tc.h.
| #define TC_CLKSEL_OFF 0x0 |
None, Timer/Counter is in off state.
Definition at line 194 of file xmega_tc.h.
Referenced by tc_get_resolution(), tc_timer_init(), tc_timer_set_alarm(), and tc_timer_stop().
| #define TC_CMD_NONE 0x0 |
None.
Definition at line 224 of file xmega_tc.h.
| #define TC_CMD_RESET 0x3 |
| #define TC_CMD_RESTART 0x2 |
| #define TC_CMD_SIZE 2 |
Timer/Counter Command.
Definition at line 170 of file xmega_tc.h.
| #define TC_CMD_START 2 |
Timer/Counter Command.
Definition at line 169 of file xmega_tc.h.
| #define TC_CMD_UPDATE 0x1 |
Force Update.
Definition at line 225 of file xmega_tc.h.
| #define TC_CNTH 0x21 |
Counter Register L.
Definition at line 72 of file xmega_tc.h.
| #define TC_CNTL 0x20 |
Counter Register H.
Definition at line 71 of file xmega_tc.h.
| #define TC_CTRLA 0x00 |
Control Register A.
Definition at line 58 of file xmega_tc.h.
| #define TC_CTRLA_CLKSEL_SIZE 4 |
Clock Select.
Definition at line 98 of file xmega_tc.h.
| #define TC_CTRLA_CLKSEL_START 0 |
Clock Select.
Definition at line 97 of file xmega_tc.h.
| #define TC_CTRLB 0x01 |
Control Register B.
Definition at line 59 of file xmega_tc.h.
| #define TC_CTRLB_CCAEN_BIT 4 |
Compare or Capture A Enable.
Definition at line 105 of file xmega_tc.h.
| #define TC_CTRLB_CCBEN_BIT 5 |
Compare or Capture B Enable.
Definition at line 106 of file xmega_tc.h.
| #define TC_CTRLB_CCCEN_BIT 6 |
Compare or Capture C Enable.
Definition at line 107 of file xmega_tc.h.
| #define TC_CTRLB_CCDEN_BIT 7 |
Compare or Capture D Enable.
Definition at line 108 of file xmega_tc.h.
| #define TC_CTRLB_WGMODE_SIZE 3 |
Waveform Generation Mode.
Definition at line 104 of file xmega_tc.h.
| #define TC_CTRLB_WGMODE_START 0 |
Waveform Generation Mode.
Definition at line 103 of file xmega_tc.h.
| #define TC_CTRLC 0x02 |
Control Register C.
Definition at line 60 of file xmega_tc.h.
| #define TC_CTRLC_CMPA_BIT 0 |
Compare Output Value A.
Definition at line 113 of file xmega_tc.h.
| #define TC_CTRLC_CMPB_BIT 1 |
Compare Output Value B.
Definition at line 114 of file xmega_tc.h.
| #define TC_CTRLC_CMPC_BIT 2 |
Compare Output Value C.
Definition at line 115 of file xmega_tc.h.
| #define TC_CTRLC_CMPD_BIT 3 |
Compare Output Value D.
Definition at line 116 of file xmega_tc.h.
| #define TC_CTRLD 0x03 |
Control Register D.
Definition at line 61 of file xmega_tc.h.
| #define TC_CTRLD_EVACT_SIZE 3 |
Event Action.
Definition at line 125 of file xmega_tc.h.
| #define TC_CTRLD_EVACT_START 5 |
Event Action.
Definition at line 124 of file xmega_tc.h.
| #define TC_CTRLD_EVDLY_BIT 4 |
Timer Delay Event.
Definition at line 123 of file xmega_tc.h.
| #define TC_CTRLD_EVSEL_SIZE 4 |
Event Source Select.
Definition at line 122 of file xmega_tc.h.
| #define TC_CTRLD_EVSEL_START 0 |
Event Source Select.
Definition at line 121 of file xmega_tc.h.
| #define TC_CTRLE 0x04 |
Control Register E.
Definition at line 62 of file xmega_tc.h.
| #define TC_CTRLE_BYTEM_BIT 0 |
Byte Mode.
Definition at line 130 of file xmega_tc.h.
| #define TC_CTRLFCRL 0x08 |
Control Register F Clear.
Definition at line 65 of file xmega_tc.h.
| #define TC_CTRLFSET 0x09 |
Control Register F Set.
Definition at line 66 of file xmega_tc.h.
| #define TC_CTRLGCLR 0x0a |
Control Register G Clear.
Definition at line 67 of file xmega_tc.h.
| #define TC_CTRLGSET 0x0b |
Control Register G Set.
Definition at line 68 of file xmega_tc.h.
| #define TC_DIR_BIT 0 |
Counter Direction.
Definition at line 167 of file xmega_tc.h.
| #define TC_EVACT_CAPT 0x1 |
Input Capture.
Definition at line 233 of file xmega_tc.h.
| #define TC_EVACT_FRQ 0x5 |
Frequency Capture.
Definition at line 237 of file xmega_tc.h.
| #define TC_EVACT_OFF 0x0 |
None.
Definition at line 232 of file xmega_tc.h.
| #define TC_EVACT_PW 0x6 |
Pulse Width Capture.
Definition at line 238 of file xmega_tc.h.
| #define TC_EVACT_QDEC 0x3 |
Quadrature Decode.
Definition at line 235 of file xmega_tc.h.
| #define TC_EVACT_RESTART 0x4 |
Restart Waveform Periode.
Definition at line 236 of file xmega_tc.h.
| #define TC_EVACT_UPDOWN 0x2 |
Externally Controlled Up/Down Count.
Definition at line 234 of file xmega_tc.h.
| #define TC_EVSEL_CH0 0x8 |
Channel 0.
Definition at line 244 of file xmega_tc.h.
| #define TC_EVSEL_CH1 0x9 |
Channel 1.
Definition at line 245 of file xmega_tc.h.
| #define TC_EVSEL_CH2 0xa |
Channel 2.
Definition at line 246 of file xmega_tc.h.
| #define TC_EVSEL_CH3 0xb |
Channel 3.
Definition at line 247 of file xmega_tc.h.
| #define TC_EVSEL_CH4 0xc |
Channel 4.
Definition at line 248 of file xmega_tc.h.
| #define TC_EVSEL_CH5 0xd |
Channel 5.
Definition at line 249 of file xmega_tc.h.
| #define TC_EVSEL_CH6 0xe |
Channel 6.
Definition at line 250 of file xmega_tc.h.
| #define TC_EVSEL_CH7 0xf |
Channel 7.
Definition at line 251 of file xmega_tc.h.
| #define TC_EVSEL_OFF 0x0 |
Off.
Definition at line 243 of file xmega_tc.h.
| #define TC_INTCTRLA 0x06 |
Interrupt Enable Register A.
Definition at line 63 of file xmega_tc.h.
| #define TC_INTCTRLA_ERRINTLVL_SIZE 2 |
Timer Error Interrupt Level.
Definition at line 142 of file xmega_tc.h.
| #define TC_INTCTRLA_ERRINTLVL_START 2 |
Timer Error Interrupt Level.
Definition at line 140 of file xmega_tc.h.
| #define TC_INTCTRLA_OVFINTLVL_SIZE 2 |
Timer Overflow/Underflow Interrupt Level.
Definition at line 138 of file xmega_tc.h.
| #define TC_INTCTRLA_OVFINTLVL_START 0 |
Timer Overflow/Underflow Interrupt Level.
Definition at line 136 of file xmega_tc.h.
| #define TC_INTCTRLB 0x07 |
Interrupt Enable Register B.
Definition at line 64 of file xmega_tc.h.
| #define TC_INTCTRLB_CCAINTLVL_SIZE 2 |
Compare or Capture A Interrupt Level.
Definition at line 150 of file xmega_tc.h.
| #define TC_INTCTRLB_CCAINTLVL_START 0 |
Compare or Capture A Interrupt Level.
Definition at line 148 of file xmega_tc.h.
| #define TC_INTCTRLB_CCBINTLVL_SIZE 2 |
Compare or Capture B Interrupt Level.
Definition at line 154 of file xmega_tc.h.
| #define TC_INTCTRLB_CCBINTLVL_START 2 |
Compare or Capture B Interrupt Level.
Definition at line 152 of file xmega_tc.h.
| #define TC_INTCTRLB_CCCINTLVL_SIZE 2 |
Compare or Capture C Interrupt Level.
Definition at line 158 of file xmega_tc.h.
| #define TC_INTCTRLB_CCCINTLVL_START 4 |
Compare or Capture C Interrupt Level.
Definition at line 156 of file xmega_tc.h.
| #define TC_INTCTRLB_CCDINTLVL_SIZE 2 |
Compare or Capture D Interrupt Level.
Definition at line 162 of file xmega_tc.h.
| #define TC_INTCTRLB_CCDINTLVL_START 6 |
Compare or Capture D Interrupt Level.
Definition at line 160 of file xmega_tc.h.
| #define TC_INTFLAGS 0x0c |
Interrupt Flag Register.
Definition at line 69 of file xmega_tc.h.
| #define TC_LUPD_BIT 1 |
Lock Update.
Definition at line 168 of file xmega_tc.h.
| #define TC_PERBUFH 0x37 |
Timer/Counter Period Buffer H.
Definition at line 84 of file xmega_tc.h.
| #define TC_PERBUFL 0x36 |
Timer/Counter Period Buffer L.
Definition at line 83 of file xmega_tc.h.
| #define TC_PERBV_BIT 0 |
Period Buffer Valid.
Definition at line 175 of file xmega_tc.h.
| #define TC_PERH 0x27 |
Period Register L.
Definition at line 74 of file xmega_tc.h.
| #define TC_PERL 0x26 |
Period Register H.
Definition at line 73 of file xmega_tc.h.
| #define tc_read_reg16 | ( | tc, | |||
| reg | ) | mmio_read16((void *) ((uintptr_t)(tc) + TC_##reg##L)) |
Read the value of 16-bit TC register reg.
Definition at line 288 of file xmega_tc.h.
Referenced by tc_timer_get_time(), and tc_timer_set_alarm().
| #define tc_read_reg8 | ( | tc, | |||
| reg | ) | mmio_read8((void *) ((uintptr_t)(tc) + TC_##reg)) |
Read the value of 8-bit TC register reg.
Definition at line 282 of file xmega_tc.h.
| #define TC_TEMP 0x0f |
Temporary Register for 16-bit Access.
Definition at line 70 of file xmega_tc.h.
| #define TC_WGMODE_DS_B 0x7 |
Dual Slope PWM, Event on BOTTOM.
Definition at line 219 of file xmega_tc.h.
| #define TC_WGMODE_DS_T 0x5 |
Dual Slope PWM, Event on TOP.
Definition at line 217 of file xmega_tc.h.
| #define TC_WGMODE_DS_TB 0x6 |
Dual Slope PWM, Event on TOP and BOTTOM.
Definition at line 218 of file xmega_tc.h.
| #define TC_WGMODE_FRQ 0x1 |
Frequency.
Definition at line 215 of file xmega_tc.h.
| #define TC_WGMODE_NORMAL 0x0 |
Normal.
Definition at line 214 of file xmega_tc.h.
| #define TC_WGMODE_SS 0x3 |
Single Slope PWM.
Definition at line 216 of file xmega_tc.h.
| #define tc_write_reg16 | ( | tc, | |||
| reg, | |||||
| value | ) | mmio_write16((void *) ((uintptr_t)(tc) + TC_##reg##L), value) |
Write value to 16-bit TC register reg.
Definition at line 285 of file xmega_tc.h.
Referenced by tc_timer_set_alarm().
| #define tc_write_reg8 | ( | tc, | |||
| reg, | |||||
| value | ) | mmio_write8((void *) ((uintptr_t)(tc) + TC_##reg), value) |
Write value to 8-bit TC register reg.
Definition at line 279 of file xmega_tc.h.
Referenced by tc_timer_init(), tc_timer_irq_handler(), tc_timer_set_alarm(), tc_timer_start(), tc_timer_stop(), and tc_timer_write_resolution().
