Xmega Clock Register Definitions
[Internal Register Definitions]
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Register Offsets | |
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| #define | XMEGA_CLK_CTRL 0x00 |
| System Clock Control. | |
| #define | XMEGA_CLK_PSCTRL 0x01 |
| System Clock Prescaler. | |
| #define | XMEGA_CLK_LOCK 0x02 |
| Clock System Lock. | |
| #define | XMEGA_CLK_RTCCTRL 0x03 |
| RTC Control. | |
Bitfields in CTRL | |
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| #define | XMEGA_CLK_SCLKSEL_START 0 |
| #define | XMEGA_CLK_SCLKSEL_SIZE 3 |
Bitfields in PSCTRL | |
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| #define | XMEGA_CLK_PSBCDIV_START 0 |
| Prescaler B/C Division Factor. | |
| #define | XMEGA_CLK_PSBCDIV_SIZE 2 |
| Prescaler B/C Division Factor. | |
| #define | XMEGA_CLK_PSADIV_START 0 |
| Prescaler A Division Factor. | |
| #define | XMEGA_CLK_PSADIV_SIZE 0 |
| Prescaler A Division Factor. | |
Bitfields in LOCK | |
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| #define | XMEGA_CLK_LOCK_BIT 0 |
| Clock System Lock. | |
| #define | XMEGA_CLK_RTCEN_BIT 0 |
| RTC Clock Source Enable. | |
| #define | XMEGA_CLK_RTCSRC_START 1 |
| RTC Clock Source. | |
| #define | XMEGA_CLK_RTCSRC_SIZE 3 |
| RTC Clock Source. | |
Prescaler A Division Factor | |
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| |
| #define | XMEGA_CLK_PSADIV_1 0 |
| No division. | |
| #define | XMEGA_CLK_PSADIV_2 1 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_4 3 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_8 5 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_16 7 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_32 9 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_64 11 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_128 13 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_256 15 |
| Divide by 2. | |
| #define | XMEGA_CLK_PSADIV_512 17 |
| Divide by 2. | |
Prescaler B/C Division Factor | |
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| |
| #define | XMEGA_CLK_PSBCDIV_1_1 0 |
| No division / No division. | |
| #define | XMEGA_CLK_PSBCDIV_1_2 1 |
| No division / Divide by 2. | |
| #define | XMEGA_CLK_PSBCDIV_4_1 2 |
| Divide by 4 / No division. | |
| #define | XMEGA_CLK_PSBCDIV_2_2 3 |
| Divide by 2 / Divide by 2. | |
Bit manipulation macros | |
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| #define | CLK_BIT(name) (1U << XMEGA_CLK_##name##_BIT) |
| Create a mask with bit name set. | |
| #define | CLK_BF(name, value) ((value) << XMEGA_CLK_##name##_START) |
| Create a mask with bitfield name set to value. | |
| #define | CLK_BFMASK(name) |
| Create a mask of the bitfield name. | |
| #define | CLK_BFEXT(name, regval) |
| Extract the value of bitfield name from regval. | |
| #define | CLK_BFINS(name, value, regval) |
| Return regval with bitfield name set to value. | |
Register access macros | |
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| #define | clk_read_reg(reg) _clk_read_reg(reg) |
| Read the value of CLK register reg. | |
| #define | _clk_read_reg(reg) mmio_read8((void *)(CLK_BASE + XMEGA_CLK_##reg)) |
| #define | clk_write_reg(reg, value) _clk_write_reg(reg, value) |
| Write value to CLK register reg. | |
| #define | _clk_write_reg(reg, value) mmio_write8((void *)(CLK_BASE + XMEGA_CLK_##reg), (value)) |
| #define | clk_write_ccp_reg(reg, value) _clk_write_ccp_reg(reg, value) |
| Write value to CCP-protected CLK register reg. | |
| #define | _clk_write_ccp_reg(reg, value) mmio_ccp_write8((void *)(CLK_BASE + XMEGA_CLK_##reg), (value)) |
Detailed Description
These are the Xmega Clock registers taken from the Xmega A manual.
Define Documentation
| #define CLK_BF | ( | name, | |||
| value | ) | ((value) << XMEGA_CLK_##name##_START) |
Create a mask with bitfield name set to value.
Definition at line 114 of file xmega_clk.h.
Referenced by sysclk_init().
| #define CLK_BFEXT | ( | name, | |||
| regval | ) |
(((regval) >> XMEGA_CLK_##name##_START) \
& ((1U << XMEGA_CLK_##name##_SIZE) - 1))
Extract the value of bitfield name from regval.
Definition at line 121 of file xmega_clk.h.
| #define CLK_BFINS | ( | name, | |||
| value, | |||||
| regval | ) |
(((regval) & ~(((1U << XMEGA_CLK_##name##_SIZE) - 1) \
<< XMEGA_CLK_##name##_START)) \
| XMEGA_CLK_BF(name, value))
Return regval with bitfield name set to value.
Definition at line 125 of file xmega_clk.h.
| #define CLK_BFMASK | ( | name | ) |
(((1U << XMEGA_CLK_##name##_SIZE) - 1) \
<< XMEGA_CLK_##name##_START)
Create a mask of the bitfield name.
Definition at line 117 of file xmega_clk.h.
| #define CLK_BIT | ( | name | ) | (1U << XMEGA_CLK_##name##_BIT) |
Create a mask with bit name set.
Definition at line 112 of file xmega_clk.h.
| #define clk_read_reg | ( | reg | ) | _clk_read_reg(reg) |
Read the value of CLK register reg.
Definition at line 134 of file xmega_clk.h.
Referenced by sysclk_init().
| #define clk_write_ccp_reg | ( | reg, | |||
| value | ) | _clk_write_ccp_reg(reg, value) |
Write value to CCP-protected CLK register reg.
Definition at line 144 of file xmega_clk.h.
Referenced by sysclk_init().
| #define clk_write_reg | ( | reg, | |||
| value | ) | _clk_write_reg(reg, value) |
Write value to CLK register reg.
Definition at line 139 of file xmega_clk.h.
| #define XMEGA_CLK_CTRL 0x00 |
System Clock Control.
Definition at line 55 of file xmega_clk.h.
| #define XMEGA_CLK_LOCK 0x02 |
Clock System Lock.
Definition at line 57 of file xmega_clk.h.
| #define XMEGA_CLK_LOCK_BIT 0 |
Clock System Lock.
Definition at line 77 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_1 0 |
| #define XMEGA_CLK_PSADIV_128 13 |
Divide by 2.
Definition at line 96 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_16 7 |
Divide by 2.
Definition at line 93 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_2 1 |
Divide by 2.
Definition at line 90 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_256 15 |
Divide by 2.
Definition at line 97 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_32 9 |
Divide by 2.
Definition at line 94 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_4 3 |
Divide by 2.
Definition at line 91 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_512 17 |
| #define XMEGA_CLK_PSADIV_64 11 |
Divide by 2.
Definition at line 95 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_8 5 |
Divide by 2.
Definition at line 92 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_SIZE 0 |
Prescaler A Division Factor.
Definition at line 72 of file xmega_clk.h.
| #define XMEGA_CLK_PSADIV_START 0 |
Prescaler A Division Factor.
Definition at line 71 of file xmega_clk.h.
| #define XMEGA_CLK_PSBCDIV_1_1 0 |
No division / No division.
Definition at line 103 of file xmega_clk.h.
Referenced by sysclk_get_per2_hz(), and sysclk_init().
| #define XMEGA_CLK_PSBCDIV_1_2 1 |
No division / Divide by 2.
Definition at line 104 of file xmega_clk.h.
Referenced by sysclk_get_per2_hz().
| #define XMEGA_CLK_PSBCDIV_2_2 3 |
Divide by 2 / Divide by 2.
Definition at line 106 of file xmega_clk.h.
Referenced by sysclk_get_per2_hz(), and sysclk_init().
| #define XMEGA_CLK_PSBCDIV_4_1 2 |
Divide by 4 / No division.
Definition at line 105 of file xmega_clk.h.
Referenced by sysclk_get_per2_hz().
| #define XMEGA_CLK_PSBCDIV_SIZE 2 |
Prescaler B/C Division Factor.
Definition at line 70 of file xmega_clk.h.
| #define XMEGA_CLK_PSBCDIV_START 0 |
Prescaler B/C Division Factor.
Definition at line 69 of file xmega_clk.h.
| #define XMEGA_CLK_PSCTRL 0x01 |
System Clock Prescaler.
Definition at line 56 of file xmega_clk.h.
| #define XMEGA_CLK_RTCCTRL 0x03 |
RTC Control.
Definition at line 58 of file xmega_clk.h.
| #define XMEGA_CLK_RTCEN_BIT 0 |
RTC Clock Source Enable.
Definition at line 82 of file xmega_clk.h.
| #define XMEGA_CLK_RTCSRC_SIZE 3 |
RTC Clock Source.
Definition at line 84 of file xmega_clk.h.
| #define XMEGA_CLK_RTCSRC_START 1 |
RTC Clock Source.
Definition at line 83 of file xmega_clk.h.
