AVR172 : Atmel BLDC control on ATAVRMC310 with ATmega32M1: iopwm324.h Source File

00001 /****** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** */
00002 /****** Created: 2007-10-03 17:26 ******* Source: AT90PWM324.XML ********** */
00003 /**************************************************************************
00004  *
00005  * - File Name          : "iopwm324.h"
00006  * - Title              : Register/Bit Definitions for the AT90PWM324
00007  * - Date               : 2007-10-03
00008  * - Version            : 2.21
00009  * - Support E-Mail     : avr@atmel.com
00010  * - Target MCU         : AT90PWM324
00011  *
00012  * - Compiler           : IAR Embedded Workbench - iccAVR and aAVR.
00013  *
00014  **************************************************************************
00015  */
00016 
00017 
00018 #include "iomacro.h"
00019 
00020 #if TID_GUARD(3)
00021 #error This file should only be compiled with iccavr or aavr whith processor option -v3
00022 #endif /* TID_GUARD(3) */
00023 
00024 /* Include the SFR part if this file has not been included before,
00025 * OR this file is included by the assembler (SFRs must be defined in
00026 * each assembler module). */
00027 #if !defined(__IOPWM324_H) || defined(__IAR_SYSTEMS_ASM__)
00028 
00029 #pragma language=extended
00030 
00031 /*==========================*/
00032 /* Predefined SFR Addresses */
00033 /*==========================*/
00034 
00035 
00036 /* ***** SPECIFY DEVICE *************************************************** */
00037 //#define  PART_NAME       AT90PWM324
00038 #define    SIGNATURE_000   0x1e
00039 #define    SIGNATURE_001   0x95
00040 #define    SIGNATURE_002   0x84
00041 
00042 
00043 
00044 /* ***** I/O REGISTER DEFINITIONS ***************************************** */
00045 /* NOTE:
00046  * Definitions marked "MEMORY MAPPED"are extended I/O ports
00047  * and cannot be used with IN/OUT instructions
00048  */
00049 SFR_B(CANMSG,   0xfa)
00050 SFR_B(CANSTMH,  0xf9)
00051 SFR_B(CANSTML,  0xf8)
00052 SFR_B(CANIDM1,  0xf7)
00053 SFR_B(CANIDM2,  0xf6)
00054 SFR_B(CANIDM3,  0xf5)
00055 SFR_B(CANIDM4,  0xf4)
00056 SFR_B(CANIDT1,  0xf3)
00057 SFR_B(CANIDT2,  0xf2)
00058 SFR_B(CANIDT3,  0xf1)
00059 SFR_B(CANIDT4,  0xf0)
00060 SFR_B(CANCDMOB, 0xef)
00061 SFR_B(CANSTMOB, 0xee)
00062 SFR_B(CANPAGE,  0xed)
00063 SFR_B(CANHPMOB, 0xec)
00064 SFR_B(CANREC,   0xeb)
00065 SFR_B(CANTEC,   0xea)
00066 SFR_B(CANTTCH,  0xe9)
00067 SFR_B(CANTTCL,  0xe8)
00068 SFR_B(CANTIMH,  0xe7)
00069 SFR_B(CANTIML,  0xe6)
00070 SFR_B(CANTCON,  0xe5)
00071 SFR_B(CANBT3,   0xe4)
00072 SFR_B(CANBT2,   0xe3)
00073 SFR_B(CANBT1,   0xe2)
00074 SFR_B(CANSIT1,  0xe1)
00075 SFR_B(CANSIT2,  0xe0)
00076 SFR_B(CANIE1,   0xdf)
00077 SFR_B(CANIE2,   0xde)
00078 SFR_B(CANEN1,   0xdd)
00079 SFR_B(CANEN2,   0xdc)
00080 SFR_B(CANGIE,   0xdb)
00081 SFR_B(CANGIT,   0xda)
00082 SFR_B(CANGSTA,  0xd9)
00083 SFR_B(CANGCON,  0xd8)
00084 SFR_B(LINDAT,   0xd2)
00085 SFR_B(LINSEL,   0xd1)
00086 SFR_B(LINIDR,   0xd0)
00087 SFR_B(LINDLR,   0xcf)
00088 SFR_B(LINBRRH,  0xce)
00089 SFR_B(LINBRRL,  0xcd)
00090 SFR_B(LINBTR,   0xcc)
00091 SFR_B(LINERR,   0xcb)
00092 SFR_B(LINENIR,  0xca)
00093 SFR_B(LINSIR,   0xc9)
00094 SFR_B(LINCR,    0xc8)
00095 SFR_B(PIFR, 0xbc)
00096 SFR_B(PIM,  0xbb)
00097 SFR_B(PMIC2,    0xba)
00098 SFR_B(PMIC1,    0xb9)
00099 SFR_B(PMIC0,    0xb8)
00100 SFR_B(PCTL, 0xb7)
00101 SFR_B(POC,  0xb6)
00102 SFR_B(PCNF, 0xb5)
00103 SFR_B(PSYNC,    0xb4)
00104 SFR_B(POCRxRBH, 0xb3)
00105 SFR_B(POCRxRBL, 0xb2)
00106 SFR_B(POCR2SBH, 0xb1)
00107 SFR_B(POCR2SBL, 0xb0)
00108 SFR_B(POCR2RAH, 0xaf)
00109 SFR_B(POCR2RAL, 0xae)
00110 SFR_B(POCR2SAH, 0xad)
00111 SFR_B(POCR2SAL, 0xac)
00112 SFR_B(POCR1SBH, 0xab)
00113 SFR_B(POCR1SBL, 0xaa)
00114 SFR_B(POCR1RAH, 0xa9)
00115 SFR_B(POCR1RAL, 0xa8)
00116 SFR_B(POCR1SAH, 0xa7)
00117 SFR_B(POCR1SAL, 0xa6)
00118 SFR_B(POCR0SBH, 0xa5)
00119 SFR_B(POCR0SBL, 0xa4)
00120 SFR_B(POCR0RAH, 0xa3)
00121 SFR_B(POCR0RAL, 0xa2)
00122 SFR_B(POCR0SAH, 0xa1)
00123 SFR_B(POCR0SAL, 0xa0)
00124 SFR_B(AC3CON,   0x97)
00125 SFR_B(AC2CON,   0x96)
00126 SFR_B(AC1CON,   0x95)
00127 SFR_B(AC0CON,   0x94)
00128 SFR_B(DACH, 0x92)
00129 SFR_B(DACL, 0x91)
00130 SFR_B(DACON,    0x90)
00131 SFR_W(OCR1B,    0x8a)
00132 SFR_W(OCR1A,    0x88)
00133 SFR_W(ICR1, 0x86)
00134 SFR_W(TCNT1,    0x84)
00135 SFR_B(TCCR1C,   0x82)
00136 SFR_B(TCCR1B,   0x81)
00137 SFR_B(TCCR1A,   0x80)
00138 SFR_B(DIDR1,    0x7f)
00139 SFR_B(DIDR0,    0x7e)
00140 SFR_B(ADMUX,    0x7c)
00141 SFR_B(ADCSRB,   0x7b)
00142 SFR_B(ADCSRA,   0x7a)
00143 SFR_B(ADCH, 0x79)
00144 SFR_B(ADCL, 0x78)
00145 SFR_B(AMP2CSR,  0x77)
00146 SFR_B(AMP1CSR,  0x76)
00147 SFR_B(AMP0CSR,  0x75)
00148 SFR_B(TIMSK1,   0x6f)
00149 SFR_B(TIMSK0,   0x6e)
00150 SFR_B(PCMSK3,   0x6d)
00151 SFR_B(PCMSK2,   0x6c)
00152 SFR_B(PCMSK1,   0x6b)
00153 SFR_B(PCMSK0,   0x6a)
00154 SFR_B(EICRA,    0x69)
00155 SFR_B(OSCCAL,   0x66)
00156 SFR_B(PRR,  0x64)
00157 SFR_B(CLKPR,    0x61)
00158 SFR_B(WDTCSR,   0x60)
00159 SFR_B(SREG, 0x3f)
00160 SFR_W(SP,   0x3d)
00161 SFR_B(SPMCSR,   0x37)
00162 SFR_B(MCUCR,    0x35)
00163 SFR_B(MCUSR,    0x34)
00164 SFR_B(SMCR, 0x33)
00165 SFR_B(DWDR, 0x31)
00166 SFR_B(ACSR, 0x30)
00167 SFR_B(SPDR, 0x2e)
00168 SFR_B(SPSR, 0x2d)
00169 SFR_B(SPCR, 0x2c)
00170 SFR_B(PLLCSR,   0x29)
00171 SFR_B(OCR0B,    0x28)
00172 SFR_B(OCR0A,    0x27)
00173 SFR_B(TCNT0,    0x26)
00174 SFR_B(TCCR0B,   0x25)
00175 SFR_B(TCCR0A,   0x24)
00176 SFR_B(GTCCR,    0x23)
00177 SFR_W(EEAR, 0x21)
00178 SFR_B(EEDR, 0x20)
00179 SFR_B(EECR, 0x1f)
00180 SFR_B(GPIOR0,   0x1e)
00181 SFR_B(EIMSK,    0x1d)
00182 SFR_B(EIFR, 0x1c)
00183 SFR_B(PCIFR,    0x1b)
00184 SFR_B(GPIOR2,   0x1a)
00185 SFR_B(GPIOR1,   0x19)
00186 SFR_B(TIFR1,    0x16)
00187 SFR_B(TIFR0,    0x15)
00188 SFR_B(PORTE,    0x0e)
00189 SFR_B(DDRE, 0x0d)
00190 SFR_B(PINE, 0x0c)
00191 SFR_B(PORTD,    0x0b)
00192 SFR_B(DDRD, 0x0a)
00193 SFR_B(PIND, 0x09)
00194 SFR_B(PORTC,    0x08)
00195 SFR_B(DDRC, 0x07)
00196 SFR_B(PINC, 0x06)
00197 SFR_B(PORTB,    0x05)
00198 SFR_B(DDRB, 0x04)
00199 SFR_B(PINB, 0x03)
00200 
00201 
00202 
00203 #ifndef __IOPWM324_H
00204 #define __IOPWM324_H
00205 
00206 #ifdef __IAR_SYSTEMS_ASM__ 
00207 #ifndef ENABLE_BIT_DEFINITIONS
00208 #define  ENABLE_BIT_DEFINITIONS
00209 #endif /* ENABLE_BIT_DEFINITIONS */
00210 #endif /* __IAR_SYSTEMS_ASM__ */
00211 
00212 #ifdef ENABLE_BIT_DEFINITIONS
00213 /* ***** BIT DEFINITIONS ************************************************** */
00214 
00215 /* ***** PORTB ************************ */
00216 /* PORTB - Port B Data Register */
00217 #define    PORTB0          0       // Port B Data Register bit 0
00218 #define    PORTB1          1       // Port B Data Register bit 1
00219 #define    PORTB2          2       // Port B Data Register bit 2
00220 #define    PORTB3          3       // Port B Data Register bit 3
00221 #define    PORTB4          4       // Port B Data Register bit 4
00222 #define    PORTB5          5       // Port B Data Register bit 5
00223 #define    PORTB6          6       // Port B Data Register bit 6
00224 #define    PORTB7          7       // Port B Data Register bit 7
00225 
00226 /* DDRB - Port B Data Direction Register */
00227 #define    DDB0            0       // Port B Data Direction Register bit 0
00228 #define    DDB1            1       // Port B Data Direction Register bit 1
00229 #define    DDB2            2       // Port B Data Direction Register bit 2
00230 #define    DDB3            3       // Port B Data Direction Register bit 3
00231 #define    DDB4            4       // Port B Data Direction Register bit 4
00232 #define    DDB5            5       // Port B Data Direction Register bit 5
00233 #define    DDB6            6       // Port B Data Direction Register bit 6
00234 #define    DDB7            7       // Port B Data Direction Register bit 7
00235 
00236 /* PINB - Port B Input Pins */
00237 #define    PINB0           0       // Port B Input Pins bit 0
00238 #define    PINB1           1       // Port B Input Pins bit 1
00239 #define    PINB2           2       // Port B Input Pins bit 2
00240 #define    PINB3           3       // Port B Input Pins bit 3
00241 #define    PINB4           4       // Port B Input Pins bit 4
00242 #define    PINB5           5       // Port B Input Pins bit 5
00243 #define    PINB6           6       // Port B Input Pins bit 6
00244 #define    PINB7           7       // Port B Input Pins bit 7
00245 
00246 
00247 /* ***** PORTC ************************ */
00248 /* PORTC - Port C Data Register */
00249 #define    PORTC0          0       // Port C Data Register bit 0
00250 #define    PORTC1          1       // Port C Data Register bit 1
00251 #define    PORTC2          2       // Port C Data Register bit 2
00252 #define    PORTC3          3       // Port C Data Register bit 3
00253 #define    PORTC4          4       // Port C Data Register bit 4
00254 #define    PORTC5          5       // Port C Data Register bit 5
00255 #define    PORTC6          6       // Port C Data Register bit 6
00256 #define    PORTC7          7       // Port C Data Register bit 7
00257 
00258 /* DDRC - Port C Data Direction Register */
00259 #define    DDC0            0       // Port C Data Direction Register bit 0
00260 #define    DDC1            1       // Port C Data Direction Register bit 1
00261 #define    DDC2            2       // Port C Data Direction Register bit 2
00262 #define    DDC3            3       // Port C Data Direction Register bit 3
00263 #define    DDC4            4       // Port C Data Direction Register bit 4
00264 #define    DDC5            5       // Port C Data Direction Register bit 5
00265 #define    DDC6            6       // Port C Data Direction Register bit 6
00266 #define    DDC7            7       // Port C Data Direction Register bit 7
00267 
00268 /* PINC - Port C Input Pins */
00269 #define    PINC0           0       // Port C Input Pins bit 0
00270 #define    PINC1           1       // Port C Input Pins bit 1
00271 #define    PINC2           2       // Port C Input Pins bit 2
00272 #define    PINC3           3       // Port C Input Pins bit 3
00273 #define    PINC4           4       // Port C Input Pins bit 4
00274 #define    PINC5           5       // Port C Input Pins bit 5
00275 #define    PINC6           6       // Port C Input Pins bit 6
00276 #define    PINC7           7       // Port C Input Pins bit 7
00277 
00278 
00279 /* ***** PORTD ************************ */
00280 /* PORTD - Port D Data Register */
00281 #define    PORTD0          0       // Port D Data Register bit 0
00282 #define    PORTD1          1       // Port D Data Register bit 1
00283 #define    PORTD2          2       // Port D Data Register bit 2
00284 #define    PORTD3          3       // Port D Data Register bit 3
00285 #define    PORTD4          4       // Port D Data Register bit 4
00286 #define    PORTD5          5       // Port D Data Register bit 5
00287 #define    PORTD6          6       // Port D Data Register bit 6
00288 #define    PORTD7          7       // Port D Data Register bit 7
00289 
00290 /* DDRD - Port D Data Direction Register */
00291 #define    DDD0            0       // Port D Data Direction Register bit 0
00292 #define    DDD1            1       // Port D Data Direction Register bit 1
00293 #define    DDD2            2       // Port D Data Direction Register bit 2
00294 #define    DDD3            3       // Port D Data Direction Register bit 3
00295 #define    DDD4            4       // Port D Data Direction Register bit 4
00296 #define    DDD5            5       // Port D Data Direction Register bit 5
00297 #define    DDD6            6       // Port D Data Direction Register bit 6
00298 #define    DDD7            7       // Port D Data Direction Register bit 7
00299 
00300 /* PIND - Port D Input Pins */
00301 #define    PIND0           0       // Port D Input Pins bit 0
00302 #define    PIND1           1       // Port D Input Pins bit 1
00303 #define    PIND2           2       // Port D Input Pins bit 2
00304 #define    PIND3           3       // Port D Input Pins bit 3
00305 #define    PIND4           4       // Port D Input Pins bit 4
00306 #define    PIND5           5       // Port D Input Pins bit 5
00307 #define    PIND6           6       // Port D Input Pins bit 6
00308 #define    PIND7           7       // Port D Input Pins bit 7
00309 
00310 
00311 /* ***** BOOT_LOAD ******************** */
00312 /* SPMCSR - Store Program Memory Control Register */
00313 #define    SPMCR           SPMCSR  // For compatibility
00314 #define    SPMEN           0       // Store Program Memory Enable
00315 #define    PGERS           1       // Page Erase
00316 #define    PGWRT           2       // Page Write
00317 #define    BLBSET          3       // Boot Lock Bit Set
00318 #define    RWWSRE          4       // Read While Write section read enable
00319 #define    ASRE            RWWSRE  // For compatibility
00320 #define    RWWSB           6       // Read While Write Section Busy
00321 #define    ASB             RWWSB   // For compatibility
00322 #define    SPMIE           7       // SPM Interrupt Enable
00323 
00324 
00325 /* ***** CAN ************************** */
00326 /* CANGCON - CAN General Control Register */
00327 #define    SWRES           0       // Software Reset Request
00328 #define    ENASTB          1       // Enable / Standby
00329 #define    TEST            2       // Test Mode
00330 #define    LISTEN          3       // Listening Mode
00331 #define    SYNTTC          4       // Synchronization of TTC
00332 #define    TTC             5       // Time Trigger Communication
00333 #define    OVRQ            6       // Overload Frame Request
00334 #define    ABRQ            7       // Abort Request
00335 
00336 /* CANGSTA - CAN General Status Register */
00337 #define    ERRP            0       // Error Passive Mode
00338 #define    BOFF            1       // Bus Off Mode
00339 #define    ENFG            2       // Enable Flag
00340 #define    RXBSY           3       // Receiver Busy
00341 #define    TXBSY           4       // Transmitter Busy
00342 #define    OVFG            6       // Overload Frame Flag
00343 
00344 /* CANGIT - CAN General Interrupt Register Flags */
00345 #define    AERG            0       // Ackknowledgement Error General Flag
00346 #define    FERG            1       // Form Error General Flag
00347 #define    CERG            2       // CRC Error General Flag
00348 #define    SERG            3       // Stuff Error General Flag
00349 #define    BXOK            4       // Burst Receive Interrupt Flag
00350 #define    OVRTIM          5       // Overrun CAN Timer Flag
00351 #define    BOFFIT          6       // Bus Off Interrupt Flag
00352 #define    CANIT           7       // General Interrupt Flag
00353 
00354 /* CANGIE - CAN General Interrupt Enable Register */
00355 #define    ENOVRT          0       // Enable CAN Timer Overrun Interrupt
00356 #define    ENERG           1       // Enable General Error Interrupt
00357 #define    ENBX            2       // Enable Burst Receive Interrupt
00358 #define    ENERR           3       // Enable MOb Error Interrupt
00359 #define    ENTX            4       // Enable Transmitt Interrupt
00360 #define    ENRX            5       // Enable Receive Interrupt
00361 #define    ENBOFF          6       // Enable Bus Off Interrupt
00362 #define    ENIT            7       // Enable all Interrupts
00363 
00364 /* CANEN2 - Enable MOb Register 2 */
00365 #define    ENMOB0          0       // Enable MOb 0
00366 #define    ENMOB1          1       // Enable MOb 1
00367 #define    ENMOB2          2       // Enable MOb 2
00368 #define    ENMOB3          3       // Enable MOb 3
00369 #define    ENMOB4          4       // Enable MOb 4
00370 #define    ENMOB5          5       // Enable MOb 5
00371 
00372 /* CANEN1 - Enable MOb Register 1(empty) */
00373 
00374 /* CANIE2 - Enable Interrupt MOb Register 2 */
00375 #define    IEMOB0          0       // Interrupt Enable  MOb 0
00376 #define    IEMOB1          1       // Interrupt Enable  MOb 1
00377 #define    IEMOB2          2       // Interrupt Enable  MOb 2
00378 #define    IEMOB3          3       // Interrupt Enable  MOb 3
00379 #define    IEMOB4          4       // Interrupt Enable  MOb 4
00380 #define    IEMOB5          5       // Interrupt Enable  MOb 5
00381 
00382 /* CANIE1 - Enable Interrupt MOb Register 1 (empty) */
00383 
00384 /* CANSIT2 - CAN Status Interrupt MOb Register 2 */
00385 #define    SIT0            0       // Status of Interrupt MOb 0
00386 #define    SIT1            1       // Status of Interrupt MOb 1
00387 #define    SIT2            2       // Status of Interrupt MOb 2
00388 #define    SIT3            3       // Status of Interrupt MOb 3
00389 #define    SIT4            4       // Status of Interrupt MOb 4
00390 #define    SIT5            5       // Status of Interrupt MOb 5
00391 
00392 /* CANSIT1 - CAN Status Interrupt MOb Register 1 (empty) */
00393 
00394 /* CANBT1 - CAN Bit Timing Register 1 */
00395 #define    BRP0            1       // Baud Rate Prescaler bit 0
00396 #define    BRP1            2       // Baud Rate Prescaler bit 1
00397 #define    BRP2            3       // Baud Rate Prescaler bit 2
00398 #define    BRP3            4       // Baud Rate Prescaler bit 3
00399 #define    BRP4            5       // Baud Rate Prescaler bit 4
00400 #define    BRP5            6       // Baud Rate Prescaler bit 5
00401 
00402 /* CANBT2 - CAN Bit Timing Register 2 */
00403 #define    PRS0            1       // Propagation Time Segment bit 0
00404 #define    PRS1            2       // Propagation Time Segment bit 1
00405 #define    PRS2            3       // Propagation Time Segment bit 2
00406 #define    SJW0            5       // Re-Sync Jump Width bit 0
00407 #define    SJW1            6       // Re-Sync Jump Width bit 1
00408 
00409 /* CANBT3 - CAN Bit Timing Register 3 */
00410 #define    SMP             0       // Sample Type
00411 #define    PHS10           1       // Phase Segment 1 bit 0
00412 #define    PHS11           2       // Phase Segment 1 bit 1
00413 #define    PHS12           3       // Phase Segment 1 bit 2
00414 #define    PHS20           4       // Phase Segment 2 bit 0
00415 #define    PHS21           5       // Phase Segment 2 bit 1
00416 #define    PHS22           6       // Phase Segment 2 bit 2
00417 
00418 /* CANTCON - Timer Control Register */
00419 
00420 /* CANTIML - Timer Register Low */
00421 
00422 /* CANTIMH - Timer Register High */
00423 
00424 /* CANTTCL - TTC Timer Register Low */
00425 
00426 /* CANTTCH - TTC Timer Register High */
00427 
00428 /* CANTEC - Transmit Error Counter Register */
00429 
00430 /* CANREC - Receive Error Counter Register */
00431 
00432 /* CANHPMOB - Highest Priority MOb Register */
00433 #define    CGP0            0       // CAN General Purpose bit 0
00434 #define    CGP1            1       // CAN General Purpose bit 1
00435 #define    CGP2            2       // CAN General Purpose bit 2
00436 #define    CGP3            3       // CAN General Purpose bit 3
00437 #define    HPMOB0          4       // Highest Priority MOb Number bit 0
00438 #define    HPMOB1          5       // Highest Priority MOb Number bit 1
00439 #define    HPMOB2          6       // Highest Priority MOb Number bit 2
00440 #define    HPMOB3          7       // Highest Priority MOb Number bit 3
00441 
00442 /* CANPAGE - Page MOb Register */
00443 #define    INDX0           0       // Data Buffer Index bit 0
00444 #define    INDX1           1       // Data Buffer Index bit 1
00445 #define    INDX2           2       // Data Buffer Index bit 2
00446 #define    AINC            3       // MOb Data Buffer Auto Increment (Active Low)
00447 #define    MOBNB0          4       // MOb Number bit 0
00448 #define    MOBNB1          5       // MOb Number bit 1
00449 #define    MOBNB2          6       // MOb Number bit 2
00450 #define    MOBNB3          7       // MOb Number bit 3
00451 
00452 /* CANSTMOB - MOb Status Register */
00453 #define    AERR            0       // Ackknowledgement Error on MOb
00454 #define    FERR            1       // Form Error on MOb
00455 #define    CERR            2       // CRC Error on MOb
00456 #define    SERR            3       // Stuff Error on MOb
00457 #define    BERR            4       // Bit Error on MOb
00458 #define    RXOK            5       // Receive OK on MOb
00459 #define    TXOK            6       // Transmit OK on MOb
00460 #define    DLCW            7       // Data Length Code Warning on MOb
00461 
00462 /* CANCDMOB - MOb Control and DLC Register */
00463 #define    DLC0            0       // Data Length Code bit 0
00464 #define    DLC1            1       // Data Length Code bit 1
00465 #define    DLC2            2       // Data Length Code bit 2
00466 #define    DLC3            3       // Data Length Code bit 3
00467 #define    IDE             4       // Identifier Extension
00468 #define    RPLV            5       // Reply Valid
00469 #define    CONMOB0         6       // MOb Config bit 0
00470 #define    CONMOB1         7       // MOb Config bit 1
00471 
00472 /* CANIDT4 - Identifier Tag Register 4 */
00473 #define    RB0TAG          0       // 
00474 #define    RB1TAG          1       // 
00475 #define    RTRTAG          2       // 
00476 #define    IDT0            3       // 
00477 #define    IDT1            4       // 
00478 #define    IDT2            5       // 
00479 #define    IDT3            6       // 
00480 #define    IDT4            7       // 
00481 
00482 /* CANIDT3 - Identifier Tag Register 3 */
00483 #define    IDT5            0       // 
00484 #define    IDT6            1       // 
00485 #define    IDT7            2       // 
00486 #define    IDT8            3       // 
00487 #define    IDT9            4       // 
00488 #define    IDT10           5       // 
00489 #define    IDT11           6       // 
00490 #define    IDT12           7       // 
00491 
00492 /* CANIDT2 - Identifier Tag Register 2 */
00493 #define    IDT13           0       // 
00494 #define    IDT14           1       // 
00495 #define    IDT15           2       // 
00496 #define    IDT16           3       // 
00497 #define    IDT17           4       // 
00498 #define    IDT18           5       // 
00499 #define    IDT19           6       // 
00500 #define    IDT20           7       // 
00501 
00502 /* CANIDT1 - Identifier Tag Register 1 */
00503 #define    IDT21           0       // 
00504 #define    IDT22           1       // 
00505 #define    IDT23           2       // 
00506 #define    IDT24           3       // 
00507 #define    IDT25           4       // 
00508 #define    IDT26           5       // 
00509 #define    IDT27           6       // 
00510 #define    IDT28           7       // 
00511 
00512 /* CANIDM4 - Identifier Mask Register 4 */
00513 #define    IDEMSK          0       // 
00514 #define    RTRMSK          2       // 
00515 #define    IDMSK0          3       // 
00516 #define    IDMSK1          4       // 
00517 #define    IDMSK2          5       // 
00518 #define    IDMSK3          6       // 
00519 #define    IDMSK4          7       // 
00520 
00521 /* CANIDM3 - Identifier Mask Register 3 */
00522 #define    IDMSK5          0       // 
00523 #define    IDMSK6          1       // 
00524 #define    IDMSK7          2       // 
00525 #define    IDMSK8          3       // 
00526 #define    IDMSK9          4       // 
00527 #define    IDMSK10         5       // 
00528 #define    IDMSK11         6       // 
00529 #define    IDMSK12         7       // 
00530 
00531 /* CANIDM2 - Identifier Mask Register 2 */
00532 #define    IDMSK13         0       // 
00533 #define    IDMSK14         1       // 
00534 #define    IDMSK15         2       // 
00535 #define    IDMSK16         3       // 
00536 #define    IDMSK17         4       // 
00537 #define    IDMSK18         5       // 
00538 #define    IDMSK19         6       // 
00539 #define    IDMSK20         7       // 
00540 
00541 /* CANIDM1 - Identifier Mask Register 1 */
00542 #define    IDMSK21         0       // 
00543 #define    IDMSK22         1       // 
00544 #define    IDMSK23         2       // 
00545 #define    IDMSK24         3       // 
00546 #define    IDMSK25         4       // 
00547 #define    IDMSK26         5       // 
00548 #define    IDMSK27         6       // 
00549 #define    IDMSK28         7       // 
00550 
00551 /* CANSTML - Time Stamp Register Low */
00552 
00553 /* CANSTMH - Time Stamp Register High */
00554 
00555 /* CANMSG - Message Data Register */
00556 
00557 
00558 /* ***** ANALOG_COMPARATOR ************ */
00559 /* AC0CON - Analog Comparator 0 Control Register */
00560 #define    AC0M0           0       // Analog Comparator 0 Multiplexer Register
00561 #define    AC0M1           1       // Analog Comparator 0 Multiplexer Regsiter
00562 #define    AC0M2           2       // Analog Comparator 0 Multiplexer Register
00563 #define    ACCKSEL         3
00564 #define    AC0IS0          4       // Analog Comparator 0 Interrupt Select Bit
00565 #define    AC0IS1          5       // Analog Comparator 0  Interrupt Select Bit
00566 #define    AC0IE           6       // Analog Comparator 0 Interrupt Enable Bit
00567 #define    AC0EN           7       // Analog Comparator 0 Enable Bit
00568 
00569 /* AC1CON - Analog Comparator 1 Control Register */
00570 #define    AC1M0           0       // Analog Comparator 1 Multiplexer Register
00571 #define    AC1M1           1       // Analog Comparator 1 Multiplexer Regsiter
00572 #define    AC1M2           2       // Analog Comparator 1 Multiplexer Register
00573 #define    AC1ICE          3       // Analog Comparator 1 Interrupt Capture Enable Bit
00574 #define    AC1IS0          4       // Analog Comparator 1 Interrupt Select Bit
00575 #define    AC1IS1          5       // Analog Comparator 1  Interrupt Select Bit
00576 #define    AC1IE           6       // Analog Comparator 1 Interrupt Enable Bit
00577 #define    AC1EN           7       // Analog Comparator 1 Enable Bit
00578 
00579 /* AC2CON - Analog Comparator 2 Control Register */
00580 #define    AC2M0           0       // Analog Comparator 2 Multiplexer Register
00581 #define    AC2M1           1       // Analog Comparator 2 Multiplexer Regsiter
00582 #define    AC2M2           2       // Analog Comparator 2 Multiplexer Register
00583 #define    AC2IS0          4       // Analog Comparator 2 Interrupt Select Bit
00584 #define    AC2IS1          5       // Analog Comparator 2  Interrupt Select Bit
00585 #define    AC2IE           6       // Analog Comparator 2 Interrupt Enable Bit
00586 #define    AC2EN           7       // Analog Comparator 2 Enable Bit
00587 
00588 /* ACSR - Analog Comparator Status Register */
00589 #define    AC0O            0       // Analog Comparator 0 Output Bit
00590 #define    AC1O            1       // Analog Comparator 1 Output Bit
00591 #define    AC2O            2       // Analog Comparator 2 Output Bit
00592 #define    AC0IF           4       // Analog Comparator 0 Interrupt Flag Bit
00593 #define    AC1IF           5       // Analog Comparator 1  Interrupt Flag Bit
00594 #define    AC2IF           6       // Analog Comparator 2 Interrupt Flag Bit
00595 #define    ACCKDIV         7       // Analog Comparator Clock Divider
00596 
00597 
00598 /* ***** DA_CONVERTER ***************** */
00599 /* DACH - DAC Data Register High Byte */
00600 #define    DACH0           0       // DAC Data Register High Byte Bit 0
00601 #define    DACH1           1       // DAC Data Register High Byte Bit 1
00602 #define    DACH2           2       // DAC Data Register High Byte Bit 2
00603 #define    DACH3           3       // DAC Data Register High Byte Bit 3
00604 #define    DACH4           4       // DAC Data Register High Byte Bit 4
00605 #define    DACH5           5       // DAC Data Register High Byte Bit 5
00606 #define    DACH6           6       // DAC Data Register High Byte Bit 6
00607 #define    DACH7           7       // DAC Data Register High Byte Bit 7
00608 
00609 /* DACL - DAC Data Register Low Byte */
00610 #define    DACL0           0       // DAC Data Register Low Byte Bit 0
00611 #define    DACL1           1       // DAC Data Register Low Byte Bit 1
00612 #define    DACL2           2       // DAC Data Register Low Byte Bit 2
00613 #define    DACL3           3       // DAC Data Register Low Byte Bit 3
00614 #define    DACL4           4       // DAC Data Register Low Byte Bit 4
00615 #define    DACL5           5       // DAC Data Register Low Byte Bit 5
00616 #define    DACL6           6       // DAC Data Register Low Byte Bit 6
00617 #define    DACL7           7       // DAC Data Register Low Byte Bit 7
00618 
00619 /* DACON - DAC Control Register */
00620 #define    DAEN            0       // DAC Enable Bit
00621 #define    DAOE            1       // DAC Output Enable Bit
00622 #define    DALA            2       // DAC Left Adjust
00623 #define    DATS0           4       // DAC Trigger Selection Bit 0
00624 #define    DATS1           5       // DAC Trigger Selection Bit 1
00625 #define    DATS2           6       // DAC Trigger Selection Bit 2
00626 #define    DAATE           7       // DAC Auto Trigger Enable Bit
00627 
00628 
00629 /* ***** CPU ************************** */
00630 /* SREG - Status Register */
00631 #define    SREG_C          0       // Carry Flag
00632 #define    SREG_Z          1       // Zero Flag
00633 #define    SREG_N          2       // Negative Flag
00634 #define    SREG_V          3       // Two's Complement Overflow Flag
00635 #define    SREG_S          4       // Sign Bit
00636 #define    SREG_H          5       // Half Carry Flag
00637 #define    SREG_T          6       // Bit Copy Storage
00638 #define    SREG_I          7       // Global Interrupt Enable
00639 
00640 /* MCUCR - MCU Control Register */
00641 #define    IVCE            0       // Interrupt Vector Change Enable
00642 #define    IVSEL           1       // Interrupt Vector Select
00643 #define    PUD             4       // Pull-up disable
00644 #define    SPIPS           7       // SPI Pin Select
00645 
00646 /* MCUSR - MCU Status Register */
00647 #define    PORF            0       // Power-on reset flag
00648 #define    EXTRF           1       // External Reset Flag
00649 #define    BORF            2       // Brown-out Reset Flag
00650 #define    WDRF            3       // Watchdog Reset Flag
00651 
00652 /* OSCCAL - Oscillator Calibration Value */
00653 #define    CAL0            0       // Oscillator Calibration Value Bit0
00654 #define    CAL1            1       // Oscillator Calibration Value Bit1
00655 #define    CAL2            2       // Oscillator Calibration Value Bit2
00656 #define    CAL3            3       // Oscillator Calibration Value Bit3
00657 #define    CAL4            4       // Oscillator Calibration Value Bit4
00658 #define    CAL5            5       // Oscillator Calibration Value Bit5
00659 #define    CAL6            6       // Oscillator Calibration Value Bit6
00660 
00661 /* CLKPR -  */
00662 #define    CLKPS0          0       // 
00663 #define    CLKPS1          1       // 
00664 #define    CLKPS2          2       // 
00665 #define    CLKPS3          3       // 
00666 #define    CLKPCE          7       // 
00667 
00668 /* SMCR - Sleep Mode Control Register */
00669 #define    SE              0       // Sleep Enable
00670 #define    SM0             1       // Sleep Mode Select bit 0
00671 #define    SM1             2       // Sleep Mode Select bit 1
00672 #define    SM2             3       // Sleep Mode Select bit 2
00673 
00674 /* GPIOR2 - General Purpose IO Register 2 */
00675 #define    GPIOR20         0       // General Purpose IO Register 2 bit 0
00676 #define    GPIOR21         1       // General Purpose IO Register 2 bit 1
00677 #define    GPIOR22         2       // General Purpose IO Register 2 bit 2
00678 #define    GPIOR23         3       // General Purpose IO Register 2 bit 3
00679 #define    GPIOR24         4       // General Purpose IO Register 2 bit 4
00680 #define    GPIOR25         5       // General Purpose IO Register 2 bit 5
00681 #define    GPIOR26         6       // General Purpose IO Register 2 bit 6
00682 #define    GPIOR27         7       // General Purpose IO Register 2 bit 7
00683 
00684 /* GPIOR1 - General Purpose IO Register 1 */
00685 #define    GPIOR10         0       // General Purpose IO Register 1 bit 0
00686 #define    GPIOR11         1       // General Purpose IO Register 1 bit 1
00687 #define    GPIOR12         2       // General Purpose IO Register 1 bit 2
00688 #define    GPIOR13         3       // General Purpose IO Register 1 bit 3
00689 #define    GPIOR14         4       // General Purpose IO Register 1 bit 4
00690 #define    GPIOR15         5       // General Purpose IO Register 1 bit 5
00691 #define    GPIOR16         6       // General Purpose IO Register 1 bit 6
00692 #define    GPIOR17         7       // General Purpose IO Register 1 bit 7
00693 
00694 /* GPIOR0 - General Purpose IO Register 0 */
00695 #define    GPIOR00         0       // General Purpose IO Register 0 bit 0
00696 #define    GPIOR01         1       // General Purpose IO Register 0 bit 1
00697 #define    GPIOR02         2       // General Purpose IO Register 0 bit 2
00698 #define    GPIOR03         3       // General Purpose IO Register 0 bit 3
00699 #define    GPIOR04         4       // General Purpose IO Register 0 bit 4
00700 #define    GPIOR05         5       // General Purpose IO Register 0 bit 5
00701 #define    GPIOR06         6       // General Purpose IO Register 0 bit 6
00702 #define    GPIOR07         7       // General Purpose IO Register 0 bit 7
00703 
00704 /* PLLCSR - PLL Control And Status Register */
00705 #define    PLOCK           0       // PLL Lock Detector
00706 #define    PLLE            1       // PLL Enable
00707 #define    PLLF            2       // PLL Factor
00708 
00709 /* PRR - Power Reduction Register */
00710 #define    PRADC           0       // Power Reduction ADC
00711 #define    PRUSART0        1       // Power Reduction USART
00712 #define    PRSPI           2       // Power Reduction Serial Peripheral Interface
00713 #define    PRTIM0          3       // Power Reduction Timer/Counter0
00714 #define    PRTIM1          4       // Power Reduction Timer/Counter1
00715 #define    PRPSC0          5       // Power Reduction PSC0
00716 #define    PRPSC1          6       // Power Reduction PSC1
00717 #define    PRPSC2          7       // Power Reduction PSC2
00718 
00719 
00720 /* ***** PORTE ************************ */
00721 /* PORTE - Port E Data Register */
00722 #define    PORTE0          0       // 
00723 #define    PORTE1          1       // 
00724 #define    PORTE2          2       // 
00725 
00726 /* DDRE - Port E Data Direction Register */
00727 #define    DDE0            0       // 
00728 #define    DDE1            1       // 
00729 #define    DDE2            2       // 
00730 
00731 /* PINE - Port E Input Pins */
00732 #define    PINE0           0       // 
00733 #define    PINE1           1       // 
00734 #define    PINE2           2       // 
00735 
00736 
00737 /* ***** TIMER_COUNTER_0 ************** */
00738 /* TIMSK0 - Timer/Counter0 Interrupt Mask Register */
00739 #define    TOIE0           0       // Timer/Counter0 Overflow Interrupt Enable
00740 #define    OCIE0A          1       // Timer/Counter0 Output Compare Match A Interrupt Enable
00741 #define    OCIE0B          2       // Timer/Counter0 Output Compare Match B Interrupt Enable
00742 
00743 /* TIFR0 - Timer/Counter0 Interrupt Flag register */
00744 #define    TOV0            0       // Timer/Counter0 Overflow Flag
00745 #define    OCF0A           1       // Timer/Counter0 Output Compare Flag 0A
00746 #define    OCF0B           2       // Timer/Counter0 Output Compare Flag 0B
00747 
00748 /* TCCR0A - Timer/Counter  Control Register A */
00749 #define    WGM00           0       // Waveform Generation Mode
00750 #define    WGM01           1       // Waveform Generation Mode
00751 #define    COM0B0          4       // Compare Output Mode, Fast PWm
00752 #define    COM0B1          5       // Compare Output Mode, Fast PWm
00753 #define    COM0A0          6       // Compare Output Mode, Phase Correct PWM Mode
00754 #define    COM0A1          7       // Compare Output Mode, Phase Correct PWM Mode
00755 
00756 /* TCCR0B - Timer/Counter Control Register B */
00757 #define    CS00            0       // Clock Select
00758 #define    CS01            1       // Clock Select
00759 #define    CS02            2       // Clock Select
00760 #define    WGM02           3       // 
00761 #define    FOC0B           6       // Force Output Compare B
00762 #define    FOC0A           7       // Force Output Compare A
00763 
00764 /* TCNT0 - Timer/Counter0 */
00765 #define    TCNT0_0         0       // 
00766 #define    TCNT0_1         1       // 
00767 #define    TCNT0_2         2       // 
00768 #define    TCNT0_3         3       // 
00769 #define    TCNT0_4         4       // 
00770 #define    TCNT0_5         5       // 
00771 #define    TCNT0_6         6       // 
00772 #define    TCNT0_7         7       // 
00773 
00774 /* OCR0A - Timer/Counter0 Output Compare Register */
00775 #define    OCR0_0          0       // 
00776 #define    OCR0_1          1       // 
00777 #define    OCR0_2          2       // 
00778 #define    OCR0_3          3       // 
00779 #define    OCR0_4          4       // 
00780 #define    OCR0_5          5       // 
00781 #define    OCR0_6          6       // 
00782 #define    OCR0_7          7       // 
00783 
00784 /* OCR0B - Timer/Counter0 Output Compare Register */
00785 //#define  OCR0_0          0       // 
00786 //#define  OCR0_1          1       // 
00787 //#define  OCR0_2          2       // 
00788 //#define  OCR0_3          3       // 
00789 //#define  OCR0_4          4       // 
00790 //#define  OCR0_5          5       // 
00791 //#define  OCR0_6          6       // 
00792 //#define  OCR0_7          7       // 
00793 
00794 /* GTCCR - General Timer/Counter Control Register */
00795 #define    PSR10           0       // Prescaler Reset Timer/Counter1 and Timer/Counter0
00796 #define    ICPSEL1         6       // Timer1 Input Capture Selection Bit
00797 #define    TSM             7       // Timer/Counter Synchronization Mode
00798 
00799 
00800 /* ***** TIMER_COUNTER_1 ************** */
00801 /* TIMSK1 - Timer/Counter Interrupt Mask Register */
00802 #define    TOIE1           0       // Timer/Counter1 Overflow Interrupt Enable
00803 #define    OCIE1A          1       // Timer/Counter1 Output CompareA Match Interrupt Enable
00804 #define    OCIE1B          2       // Timer/Counter1 Output CompareB Match Interrupt Enable
00805 #define    ICIE1           5       // Timer/Counter1 Input Capture Interrupt Enable
00806 
00807 /* TIFR1 - Timer/Counter Interrupt Flag register */
00808 #define    TOV1            0       // Timer/Counter1 Overflow Flag
00809 #define    OCF1A           1       // Output Compare Flag 1A
00810 #define    OCF1B           2       // Output Compare Flag 1B
00811 #define    ICF1            5       // Input Capture Flag 1
00812 
00813 /* TCCR1A - Timer/Counter1 Control Register A */
00814 #define    WGM10           0       // Waveform Generation Mode
00815 #define    WGM11           1       // Waveform Generation Mode
00816 #define    COM1B0          4       // Compare Output Mode 1B, bit 0
00817 #define    COM1B1          5       // Compare Output Mode 1B, bit 1
00818 #define    COM1A0          6       // Comparet Ouput Mode 1A, bit 0
00819 #define    COM1A1          7       // Compare Output Mode 1A, bit 1
00820 
00821 /* TCCR1B - Timer/Counter1 Control Register B */
00822 #define    CS10            0       // Prescaler source of Timer/Counter 1
00823 #define    CS11            1       // Prescaler source of Timer/Counter 1
00824 #define    CS12            2       // Prescaler source of Timer/Counter 1
00825 #define    WGM12           3       // Waveform Generation Mode
00826 #define    WGM13           4       // Waveform Generation Mode
00827 #define    ICES1           6       // Input Capture 1 Edge Select
00828 #define    ICNC1           7       // Input Capture 1 Noise Canceler
00829 
00830 /* TCCR1C - Timer/Counter1 Control Register C */
00831 #define    FOC1B           6       // 
00832 #define    FOC1A           7       // 
00833 
00834 /* GTCCR - General Timer/Counter Control Register */
00835 #define    PSRSYNC         0       // Prescaler Reset Timer/Counter1 and Timer/Counter0
00836 //#define  TSM             7       // Timer/Counter Synchronization Mode
00837 
00838 
00839 /* ***** AD_CONVERTER ***************** */
00840 /* ADMUX - The ADC multiplexer Selection Register */
00841 #define    MUX0            0       // Analog Channel and Gain Selection Bits
00842 #define    MUX1            1       // Analog Channel and Gain Selection Bits
00843 #define    MUX2            2       // Analog Channel and Gain Selection Bits
00844 #define    MUX3            3       // Analog Channel and Gain Selection Bits
00845 #define    ADLAR           5       // Left Adjust Result
00846 #define    REFS0           6       // Reference Selection Bit 0
00847 #define    REFS1           7       // Reference Selection Bit 1
00848 
00849 /* ADCSRA - The ADC Control and Status register */
00850 #define    ADPS0           0       // ADC  Prescaler Select Bits
00851 #define    ADPS1           1       // ADC  Prescaler Select Bits
00852 #define    ADPS2           2       // ADC  Prescaler Select Bits
00853 #define    ADIE            3       // ADC Interrupt Enable
00854 #define    ADIF            4       // ADC Interrupt Flag
00855 #define    ADATE           5       // ADC Auto Trigger Enable
00856 #define    ADSC            6       // ADC Start Conversion
00857 #define    ADEN            7       // ADC Enable
00858 
00859 /* ADCH - ADC Data Register High Byte */
00860 #define    ADCH0           0       // ADC Data Register High Byte Bit 0
00861 #define    ADCH1           1       // ADC Data Register High Byte Bit 1
00862 #define    ADCH2           2       // ADC Data Register High Byte Bit 2
00863 #define    ADCH3           3       // ADC Data Register High Byte Bit 3
00864 #define    ADCH4           4       // ADC Data Register High Byte Bit 4
00865 #define    ADCH5           5       // ADC Data Register High Byte Bit 5
00866 #define    ADCH6           6       // ADC Data Register High Byte Bit 6
00867 #define    ADCH7           7       // ADC Data Register High Byte Bit 7
00868 
00869 /* ADCL - ADC Data Register Low Byte */
00870 #define    ADCL0           0       // ADC Data Register Low Byte Bit 0
00871 #define    ADCL1           1       // ADC Data Register Low Byte Bit 1
00872 #define    ADCL2           2       // ADC Data Register Low Byte Bit 2
00873 #define    ADCL3           3       // ADC Data Register Low Byte Bit 3
00874 #define    ADCL4           4       // ADC Data Register Low Byte Bit 4
00875 #define    ADCL5           5       // ADC Data Register Low Byte Bit 5
00876 #define    ADCL6           6       // ADC Data Register Low Byte Bit 6
00877 #define    ADCL7           7       // ADC Data Register Low Byte Bit 7
00878 
00879 /* ADCSRB - ADC Control and Status Register B */
00880 #define    ADTS0           0       // ADC Auto Trigger Source 0
00881 #define    ADTS1           1       // ADC Auto Trigger Source 1
00882 #define    ADTS2           2       // ADC Auto Trigger Source 2
00883 #define    ADTS3           3       // ADC Auto Trigger Source 3
00884 #define    ADASCR          4       // ADC on Amplified Channel Start Conversion Request Bit
00885 #define    ADHSM           7       // ADC High Speed Mode
00886 
00887 /* DIDR0 - Digital Input Disable Register 0 */
00888 #define    ADC0D           0       // ADC0 Digital input Disable
00889 #define    ADC1D           1       // ADC1 Digital input Disable
00890 #define    ADC2D           2       // ADC2 Digital input Disable
00891 #define    ADC3D           3       // ADC3 Digital input Disable
00892 #define    ADC4D           4       // ADC4 Digital input Disable
00893 #define    ADC5D           5       // ADC5 Digital input Disable
00894 #define    ADC6D           6       // ADC6 Digital input Disable
00895 #define    ADC7D           7       // ADC7 Digital input Disable
00896 
00897 /* DIDR1 - Digital Input Disable Register 0 */
00898 #define    ADC8D           0       // 
00899 #define    ADC9D           1       // 
00900 #define    ADC10D          2       // 
00901 #define    AMP0ND          3       // 
00902 #define    AMP0PD          4       // 
00903 #define    ACMP0D          5       // 
00904 
00905 /* AMP0CSR -  */
00906 #define    AMP0TS0         0       // 
00907 #define    AMP0TS1         1       // 
00908 #define    AMP0G0          4       // 
00909 #define    AMP0G1          5       // 
00910 #define    AMP0IS          6       // 
00911 #define    AMP0EN          7       // 
00912 
00913 /* AMP1CSR -  */
00914 #define    AMP1TS0         0       // 
00915 #define    AMP1TS1         1       // 
00916 #define    AMP1TS2         2       // 
00917 #define    AMP1G0          4       // 
00918 #define    AMP1G1          5       // 
00919 #define    AMP1IS          6       // 
00920 #define    AMP1EN          7       // 
00921 
00922 
00923 /* ***** LINUART ********************** */
00924 /* LINCR - LIN Control Register */
00925 #define    LCMD0           0       // LIN Command and Mode bit 0
00926 #define    LCMD1           1       // LIN Command and Mode bit 1
00927 #define    LCMD2           2       // LIN Command and Mode bit 2
00928 #define    LENA            3       // LIN or UART Enable
00929 #define    LCONF0          4       // LIN Configuration bit 0
00930 #define    LCONF1          5       // LIN Configuration bit 1
00931 #define    LIN13           6       // LIN Standard
00932 #define    LSWRES          7       // Software Reset
00933 
00934 /* LINSIR - LIN Status and Interrupt Register */
00935 #define    LRXOK           0       // Receive Performed Interrupt
00936 #define    LTXOK           1       // Transmit Performed Interrupt
00937 #define    LIDOK           2       // Identifier Interrupt
00938 #define    LERR            3       // Error Interrupt
00939 #define    LBUSY           4       // Busy Signal
00940 #define    LIDST0          5       // Identifier Status bit 0
00941 #define    LIDST1          6       // Identifier Status bit 1
00942 #define    LIDST2          7       // Identifier Status bit 2
00943 
00944 /* LINENIR - LIN Enable Interrupt Register */
00945 #define    LENRXOK         0       // Enable Receive Performed Interrupt
00946 #define    LENTXOK         1       // Enable Transmit Performed Interrupt
00947 #define    LENIDOK         2       // Enable Identifier Interrupt
00948 #define    LENERR          3       // Enable Error Interrupt
00949 
00950 /* LINERR - LIN Error Register */
00951 #define    LBERR           0       // Bit Error Flag
00952 #define    LCERR           1       // Checksum Error Flag
00953 #define    LPERR           2       // Parity Error Flag
00954 #define    LSERR           3       // Synchronization Error Flag
00955 #define    LFERR           4       // Framing Error Flag
00956 #define    LOVERR          5       // Overrun Error Flag
00957 #define    LTOERR          6       // Frame Time Out Error Flag
00958 #define    LABORT          7       // Abort Flag
00959 
00960 /* LINBTR - LIN Bit Timing Register */
00961 #define    LBT0            0       // LIN Bit Timing bit 0
00962 #define    LBT1            1       // LIN Bit Timing bit 1
00963 #define    LBT2            2       // LIN Bit Timing bit 2
00964 #define    LBT3            3       // LIN Bit Timing bit 3
00965 #define    LBT4            4       // LIN Bit Timing bit 4
00966 #define    LBT5            5       // LIN Bit Timing bit 5
00967 #define    LDISR           7       // Disable Bit Timing Resynchronization
00968 
00969 /* LINBRRL - LIN Baud Rate Low Register */
00970 #define    LDIV0           0       // 
00971 #define    LDIV1           1       // 
00972 #define    LDIV2           2       // 
00973 #define    LDIV3           3       // 
00974 #define    LDIV4           4       // 
00975 #define    LDIV5           5       // 
00976 #define    LDIV6           6       // 
00977 #define    LDIV7           7       // 
00978 
00979 /* LINBRRH - LIN Baud Rate High Register */
00980 #define    LDIV8           0       // 
00981 #define    LDIV9           1       // 
00982 #define    LDIV10          2       // 
00983 #define    LDIV11          3       // 
00984 
00985 /* LINDLR - LIN Data Length Register */
00986 #define    LRXDL0          0       // LIN Receive Data Length bit 0
00987 #define    LRXDL1          1       // LIN Receive Data Length bit 1
00988 #define    LRXDL2          2       // LIN Receive Data Length bit 2
00989 #define    LRXDL3          3       // LIN Receive Data Length bit 3
00990 #define    LTXDL0          4       // LIN Transmit Data Length bit 0
00991 #define    LTXDL1          5       // LIN Transmit Data Length bit 1
00992 #define    LTXDL2          6       // LIN Transmit Data Length bit 2
00993 #define    LTXDL3          7       // LIN Transmit Data Length bit 3
00994 
00995 /* LINIDR - LIN Identifier Register */
00996 #define    LID0            0       // Identifier bit 0
00997 #define    LID1            1       // Identifier bit 1
00998 #define    LID2            2       // Identifier bit 2
00999 #define    LID3            3       // Identifier bit 3
01000 #define    LID4            4       // Identifier bit 4 or Data Length bit 0
01001 #define    LID5            5       // Identifier bit 5 or Data Length bit 1
01002 #define    LP0             6       // Parity bit 0
01003 #define    LP1             7       // Parity bit 1
01004 
01005 /* LINSEL - LIN Data Buffer Selection Register */
01006 #define    LINDX0          0       // FIFO LIN Data Buffer Index bit 0
01007 #define    LINDX1          1       // FIFO LIN Data Buffer Index bit 1
01008 #define    LINDX2          2       // FIFO LIN Data Buffer Index bit 2
01009 #define    LAINC           3       // Auto Increment of Data Buffer Index (Active Low)
01010 
01011 /* LINDAT - LIN Data Register */
01012 #define    LDATA0          0       // 
01013 #define    LDATA1          1       // 
01014 #define    LDATA2          2       // 
01015 #define    LDATA3          3       // 
01016 #define    LDATA4          4       // 
01017 #define    LDATA5          5       // 
01018 #define    LDATA6          6       // 
01019 #define    LDATA7          7       // 
01020 
01021 
01022 /* ***** SPI ************************** */
01023 /* SPDR - SPI Data Register */
01024 #define    SPDR0           0       // SPI Data Register bit 0
01025 #define    SPDR1           1       // SPI Data Register bit 1
01026 #define    SPDR2           2       // SPI Data Register bit 2
01027 #define    SPDR3           3       // SPI Data Register bit 3
01028 #define    SPDR4           4       // SPI Data Register bit 4
01029 #define    SPDR5           5       // SPI Data Register bit 5
01030 #define    SPDR6           6       // SPI Data Register bit 6
01031 #define    SPDR7           7       // SPI Data Register bit 7
01032 
01033 /* SPSR - SPI Status Register */
01034 #define    SPI2X           0       // Double SPI Speed Bit
01035 #define    WCOL            6       // Write Collision Flag
01036 #define    SPIF            7       // SPI Interrupt Flag
01037 
01038 /* SPCR - SPI Control Register */
01039 #define    SPR0            0       // SPI Clock Rate Select 0
01040 #define    SPR1            1       // SPI Clock Rate Select 1
01041 #define    CPHA            2       // Clock Phase
01042 #define    CPOL            3       // Clock polarity
01043 #define    MSTR            4       // Master/Slave Select
01044 #define    DORD            5       // Data Order
01045 #define    SPE             6       // SPI Enable
01046 #define    SPIE            7       // SPI Interrupt Enable
01047 
01048 
01049 /* ***** WATCHDOG ********************* */
01050 /* WDTCSR - Watchdog Timer Control Register */
01051 #define    WDP0            0       // Watch Dog Timer Prescaler bit 0
01052 #define    WDP1            1       // Watch Dog Timer Prescaler bit 1
01053 #define    WDP2            2       // Watch Dog Timer Prescaler bit 2
01054 #define    WDE             3       // Watch Dog Enable
01055 #define    WDCE            4       // Watchdog Change Enable
01056 #define    WDP3            5       // Watchdog Timer Prescaler Bit 3
01057 #define    WDIE            6       // Watchdog Timeout Interrupt Enable
01058 #define    WDIF            7       // Watchdog Timeout Interrupt Flag
01059 
01060 
01061 /* ***** EXTERNAL_INTERRUPT *********** */
01062 /* EICRA - External Interrupt Control Register A */
01063 #define    ISC00           0       // External Interrupt Sense Control Bit
01064 #define    ISC01           1       // External Interrupt Sense Control Bit
01065 #define    ISC10           2       // External Interrupt Sense Control Bit
01066 #define    ISC11           3       // External Interrupt Sense Control Bit
01067 #define    ISC20           4       // External Interrupt Sense Control Bit
01068 #define    ISC21           5       // External Interrupt Sense Control Bit
01069 #define    ISC30           6       // External Interrupt Sense Control Bit
01070 #define    ISC31           7       // External Interrupt Sense Control Bit
01071 
01072 /* EIMSK - External Interrupt Mask Register */
01073 #define    INT0            0       // External Interrupt Request 0 Enable
01074 #define    INT1            1       // External Interrupt Request 1 Enable
01075 #define    INT2            2       // External Interrupt Request 2 Enable
01076 #define    INT3            3       // External Interrupt Request 3 Enable
01077 
01078 /* EIFR - External Interrupt Flag Register */
01079 #define    INTF0           0       // External Interrupt Flag 0
01080 #define    INTF1           1       // External Interrupt Flag 1
01081 #define    INTF2           2       // External Interrupt Flag 2
01082 #define    INTF3           3       // External Interrupt Flag 3
01083 
01084 
01085 /* ***** EEPROM *********************** */
01086 /* EEDR - EEPROM Data Register */
01087 #define    EEDR0           0       // EEPROM Data Register bit 0
01088 #define    EEDR1           1       // EEPROM Data Register bit 1
01089 #define    EEDR2           2       // EEPROM Data Register bit 2
01090 #define    EEDR3           3       // EEPROM Data Register bit 3
01091 #define    EEDR4           4       // EEPROM Data Register bit 4
01092 #define    EEDR5           5       // EEPROM Data Register bit 5
01093 #define    EEDR6           6       // EEPROM Data Register bit 6
01094 #define    EEDR7           7       // EEPROM Data Register bit 7
01095 
01096 /* EECR - EEPROM Control Register */
01097 #define    EERE            0       // EEPROM Read Enable
01098 #define    EEWE            1       // EEPROM Write Enable
01099 #define    EEMWE           2       // EEPROM Master Write Enable
01100 #define    EERIE           3       // EEPROM Ready Interrupt Enable
01101 
01102 
01103 /* ***** PSC ************************** */
01104 /* PIFR - PSC Interrupt Flag Register */
01105 #define    PEOP            0       // PSC End of Cycle Interrupt
01106 #define    PEV0            1       // PSC External Event 0 Interrupt
01107 #define    PEV1            2       // PSC External Event 1 Interrupt
01108 #define    PEV2            3       // PSC External Event 2 Interrupt
01109 
01110 /* PIM - PSC Interrupt Mask Register */
01111 #define    PEOPE           0       // PSC End of Cycle Interrupt Enable
01112 #define    PEVE0           1       // External Event 0 Interrupt Enable
01113 #define    PEVE1           2       // External Event 1 Interrupt Enable
01114 #define    PEVE2           3       // External Event 2 Interrupt Enable
01115 
01116 /* PMIC2 - PSC Module 2 Input Control Register */
01117 #define    PRFM20          0       // PSC Module 2 Input Mode bit 0
01118 #define    PRFM21          1       // PSC Module 2 Input Mode bit 1
01119 #define    PRFM22          2       // PSC Module 2 Input Mode bit 2
01120 #define    PAOC2           3       // PSC Module 2 Asynchronous Output Control
01121 #define    PFLTE2          4       // PSC Module 2 Input Filter Enable
01122 #define    PELEV2          5       // PSC Module 2 Input Level Selector
01123 #define    PISEL2          6       // PSC Module 2 Input Select
01124 #define    POVEN2          7       // PSC Module 2 Overlap Enable
01125 
01126 /* PMIC1 - PSC Module 1 Input Control Register */
01127 #define    PRFM10          0       // PSC Module 1 Input Mode bit 0
01128 #define    PRFM11          1       // PSC Module 1 Input Mode bit 1
01129 #define    PRFM12          2       // PSC Module 1 Input Mode bit 2
01130 #define    PAOC1           3       // PSC Module 1 Asynchronous Output Control
01131 #define    PFLTE1          4       // PSC Module 1 Input Filter Enable
01132 #define    PELEV1          5       // PSC Module 1 Input Level Selector
01133 #define    PISEL1          6       // PSC Module 1 Input Select
01134 #define    POVEN1          7       // PSC Module 1 Overlap Enable
01135 
01136 /* PMIC0 - PSC Module 0 Input Control Register */
01137 #define    PRFM00          0       // PSC Module 0 Input Mode bit 0
01138 #define    PRFM01          1       // PSC Module 0 Input Mode bit 1
01139 #define    PRFM02          2       // PSC Module 0 Input Mode bit 2
01140 #define    PAOC0           3       // PSC Module 0 Asynchronous Output Control
01141 #define    PFLTE0          4       // PSC Module 0 Input Filter Enable
01142 #define    PELEV0          5       // PSC Module 0 Input Level Selector
01143 #define    PISEL0          6       // PSC Module 0 Input Select
01144 #define    POVEN0          7       // PSC Module 0 Overlap Enable
01145 
01146 /* PCTL - PSC Control Register */
01147 #define    PRUN            0       // PSC Run
01148 #define    PCCYC           1       // PSC Complete Cycle
01149 #define    PCLKSEL         5       // PSC Input Clock Select
01150 #define    PPRE0           6       // PSC Prescaler Select bit 0
01151 #define    PPRE1           7       // PSC Prescaler Select bit 1
01152 
01153 /* POC - PSC Output Configuration */
01154 #define    POEN0A          0       // PSC Output 0A Enable
01155 #define    POEN0B          1       // PSC Output 0B Enable
01156 #define    POEN1A          2       // PSC Output 1A Enable
01157 #define    POEN1B          3       // PSC Output 1B Enable
01158 #define    POEN2A          4       // PSC Output 2A Enable
01159 #define    POEN2B          5       // PSC Output 2B Enable
01160 
01161 /* PCNF - PSC Configuration Register */
01162 #define    POPA            2       // PSC Output A Polarity
01163 #define    POPB            3       // PSC Output B Polarity
01164 #define    PMODE           4       // PSC Mode
01165 #define    PULOCK          5       // PSC Update Lock
01166 
01167 /* PSYNC - PSC Synchro Configuration */
01168 #define    PSYNC00         0       // Selection of Synchronization Out for ADC
01169 #define    PSYNC01         1       // Selection of Synchronization Out for ADC
01170 #define    PSYNC10         2       // Selection of Synchronization Out for ADC
01171 #define    PSYNC11         3       // Selection of Synchronization Out for ADC
01172 #define    PSYNC20         4       // Selection of Synchronization Out for ADC
01173 #define    PSYNC21         5       // Selection of Synchronization Out for ADC
01174 
01175 /* POCRxRBH - PSC Output Compare RB Register High */
01176 #define    POCR_RB_8       0       // 
01177 #define    POCR_RB_9       1       // 
01178 #define    POCR_RB_00      2       // 
01179 #define    POCR_RB_01      3       // 
01180 
01181 /* POCRxRBL - PSC Output Compare RB Register Low */
01182 #define    POCR_RB_0       0       // 
01183 #define    POCR_RB_1       1       // 
01184 #define    POCR_RB_2       2       // 
01185 #define    POCR_RB_3       3       // 
01186 #define    POCR_RB_4       4       // 
01187 #define    POCR_RB_5       5       // 
01188 #define    POCR_RB_6       6       // 
01189 #define    POCR_RB_7       7       // 
01190 
01191 /* POCR2SBH - PSC Module 2 Output Compare SB Register High */
01192 #define    POCR2SB_8       0       // 
01193 #define    POCR2SB_9       1       // 
01194 #define    POCR2SB_00      2       // 
01195 #define    POCR2SB_01      3       // 
01196 
01197 /* POCR2SBL - PSC Module 2 Output Compare SB Register Low */
01198 #define    POCR2SB_0       0       // 
01199 #define    POCR2SB_1       1       // 
01200 #define    POCR2SB_2       2       // 
01201 #define    POCR2SB_3       3       // 
01202 #define    POCR2SB_4       4       // 
01203 #define    POCR2SB_5       5       // 
01204 #define    POCR2SB_6       6       // 
01205 #define    POCR2SB_7       7       // 
01206 
01207 /* POCR2RAH - PSC Module 2 Output Compare RA Register High */
01208 #define    POCR2RA_8       0       // 
01209 #define    POCR2RA_9       1       // 
01210 #define    POCR2RA_00      2       // 
01211 #define    POCR2RA_01      3       // 
01212 
01213 /* POCR2RAL - PSC Module 2 Output Compare RA Register Low */
01214 #define    POCR2RA_0       0       // 
01215 #define    POCR2RA_1       1       // 
01216 #define    POCR2RA_2       2       // 
01217 #define    POCR2RA_3       3       // 
01218 #define    POCR2RA_4       4       // 
01219 #define    POCR2RA_5       5       // 
01220 #define    POCR2RA_6       6       // 
01221 #define    POCR2RA_7       7       // 
01222 
01223 /* POCR2SAH - PSC Module 2 Output Compare SA Register High */
01224 #define    POCR2SA_8       0       // 
01225 #define    POCR2SA_9       1       // 
01226 #define    POCR2SA_00      2       // 
01227 #define    POCR2SA_01      3       // 
01228 
01229 /* POCR2SAL - PSC Module 2 Output Compare SA Register Low */
01230 #define    POCR2SA_0       0       // 
01231 #define    POCR2SA_1       1       // 
01232 #define    POCR2SA_2       2       // 
01233 #define    POCR2SA_3       3       // 
01234 #define    POCR2SA_4       4       // 
01235 #define    POCR2SA_5       5       // 
01236 #define    POCR2SA_6       6       // 
01237 #define    POCR2SA_7       7       // 
01238 
01239 /* POCR1SBH - PSC Module 1 Output Compare SB Register High */
01240 #define    POCR1SB_8       0       // 
01241 #define    POCR1SB_9       1       // 
01242 #define    POCR1SB_00      2       // 
01243 #define    POCR1SB_01      3       // 
01244 
01245 /* POCR1SBL - PSC Module 1 Output Compare SB Register Low */
01246 #define    POCR1SB_0       0       // 
01247 #define    POCR1SB_1       1       // 
01248 #define    POCR1SB_2       2       // 
01249 #define    POCR1SB_3       3       // 
01250 #define    POCR1SB_4       4       // 
01251 #define    POCR1SB_5       5       // 
01252 #define    POCR1SB_6       6       // 
01253 #define    POCR1SB_7       7       // 
01254 
01255 /* POCR1RAH - PSC Module 1 Output Compare RA Register High */
01256 #define    POCR1RA_8       0       // 
01257 #define    POCR1RA_9       1       // 
01258 #define    POCR1RA_00      2       // 
01259 #define    POCR1RA_01      3       // 
01260 
01261 /* POCR1RAL - PSC Module 1 Output Compare RA Register Low */
01262 #define    POCR1RA_0       0       // 
01263 #define    POCR1RA_1       1       // 
01264 #define    POCR1RA_2       2       // 
01265 #define    POCR1RA_3       3       // 
01266 #define    POCR1RA_4       4       // 
01267 #define    POCR1RA_5       5       // 
01268 #define    POCR1RA_6       6       // 
01269 #define    POCR1RA_7       7       // 
01270 
01271 /* POCR1SAH - PSC Output Compare SA Register High */
01272 #define    POCR1SA_8       0       // 
01273 #define    POCR1SA_9       1       // 
01274 #define    POCR1SA_00      2       // 
01275 #define    POCR1SA_01      3       // 
01276 
01277 /* POCR1SAL - PSC Module 1 Output Compare SA Register Low */
01278 #define    POCR1SA_0       0       // 
01279 #define    POCR1SA_1       1       // 
01280 #define    POCR1SA_2       2       // 
01281 #define    POCR1SA_3       3       // 
01282 #define    POCR1SA_4       4       // 
01283 #define    POCR1SA_5       5       // 
01284 #define    POCR1SA_6       6       // 
01285 #define    POCR1SA_7       7       // 
01286 
01287 /* POCR0SBH - PSC Output Compare SB Register High */
01288 #define    POCR0SB_8       0       // 
01289 #define    POCR0SB_9       1       // 
01290 #define    POCR0SB_00      2       // 
01291 #define    POCR0SB_01      3       // 
01292 
01293 /* POCR0SBL - PSC Module 0 Output Compare SB Register Low */
01294 #define    POCR0SB_0       0       // 
01295 #define    POCR0SB_1       1       // 
01296 #define    POCR0SB_2       2       // 
01297 #define    POCR0SB_3       3       // 
01298 #define    POCR0SB_4       4       // 
01299 #define    POCR0SB_5       5       // 
01300 #define    POCR0SB_6       6       // 
01301 #define    POCR0SB_7       7       // 
01302 
01303 /* POCR0RAH - PSC Module 0 Output Compare RA Register High */
01304 #define    POCR0RA_8       0       // 
01305 #define    POCR0RA_9       1       // 
01306 #define    POCR0RA_00      2       // 
01307 #define    POCR0RA_01      3       // 
01308 
01309 /* POCR0RAL - PSC Module 0 Output Compare RA Register Low */
01310 #define    POCR0RA_0       0       // 
01311 #define    POCR0RA_1       1       // 
01312 #define    POCR0RA_2       2       // 
01313 #define    POCR0RA_3       3       // 
01314 #define    POCR0RA_4       4       // 
01315 #define    POCR0RA_5       5       // 
01316 #define    POCR0RA_6       6       // 
01317 #define    POCR0RA_7       7       // 
01318 
01319 /* POCR0SAH - PSC Module 0 Output Compare SA Register High */
01320 #define    POCR0SA_8       0       // 
01321 #define    POCR0SA_9       1       // 
01322 #define    POCR0SA_00      2       // 
01323 #define    POCR0SA_01      3       // 
01324 
01325 /* POCR0SAL - PSC Module 0 Output Compare SA Register Low */
01326 #define    POCR0SA_0       0       // 
01327 #define    POCR0SA_1       1       // 
01328 #define    POCR0SA_2       2       // 
01329 #define    POCR0SA_3       3       // 
01330 #define    POCR0SA_4       4       // 
01331 #define    POCR0SA_5       5       // 
01332 #define    POCR0SA_6       6       // 
01333 #define    POCR0SA_7       7       // 
01334 
01335 
01336 
01337 /* ***** LOCKSBITS ******************************************************** */
01338 #define    LB1             0       // Lock bit
01339 #define    LB2             1       // Lock bit
01340 #define    BLB01           2       // Boot Lock bit
01341 #define    BLB02           3       // Boot Lock bit
01342 #define    BLB11           4       // Boot lock bit
01343 #define    BLB12           5       // Boot lock bit
01344 
01345 
01346 /* ***** FUSES ************************************************************ */
01347 /* LOW fuse bits */
01348 #define    CKSEL0          0       // Select Clock Source
01349 #define    CKSEL1          1       // Select Clock Source
01350 #define    CKSEL2          2       // Select Clock Source
01351 #define    CKSEL3          3       // Select Clock Source
01352 #define    SUT0            4       // Select start-up time
01353 #define    SUT1            5       // Select start-up time
01354 #define    CKOUT           6       // Oscillator output option
01355 #define    CKDIV8          7       // Divide clock by 8
01356 
01357 /* HIGH fuse bits */
01358 #define    BOOTRST         0       // Select Reset Vector
01359 #define    BOOTSZ0         1       // Select Boot Size
01360 #define    BOOTSZ1         2       // Select Boot Size
01361 #define    EESAVE          3       // EEPROM memory is preserved through chip erase
01362 #define    WDTON           4       // Watchdog timer always on
01363 #define    SPIEN           5       // Enable Serial programming and Data Downloading
01364 #define    DWEN            6       // dwbugWIRE Enable
01365 #define    RSTDISBL        7       // External Reset Disable
01366 
01367 /* EXTENDED fuse bits */
01368 #define    BODLEVEL0       0       // Brown-out Detector Trigger Level
01369 #define    BODLEVEL1       1       // Brown-out Detector Trigger Level
01370 #define    BODLEVEL2       2       // Brown-out Detector Trigger Level
01371 #define    PSCBRV          3       // PSC Outputs xB Reset Value
01372 #define    PSCARV          4       // PSC Outputs xA Reset Value
01373 #define    PSCRB           5       // PSC Reset Behavior
01374 
01375 
01376 
01377 /* ***** CPU REGISTER DEFINITIONS ***************************************** */
01378 #define    XH              r27
01379 #define    XL              r26
01380 #define    YH              r29
01381 #define    YL              r28
01382 #define    ZH              r31
01383 #define    ZL              r30
01384 
01385 
01386 
01387 /* ***** DATA MEMORY DECLARATIONS ***************************************** */
01388 #define    FLASHEND        0x7fff  // Note: Byte address
01389 #define    IOEND           0x00ff
01390 #define    SRAM_START      0x0100
01391 #define    SRAM_SIZE       2048
01392 #define    RAMEND          0x08ff
01393 #define    XRAMEND         0x0000
01394 #define    E2END           0x03ff
01395 #define    EEPROMEND       0x03ff
01396 #define    EEADRBITS       10
01397 
01398 
01399 
01400 /* ***** BOOTLOADER DECLARATIONS ****************************************** */
01401 #define    NRWW_START_ADDR 0x3800
01402 #define    NRWW_STOP_ADDR  0x3fff
01403 #define    RWW_START_ADDR  0x0
01404 #define    RWW_STOP_ADDR   0x37ff
01405 #define    PAGESIZE        64
01406 #define    FIRSTBOOTSTART  0x3f00
01407 #define    SECONDBOOTSTART 0x3e00
01408 #define    THIRDBOOTSTART  0x3c00
01409 #define    FOURTHBOOTSTART 0x3800
01410 #define    SMALLBOOTSTART  FIRSTBOOTSTART
01411 #define    LARGEBOOTSTART  FOURTHBOOTSTART
01412 
01413 #endif /* ENABLE_BIT_DEFINITIONS */
01414 
01415 
01416 
01417 /* ***** INTERRUPT VECTORS ************************************************ */
01418 #define    RESET_vect      (0x00)  // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
01419 #define    ANA_COMP0_vect  (0x04)  // Analog Comparator 0
01420 #define    ANA_COMP1_vect  (0x08)  // Analog Comparator 1
01421 #define    ANA_COMP2_vect  (0x0c)  // Analog Comparator 2
01422 #define    ANA_COMP3_vect  (0x10)  // Analog Comparator 3
01423 #define    PSC_FAULT_vect  (0x14)  // PSC Fault
01424 #define    PSC_END_CYCLE_vect (0x18)  // PSC End of Cycle
01425 #define    INT0_vect       (0x1c)  // External Interrupt Request 0
01426 #define    INT1_vect       (0x20)  // External Interrupt Request 1
01427 #define    INT2_vect       (0x24)  // External Interrupt Request 2
01428 #define    INT3_vect       (0x28)  // External Interrupt Request 3
01429 #define    TIMER1_CAPT_vect (0x2c)  // Timer/Counter1 Capture Event
01430 #define    TIMER1_COMPA_vect (0x30)  // Timer/Counter1 Compare Match A
01431 #define    TIMER1_COMPB_vect (0x34)  // Timer/Counter1 Compare Match B
01432 #define    TIMER1_OVF_vect (0x38)  // Timer1/Counter1 Overflow
01433 #define    TIMER0_COMPA_vect (0x3c)  // Timer/Counter0 Compare Match A
01434 #define    TIMER0_COMPB_vect (0x40)  // Timer/Counter0 Compare Match B
01435 #define    TIMER0_OVF_vect (0x44)  // Timer/Counter0 Overflow
01436 #define    CAN_INT_vect    (0x48)  // CAN MOB, Burst, General Errors
01437 #define    CAN_TOVF_vect   (0x4c)  // CAN Timer Overflow
01438 #define    LIN_TC_vect     (0x50)  // LIN Transfer Complete
01439 #define    LIN_ERR_vect    (0x54)  // LIN Error
01440 #define    PCINT0_vect     (0x58)  // Pin Change Interrupt Request 0
01441 #define    PCINT1_vect     (0x5c)  // Pin Change Interrupt Request 1
01442 #define    PCINT2_vect     (0x60)  // Pin Change Interrupt Request 2
01443 #define    PCINT3_vect     (0x64)  // Pin Change Interrupt Request 3
01444 #define    SPI_STC_vect    (0x68)  // SPI Serial Transfer Complete
01445 #define    ADC_vect        (0x6c)  // ADC Conversion Complete
01446 #define    WDT_vect        (0x70)  // Watchdog Time-Out Interrupt
01447 #define    EE_RDY_vect     (0x74)  // EEPROM Ready
01448 #define    SPM_RDY_vect    (0x78)  // Store Program Memory Read
01449 
01450 
01451 
01452 #endif /* __IOPWM324_H (define part) */
01453 
01454 #pragma language=default
01455 
01456 #endif  /* __IOPWM324_H (SFR part)*/
01457 
01458 /* ***** END OF FILE ****************************************************** */