clksys_driver.c

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/* This file has been prepared for Doxygen automatic documentation generation.*/
#include "clksys_driver.h"

void CCPWrite( volatile uint8_t * address, uint8_t value )
{
#ifdef __ICCAVR__

        // Store global interrupt setting in scratch register and disable interrupts.
        asm("in  R1, 0x3F \n"
            "cli"
            );

        // Move destination address pointer to Z pointer registers.
        asm("movw r30, r16");
#ifdef RAMPZ
        asm("ldi  R16, 0 \n"
            "out  0x3B, R16"
            );

#endif
        asm("ldi  r16,  0xD8 \n"
            "out  0x34, r16  \n"
#if (__MEMORY_MODEL__ == 1)
            "st     Z,  r17  \n");
#elif (__MEMORY_MODEL__ == 2)
            "st     Z,  r18  \n");
#else /* (__MEMORY_MODEL__ == 3) || (__MEMORY_MODEL__ == 5) */
            "st     Z,  r19  \n");
#endif /* __MEMORY_MODEL__ */

        // Restore global interrupt setting from scratch register.
        asm("out  0x3F, R1");

#elif defined __GNUC__
        AVR_ENTER_CRITICAL_REGION( );
        volatile uint8_t * tmpAddr = address;
#ifdef RAMPZ
        RAMPZ = 0;
#endif
        asm volatile(
                "movw r30,  %0"       "\n\t"
                "ldi  r16,  %2"       "\n\t"
                "out   %3, r16"       "\n\t"
                "st     Z,  %1"       "\n\t"
                :
                : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP)
                : "r16", "r30", "r31"
                );

        AVR_LEAVE_CRITICAL_REGION( );
#endif
}

void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange,
                         bool lowPower32kHz,
                         OSC_XOSCSEL_t xoscModeSelection )
{
        OSC.XOSCCTRL = (uint8_t) freqRange |
                       ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
                       xoscModeSelection;
}


void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor )
{
        factor &= OSC_PLLFAC_gm;
        OSC.PLLCTRL = (uint8_t) clockSource | ( factor << OSC_PLLFAC_gp );
}


uint8_t CLKSYS_Disable( uint8_t oscSel )
{
        OSC.CTRL &= ~oscSel;
        uint8_t clkEnabled = OSC.CTRL & oscSel;
        return clkEnabled;
}


void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor,
                               CLK_PSBCDIV_t PSBCfactor )
{
        uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
        CCPWrite( &CLK.PSCTRL, PSconfig );
}


uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource )
{
        uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource;
        CCPWrite( &CLK.CTRL, clkCtrl );
        clkCtrl = ( CLK.CTRL & clockSource );
        return clkCtrl;
}


void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource )
{
        CLK.RTCCTRL = ( CLK.RTCCTRL & ~CLK_RTCSRC_gm ) |
                      clockSource |
                      CLK_RTCEN_bm;
}


void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference )
{
        OSC.DFLLCTRL = ( OSC.DFLLCTRL & ~clkSource ) |
                       ( extReference ? clkSource : 0 );
        if (clkSource == OSC_RC2MCREF_bm) {
                DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
        } else if (clkSource == OSC_RC32MCREF_gm) {
                DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
        }
}


void CLKSYS_XOSC_FailureDetection_Enable( void )
{
        CCPWrite( &OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
}


void CLKSYS_Configuration_Lock( void )
{
        CCPWrite( &CLK.LOCK, CLK_LOCK_bm );
}