61 #if defined(RTC32) || defined(__DOXYGEN__)
66 VBAT.CTRL = VBAT_RESET_bm;
69 VBAT.CTRL |= VBAT_ACCEN_bm;
72 VBAT.CTRL |= VBAT_XOSCFDEN_bm | VBAT_XOSCSEL_bm;
80 VBAT.CTRL |= VBAT_XOSCEN_bm;
83 while (!(VBAT.STATUS & VBAT_XOSCRDY_bm));
88 bool rtc_is_busy(
void ) {
90 return RTC32.SYNCCTRL & RTC32_SYNCBUSY_bm;
92 return RTC.STATUS & RTC_SYNCBUSY_bm;
107 OSC.CTRL |= OSC_RC32KEN_bm;
108 while (!(OSC.STATUS & OSC_RC32KRDY_bm));
109 CLK.RTCCTRL = CLK_RTCSRC_RCOSC_gc | CLK_RTCEN_bm;
113 RTC_TEST.CTRL &= ~RTC_TEST_START_bm;
114 while (rtc_is_busy());
115 RTC_TEST.PER = 0xffff;
118 while (rtc_is_busy());
119 RTC_TEST.INTCTRL = RTC_TEST_COMPINTLVL_LO_gc;
120 RTC_TEST.INTFLAGS = RTC_TEST_COMPIF_bm;
122 RTC_TEST.CTRL |= RTC_TEST_START_bm;
136 while (rtc_is_busy());
139 while (rtc_is_busy());
140 RTC_TEST.CTRL |= RTC_TEST_START_bm;
142 #ifdef CLASSB_FREQ_TEST
146 #ifdef CLASSB_INT_MON