| BLDC control on ATAVRMC303 with ATxMega128A1

adc_drv.h
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1
14 #ifndef ADC_DRV_H
15 #define ADC_DRV_H
16
17 //_____ I N C L U D E S ____________________________________________________
18
19 #ifndef ADHSM
20 #define ADHSM 7
21 #endif
22
26 //_____ M A C R O S ________________________________________________________
27
31
35 #define Enable_adc() (ADCB.CTRLB |= ADC_ENABLE_bm)
36
41 #define Right_adjust_adc_result() (ADCB.CTRLA = ((ADCB.CTRLA & ~ ADC_RESOLUTION_LEFT12BIT_gc) | ADC_RESOLUTION_12BIT_gc))
42 #define Left_adjust_adc_result() (ADCB.CTRLA |= ADC_RESOLUTION_LEFT12BIT_gc)
43
48 #define Enable_adc_high_speed_mode() (ADCSRB |= (1<<ADHSM))
49 #define Disable_adc_high_speed_mode() (ADCSRB &= ~(1<<ADHSM))
50
52
56 #define Enable_internal_vref() (ADCB.REFCTRL = ADC_REFSEL_INT1V_gc)
57 #define Enable_internal_vref_decoupled() (ADCB.REFCTRL = ADC_REFSEL_INT1VDECOUPLED_gc)
58 #define Enable_vcc_vref() (ADCB.REFCTRL = ADC_REFSEL_INTVCC_gc)
59 #define Enable_vcc_vref_decoupled() (ADCB.REFCTRL = ADC_REFSEL_INTVCCDECOUPLED_gc)
60 #define Enable_external_vref() (ADCB.REFCTRL = ADC_REFSEL_EXT_gc)
61
63
67 #define Enable_all_it() (SREG |= (0x80) )
68 #define Disable_all_it() (SREG &= ~(0x80) )
69 #define Enable_adc_it() (ADCSRA |= (1<<ADIE) )
70 #define Disable_adc_it() (ADCSRA &= ~(1<<ADIE) )
71 #define Clear_adc_flag() (ADCSRA &= (1<<ADIF) )
72
77 #define Set_prescaler(prescaler) (ADCSRA &= ~((1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)),\
78 ADCSRA |= (prescaler) )
79
84 #define Clear_adc_mux() (ADMUX &= ~((1<<MUX3)|(1<<MUX2)|(1<<MUX1)|(1<<MUX0)) )
85 #define Select_adc_channel(channel) (Clear_adc_mux(), ADMUX |= (channel) )
86
91
95 #define Start_conv() (ADCB.CTRLB |= ADC_CH0START_bm)
96 #define Start_conv_channel(channel) (Select_adc_channel(channel), Start_conv() )
97 #define Start_amplified_conv() (ADCSRB |= (1<<ADASCR) )
98 #define Stop_amplified_conv() (ADCSRB &= ~(1<<ADASCR) )
99 #define Start_amplified_conv_channel(channel) (Select_adc_channel(channel), Start_amplified_conv() )
100
105 #define Start_conv_idle() (SMCR |= (1<<SM0)|(1<<SE) )
106 #define Start_conv_idle_channel(channel) (Select_adc_channel(channel), Start_conv_idle() )
107 #define Clear_sleep_mode() (SMCR &= ~(1<<SM0)|(1<<SE) )
108
111
115 #define Adc_get_8_bits_result() ((U8)(ADCH))
116 #define Adc_get_10_bits_result() ((U16)(ADCL+((U16)(ADCH<<8))))
117
119
123 #define Disable_adc() (ADCB.CTRLA &= ~ADC_ENABLE_bm)
124
129 #define Is_adc_conv_finished() (ADCB.INTFLAGS & ADC_CH0IF_bm)
130 #define Is_adc_conv_not_finished() (ADCB.INTFLAGS & ADC_CH0IF_bm)) ? FALSE : TRUE )
131
134
135 //_____ D E F I N I T I O N S ______________________________________________
136
137 //_____ F U N C T I O N S __________________________________________________
141
146 void init_adc(void);
148
150
151 #endif // ADC_DRV_H
init_adc
void init_adc(void)
Configures the ADC accordingly to the ADC Define Configuration values.
Definition: adc_drv.c:35