/*
  * \file
  *
  * \brief Example code for testing crystal stability and robustness. The
  * firmware will output the crystal clock on a I/O pin that can be probed
  * with a standard 10X oscilloscope probe. DO NOT probe the crystal directly
  * if you do not have very high impedance probes indeded for crystal
  * measurements. The output clock will be devided by 2. NOTE: The correct 
  * device must be set by a define. 
  *
  *
  * Copyright (C) 2009 Atmel Corporation. All rights reserved.
  *
  * \page License
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
  * this list of conditions and the following disclaimer.
  *
  * 2. Redistributions in binary form must reproduce the above copyright notice,
  * this list of conditions and the following disclaimer in the documentation
  * and/or other materials provided with the distribution.
  *
  * 3. The name of Atmel may not be used to endorse or promote products derived
  * from this software without specific prior written permission.
  *
  * 4. This software may only be redistributed and used in connection with an
  * Atmel AVR product.
  *
  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  * DAMAGE.
  *
  *
  * Devices                      Define                          
  * supported
  *
  * ATmega8              ATMEGA8
  * ATmega8A                     ATMEGA8
  * ATmega16                     ATMEGA16_32
  * ATmega16A            ATMEGA16_32
  * ATmega32                     ATMEGA16_32     
  * ATmega32A            ATMEGA16_32
  * ATmega64                     ATMEGA64_128
  * ATmega64A            ATMEGA64_128    
  * ATmega128            ATMEGA64_128
  * ATmega128A           ATMEGA64_128
  * ATmega640            ATMEGA640_1280_2560
  * ATmega1280           ATMEGA640_1280_2560
  * ATmega1281           ATMEGA640_1280_2560
  * ATmega2560           ATMEGA640_1280_2560
  * ATmega2561           ATMEGA640_1280_2560
  * ATmega162            ATMEGA162
  * ATmega165A           ATMEGA169
  * ATmega165P           ATMEGA169
  * ATmega165PA          ATMEGA169
  * ATmega169            ATMEGA169
  * ATmega169A           ATMEGA169
  * ATmega169P           ATMEGA169
  * ATmega169PA          ATMEGA169
  * ATmega325A           ATMEGA329_649
  * ATmega325P           ATMEGA329_649
  * ATmega325PA          ATMEGA329_649
  * ATmega3250A          ATMEGA329_649
  * ATmega3250P          ATMEGA329_649
  * ATmega3250PA         ATMEGA329_649
  * ATmega329            ATMEGA329_649
  * ATmega329A           ATMEGA329_649
  * ATmega329P           ATMEGA329_649
  * ATmega329PA          ATMEGA329_649
  * ATmega3290A          ATMEGA329_649
  * ATmega3290P          ATMEGA329_649
  * ATmega3290PA         ATMEGA329_649
  * ATmega645A           ATMEGA329_649
  * ATmega645P           ATMEGA329_649
  * ATmega6450A          ATMEGA329_649
  * ATmega6450P          ATMEGA329_649
  * ATmega649            ATMEGA329_649
  * ATmega6490           ATMEGA329_649
  * ATmega649A           ATMEGA329_649
  * ATmega649P           ATMEGA329_649
  * ATmega6490A          ATMEGA329_649
  * ATmega6490P          ATMEGA329_649
  * ATmega48                     ATMEGA48_88_168
  * ATmega48A            ATMEGA48_88_168
  * ATmega88                     ATMEGA48_88_168
  * ATmega88A            ATMEGA48_88_168
  * ATmega168            ATMEGA48_88_168
  * ATmega168A           ATMEGA48_88_168
  * ATmega48P            ATMEGA48_88_168
  * ATmega48PA           ATMEGA48_88_168
  * ATmega88P            ATMEGA48_88_168
  * ATmega88PA           ATMEGA48_88_168
  * ATmega168P           ATMEGA48_88_168
  * ATmega168PA          ATMEGA48_88_168
  * ATmega164A           ATMEGA164_324_644_1284
  * ATmega164P           ATMEGA164_324_644_1284
  * ATmega164PA          ATMEGA164_324_644_1284
  * ATmega324A           ATMEGA164_324_644_1284
  * ATmega324P           ATMEGA164_324_644_1284
  * ATmega324PA          ATMEGA164_324_644_1284
  * ATmega644A           ATMEGA164_324_644_1284
  * ATmega644P           ATMEGA164_324_644_1284
  * ATmega644PA          ATMEGA164_324_644_1284
  * ATmega1284P          ATMEGA164_324_644_1284
  */

  
#include <avr/io.h>

// Select your define from the list above
#define ATMEGA8

/*============================ ATMEGA48_88_168 ================================*/
#ifdef ATMEGA48_88_168
int main( void )
{
         // Crystal clock will be output on PORTB3 (divided by 2)
         DDRB |= (1<<PORTB3);

         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2A  =  0;
         TCCR2A = (0<<COM2A1)|(1<<COM2A0)|(1<<WGM21)|(0<<WGM20);
         TCCR2B = (0<<WGM22)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR   = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA8 ========================================*/
#ifdef ATMEGA8
int main( void )
{
         // Crystal clock will be output on PORTB3 (divided by 2)
         DDRB |= (1<<PORTB3);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2 = 0;
         TCCR2 = (0<<COM21)|(1<<COM20)|(1<<WGM21)|(0<<WGM20)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA16_32 ====================================*/
#ifdef ATMEGA16_32
int main( void )
{
         // Crystal clock will be output on PORTD7 (divided by 2)
         DDRD |= (1<<PORTD7);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2 = 0;
         TCCR2 = (0<<COM21)|(1<<COM20)|(1<<WGM21)|(0<<WGM20)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA64_128 ===================================*/
#ifdef ATMEGA64_128
int main( void )
{
         // Crystal clock will be output on PORTB4 (divided by 2)
         DDRB |= (1<<PORTB4);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR0 = 0;
         TCCR0 = (0<<COM21)|(1<<COM20)|(1<<WGM21)|(0<<WGM20)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR = (1<<AS0);

         while(1){}
}
#endif

/*============================ ATMEGA640_1280_2560 =============================*/
#ifdef ATMEGA640_1280_2560
int main( void )
{
         // Crystal clock will be output on PORTB4 (divided by 2)
         DDRB |= (1<<PORTB4);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2A = 0;
         TCCR2A = (0<<COM2A1)|(1<<COM2A0)|(1<<WGM21)|(0<<WGM20);
         TCCR2B = (0<<WGM22)|(0<<CS22)|(0<<CS21)|(1<<CS20);

         ASSR = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA162 ======================================*/
#ifdef ATMEGA162
int main( void )
{
         // Crystal clock will be output on PORTB1 (divided by 2)
         DDRB |= (1<<PORTB1);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR0 = 0;
         TCCR2 = (0<<COM21)|(1<<COM20)|(1<<WGM21)|(0<<WGM20)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA169 ======================================*/
#ifdef ATMEGA169
int main( void )
{
         // Crystal clock will be output on PORTB7 (divided by 2)
         DDRB |= (1<<PORTB7);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2A  =  0;
         TCCR2A = (0<<COM2A1)|(1<<COM2A0)|(1<<WGM21)|(0<<WGM20)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR   = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA329_649 =================================*/
#ifdef ATMEGA329_649
int main( void )
{
         // Crystal clock will be output on PORTB7 (divided by 2)
         DDRB |= (1<<PORTB7);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2A  =  0;
         TCCR2A = (0<<COM2A1)|(1<<COM2A0)|(1<<WGM21)|(0<<WGM20)|(0<<CS22)|(0<<CS21)|(1<<CS20);
         ASSR   = (1<<AS2);

         while(1){}
}
#endif

/*============================ ATMEGA164_324_644_1284 ========================*/
#ifdef ATMEGA164_324_644_1284
int main( void )
{
         // Crystal clock will be output on PORTB4 (divided by 2)
         DDRD |= (1<<PORTD7);
         
         // Enable CTC mode with toggle on compare match. Precale 1 and top at 0
         OCR2A = 0;
         TCCR2A = (0<<COM2A1)|(1<<COM2A0)|(1<<WGM21)|(0<<WGM20);
         TCCR2B = (0<<WGM22)|(0<<CS22)|(0<<CS21)|(1<<CS20);

         ASSR = (1<<AS2);

         while(1){}
}
#endif

