# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHz} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RGMII_RXC} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RGMII_RX_CTL} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {USER_RST} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDC} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RGMII_TXC} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RGMII_TX_CTL} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_TX} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDIO} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {RGMII_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RGMII_TXD} -port_direction {OUT} -port_range {[3:0]} -port_is_pad {1}


# Add BIBUF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}



# Add CLKINT_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {CLKINT} -instance_name {CLKINT_0}



# Add COREJTAGDEBUG_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREJTAGDEBUG_C0} -instance_name {COREJTAGDEBUG_C0_0}



# Add CORERESET_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C0} -instance_name {CORERESET_PF_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:FF_US_RESTORE} -value {GND}



# Add CORETSE_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORETSE_C0} -instance_name {CORETSE_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_C0_0:MTXHWM}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_C0_0:TSM_CONTROL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_C0_0:TSM_TX_INTR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_C0_0:TSM_RX_INTR}



# Add MIV_ESS_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_C0} -instance_name {MIV_ESS_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_IN} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_INT}



# Add MIV_RV32_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_RESETN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:TIME_COUNT_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:JTAG_TDO_DR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_IRQ} -value {GND}



# Add PF_CCC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0}



# Add PF_INIT_MONITOR_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_INIT_MONITOR_C0} -instance_name {PF_INIT_MONITOR_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:AUTOCALIB_DONE}



# Add PF_RGMII_TO_GMII_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_RGMII_TO_GMII_C0} -instance_name {PF_RGMII_TO_GMII_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:D" "CORETSE_C0_0:MDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "CORETSE_C0_0:MDOEN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:PAD" "PHY_MDIO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "CORETSE_C0_0:MDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKINT_0:A" "CLK_50MHz" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKINT_0:Y" "PF_CCC_C0_0:REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TCK_0" "MIV_RV32_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDI_0" "MIV_RV32_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDO_0" "MIV_RV32_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TMS_0" "MIV_RV32_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TRSTN_0" "MIV_RV32_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:BANK_x_VDDI_STATUS" "CORERESET_PF_C0_0:BANK_y_VDDI_STATUS" "PF_INIT_MONITOR_C0_0:BANK_6_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:CLK" "CORETSE_C0_0:MRXCLK" "CORETSE_C0_0:MTXCLK" "CORETSE_C0_0:PCLK" "MIV_ESS_C0_0:PCLK" "MIV_RV32_C0_0:CLK" "PF_CCC_C0_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:EXT_RST_N" "USER_RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:FABRIC_RESET_N" "CORETSE_C0_0:PRESETN" "MIV_ESS_C0_0:PRESETN" "MIV_RV32_C0_0:RESETN" "PHY_RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:FPGA_POR_N" "PF_INIT_MONITOR_C0_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:INIT_DONE" "PF_INIT_MONITOR_C0_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:PLL_LOCK" "PF_CCC_C0_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:PLL_POWERDOWN_B" "PF_CCC_C0_0:PLL_POWERDOWN_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:COL" "PF_RGMII_TO_GMII_C0_0:GMII_COL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:CRS" "PF_RGMII_TO_GMII_C0_0:GMII_CRS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MDC" "PHY_MDC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MRXACPT" "CORETSE_C0_0:MTXACPT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MRXEOF" "CORETSE_C0_0:MTXEOF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MRXRDY" "CORETSE_C0_0:MTXRDY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MRXSOF" "CORETSE_C0_0:MTXSOF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:RXCLK" "CORETSE_C0_0:TXCLK" "PF_RGMII_TO_GMII_C0_0:GMII_RXCLK" "PF_RGMII_TO_GMII_C0_0:GMII_TXCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:RXDV" "PF_RGMII_TO_GMII_C0_0:GMII_RX_DV" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:RXER" "PF_RGMII_TO_GMII_C0_0:GMII_RX_ER" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:TXEN" "PF_RGMII_TO_GMII_C0_0:GMII_TX_EN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:TXER" "PF_RGMII_TO_GMII_C0_0:GMII_TX_ER" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "MIV_ESS_C0_0:GPIO_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_RX" "UART_RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_TX" "UART_TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_RGMII_TO_GMII_C0_0:RGMII_RXC" "RGMII_RXC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_RGMII_TO_GMII_C0_0:RGMII_RX_CTL" "RGMII_RX_CTL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_RGMII_TO_GMII_C0_0:RGMII_TXC" "RGMII_TXC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_RGMII_TO_GMII_C0_0:RGMII_TX_CTL" "RGMII_TX_CTL" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MRXBYTEVALID" "CORETSE_C0_0:MTXBYTEVALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:MRXDAT" "CORETSE_C0_0:MTXDAT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:RXD" "PF_RGMII_TO_GMII_C0_0:GMII_RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:TXD" "PF_RGMII_TO_GMII_C0_0:GMII_TXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_RGMII_TO_GMII_C0_0:RGMII_RXD" "RGMII_RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_RGMII_TO_GMII_C0_0:RGMII_TXD" "RGMII_TXD" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_C0_0:APBS" "MIV_ESS_C0_0:APB_3_mTARGET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:APB_0_mINITIATOR" "MIV_RV32_C0_0:APB_INITIATOR" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
