# Import source files
import_files -hdl_source {./src/hdl/addr_counter.v}
import_files -hdl_source {./src/hdl/DDR3_UI_DATA.v}
import_files -hdl_source {./src/hdl/Native_interface.v}
import_files -hdl_source {./src/hdl/throughput_cnt.v}


build_design_hierarchy 
# Create, configure and generate core components
source ./src/components/CCC_0.tcl
source ./src/components/DDR3_0.tcl
source ./src/components/reset_syn_1.tcl
source ./src/components/reset_syn_2.tcl
source ./src/components/INIT_Monitor.tcl
source ./src/components/PF_TPSRAM_C0.tcl
source ./src/components/PF_OSC_C0.tcl
# Generate SmartDesign Components

build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 
save_project
puts "Design generated successfully\n"
