///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
// © 2022 Microchip Technology Inc. and its subsidiaries
// All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------------
// Title : DDR3_UI_DATA.v
// Description : This module describes pattern the data has to be written in DDR3 .  <-- This module
//-------------------------------------------------------------------------

`timescale 1ns / 100ps


module DDR3_UI_DATA #
(
//defining parameter
    parameter integer  DATA_WIDTH  = 32 
)
(
    // Inputs
    RESETN,
    data_sel,
    CLK,
    read_req,
    dataout,
    restart
);

//--------------------------------------------------------------------
// Input/output
//--------------------------------------------------------------------
input 	RESETN;
input	CLK;
input [1:0] data_sel;
input	 read_req;
input    restart;
output [DATA_WIDTH*8-1:0]   dataout;

//--------------------------
//------------------------------------------
// Nets
//--------------------------------------------------------------------
reg [DATA_WIDTH*8-1:0]   seq_data;
reg [DATA_WIDTH*8-1:0]   walking1_data;
reg [DATA_WIDTH*8-1:0]   seq_data1_q;

// INCREMENTAL DATA
always @(posedge CLK or negedge RESETN)
begin
    if (!RESETN || restart) begin
        seq_data [DATA_WIDTH-1:0] <= {{(DATA_WIDTH-4){1'b0}},4'h1};
        seq_data [(DATA_WIDTH*2)-1:DATA_WIDTH]     <= 
		{{(DATA_WIDTH-4){1'b0}},4'h2}; 
        seq_data [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] <= 
		{{(DATA_WIDTH-4){1'b0}},4'h3}; 
        seq_data [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] <= 
		{{(DATA_WIDTH-4){1'b0}},4'h4}; 
        seq_data [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] <= 
		{{(DATA_WIDTH-4){1'b0}},4'h5}; 
        seq_data [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] <= 
		{{(DATA_WIDTH-4){1'b0}},4'h6}; 
        seq_data [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] <= 
		{{(DATA_WIDTH-4){1'b0}},4'h7};
        seq_data [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] <= 
		{{(DATA_WIDTH-4){1'b0}},4'h8}; 
    end
    else if (read_req == 1'b1&& data_sel == 2'b00) begin
        seq_data [DATA_WIDTH-1:0] <= seq_data [DATA_WIDTH-1:0]+ 8;
        seq_data [(DATA_WIDTH*2)-1:DATA_WIDTH]     <=
		seq_data [(DATA_WIDTH*2)-1:DATA_WIDTH]+ 8;
        seq_data [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] <= 
		seq_data [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] + 8;
        seq_data [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] <= 
		seq_data [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] + 8;
        seq_data [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] <= 
		seq_data [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] + 8;
        seq_data [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] <= 
		seq_data [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] + 8;
        seq_data [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] <= 
		seq_data [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] + 8;
        seq_data [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] <= 
		seq_data [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] + 8;
    end

end
// DEREMENTAL DATA
always @(posedge CLK or negedge RESETN)
begin
    if (!RESETN || restart) begin
        seq_data1_q [DATA_WIDTH-1:0] <= 32'hFFFFFFF8;
        seq_data1_q [(DATA_WIDTH*2)-1:DATA_WIDTH]     <= 
		{{(DATA_WIDTH-4){1'b1}},4'h9}; 
        seq_data1_q [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] <= 
		{{(DATA_WIDTH-4){1'b1}},4'hA}; 
        seq_data1_q [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] <= 
		{{(DATA_WIDTH-4){1'b1}},4'hB}; 
        seq_data1_q [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] <= 
		{{(DATA_WIDTH-4){1'b1}},4'hC}; 
        seq_data1_q [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] <= 
		{{(DATA_WIDTH-4){1'b1}},4'hD}; 
        seq_data1_q [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] <= 
		{{(DATA_WIDTH-4){1'b1}},4'hE};
        seq_data1_q [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] <= 
		{{(DATA_WIDTH-4){1'b1}},4'hF}; 
    end
    else if (read_req == 1'b1 && (data_sel == 2'b11)) begin        
        seq_data1_q [DATA_WIDTH-1:0] <= seq_data1_q [DATA_WIDTH-1:0]- 8;
        seq_data1_q [(DATA_WIDTH*2)-1:DATA_WIDTH]     <= 
		seq_data1_q [(DATA_WIDTH*2)-1:DATA_WIDTH]- 8;
        seq_data1_q [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] <= 
		seq_data1_q [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] - 8;
        seq_data1_q [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] <= 
		seq_data1_q [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] - 8;
        seq_data1_q [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] <= 
		seq_data1_q [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] - 8;
        seq_data1_q [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] <= 
		seq_data1_q [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] - 8;
        seq_data1_q [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] <= 
		seq_data1_q [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] - 8;
        seq_data1_q [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] <= 
		seq_data1_q [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] - 8;
    end

end

// WALKING-1 DATA
always @(posedge CLK or negedge RESETN)
begin
    if (!RESETN || restart) begin     
        walking1_data [DATA_WIDTH-1:0] <= 32'h00000001; 
        walking1_data [(DATA_WIDTH*2)-1:DATA_WIDTH]     <= 32'h00000002;
        walking1_data [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] <= 32'h00000004; 
        walking1_data [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] <= 32'h00000008; 
        walking1_data [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] <= 32'h00000010; 
        walking1_data [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] <= 32'h00000020; 
        walking1_data [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] <= 32'h00000040;
        walking1_data [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] <= 32'h00000080; 
    end
    else
       begin
            
        if ((read_req == 1'b1 && data_sel == 2'b01)|| (read_req == 1'b1 && data_sel == 2'b10)) begin
            walking1_data [DATA_WIDTH-1:0] <= {walking1_data [DATA_WIDTH-9:0] , (walking1_data [DATA_WIDTH-1: DATA_WIDTH-8])};
            walking1_data [(DATA_WIDTH*2)-1:DATA_WIDTH]     <= 
			{walking1_data [(DATA_WIDTH*2)-9:DATA_WIDTH] , walking1_data [(DATA_WIDTH*2)-1:(DATA_WIDTH*2)-8]};
            walking1_data [(DATA_WIDTH*3)-1:(DATA_WIDTH*2)] <= 
			{walking1_data [(DATA_WIDTH*3)-9:(DATA_WIDTH*2)] , walking1_data [(DATA_WIDTH*3)-1:(DATA_WIDTH*3)-8]};
            walking1_data [(DATA_WIDTH*4)-1:(DATA_WIDTH*3)] <= 
			{walking1_data [(DATA_WIDTH*4)-9:(DATA_WIDTH*3)] , walking1_data [(DATA_WIDTH*4)-1:(DATA_WIDTH*4)-8]};
            walking1_data [(DATA_WIDTH*5)-1:(DATA_WIDTH*4)] <= 
			{walking1_data [(DATA_WIDTH*5)-9:(DATA_WIDTH*4)] , walking1_data [(DATA_WIDTH*5)-1:(DATA_WIDTH*5)-8]};
            walking1_data [(DATA_WIDTH*6)-1:(DATA_WIDTH*5)] <= 
			{walking1_data [(DATA_WIDTH*6)-9:(DATA_WIDTH*5)] , walking1_data [(DATA_WIDTH*6)-1:(DATA_WIDTH*6)-8]};
            walking1_data [(DATA_WIDTH*7)-1:(DATA_WIDTH*6)] <= 
			{walking1_data [(DATA_WIDTH*7)-9:(DATA_WIDTH*6)] , walking1_data [(DATA_WIDTH*7)-1:(DATA_WIDTH*7)-8]};
            walking1_data [(DATA_WIDTH*8)-1:(DATA_WIDTH*7)] <= 
			{walking1_data [(DATA_WIDTH*8)-9:(DATA_WIDTH*7)] , walking1_data [(DATA_WIDTH*8)-1:(DATA_WIDTH*8)-8]};
        end
		
    end	
end


assign	dataout = (data_sel == 2'b00) ? seq_data: //incremental data pattern
		  (data_sel == 2'b01) ? walking1_data : //walking 1's data pattern 	
		  (data_sel == 2'b10) ? ~walking1_data : //walking 0's data pattern 
           	  seq_data1_q ; //decremental data pattern

endmodule
