///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
// © 2022 Microchip Technology Inc. and its subsidiaries
// All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------------
// Title : addr_counter.v
// Description : This module describes a counter which counts when the enable signal asserted and controls the write enable signal .  <-- This module
//-------------------------------------------------------------------------

module counter( CLK, RESETN, enable, wr_en,count );
input CLK, RESETN;
input   enable;
output  reg wr_en;
output  [8:0]   count;

reg [9:0]   cnt;
//This block describes the counter and write enable for further modules
always @(posedge CLK or negedge RESETN)
begin
    if (!RESETN) begin
        cnt <= 9'b0;
        wr_en <= 1'b1; end
    else if(enable == 1) begin
        cnt <= cnt + 1;
        if( cnt >= 10'h3ff)
          begin
            cnt <= cnt;
            wr_en <= 1'b0; 
          end
        else
          wr_en<= 1'b1;
    end
end
assign count = cnt;

endmodule