///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
// © 2022 Microchip Technology Inc. and its subsidiaries
// All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------------
// Title : throughput_cnt.v
// Description : This module counts the number of read ,write cycles and detects the burst operation .  <-- This module
//-------------------------------------------------------------------------

//`timescale <time_units> / <precision>

module last_burst_calc #
(
//parameters
    parameter integer  MULTIBURST_MAX           = 32  //The maximum number of bursts in a multi-burst operation
)
( CLK, RESETN, l_d_req, l_d_req_last, l_r_valid, l_r_valid_last,
last_w_burst, last_r_burst);
input CLK, RESETN, l_d_req, l_d_req_last, l_r_valid, l_r_valid_last;
output reg last_w_burst;
output reg last_r_burst;
reg l_d_req_last_q;
reg l_r_valid_last_q ;
reg [7:0] mb_w_cnt;
reg [7:0] mb_r_cnt;


//assigning reg
always @(posedge CLK or negedge RESETN)
begin
    if (!RESETN) begin
        l_d_req_last_q <= 0;
        l_r_valid_last_q <= 0;
        mb_w_cnt <= 8'b1;
        mb_r_cnt <= 8'b1;
    end
    else begin
        l_d_req_last_q <= l_d_req_last;
        l_r_valid_last_q <= l_r_valid_last;
        if (l_d_req_last_q == 1'b1)
            mb_w_cnt <= mb_w_cnt +1;
        if (l_r_valid_last_q == 1'b1)
            mb_r_cnt <= mb_r_cnt +1;
end
end

// counts the write cycles
always @(posedge CLK or negedge RESETN)
begin
    if (!RESETN) begin
        last_w_burst <= 1'b1;
        last_r_burst <= 1'b1;
    end
else begin
    if (mb_w_cnt == MULTIBURST_MAX)
        last_w_burst <= 1'b1;
    else
        last_w_burst <= 1'b0;
    if (mb_r_cnt == MULTIBURST_MAX)
        last_r_burst <= 1'b1;
    else
        last_r_burst <= 1'b0;
end
end



endmodule

