# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {resetn} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRLR_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD2} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD3} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_rd_wrt_err} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {R_ADDR} -port_direction {IN} -port_range {[8:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {data_pattern} -port_direction {IN} -port_range {[1:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {R_DATA} -port_direction {OUT} -port_range {[255:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1}

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add CCC_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_0} -instance_name {CCC_0_0}



# Add control_logic instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DDR3_Native_interface} -hdl_file {hdl\Native_interface.v} -instance_name {control_logic}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {control_logic:MULTIBURST_MAX} -value {00010000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {control_logic:mburst_length} -value {10000000000}



# Add counter_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {counter} -hdl_file {hdl\addr_counter.v} -instance_name {counter_0}



# Add DDR3_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR3_0} -instance_name {DDR3_0_0}



# Add INIT_Monitor_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_Monitor} -instance_name {INIT_Monitor_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:AUTOCALIB_DONE}



# Add PF_OSC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_C0} -instance_name {PF_OSC_C0_0}



# Add PF_TPSRAM_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TPSRAM_C0} -instance_name {PF_TPSRAM_C0_0}



# Add reset_syn_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_syn_1} -instance_name {reset_syn_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_1:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_1:FF_US_RESTORE} -value {GND}



# Add reset_syn_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_syn_2} -instance_name {reset_syn_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_2:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_2:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {reset_syn_2:PLL_POWERDOWN_B}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "DDR3_0_0:l_r_valid_p0" "control_logic:l_r_valid" "counter_0:enable" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "counter_0:wr_en" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_TPSRAM_C0_0:W_EN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "DDR3_0_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT0_FABCLK_0" "DDR3_0_0:PLL_REF_CLK" "reset_syn_1:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:PLL_LOCK_0" "reset_syn_1:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:PLL_POWERDOWN_N_0" "reset_syn_1:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:REF_CLK_0" "PF_OSC_C0_0:RCOSC_160MHZ_GL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "DDR3_0_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "DDR3_0_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "DDR3_0_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "DDR3_0_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CTRLR_READY" "DDR3_0_0:CTRLR_READY" "control_logic:ctrl_ready" "reset_syn_2:EXT_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:ODT" "ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:PLL_LOCK" "reset_syn_2:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:SHIELD2" "SHIELD2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:SHIELD3" "SHIELD3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:SYS_CLK" "PF_TPSRAM_C0_0:CLK" "control_logic:CLK" "counter_0:CLK" "reset_syn_2:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:SYS_RESET_N" "reset_syn_1:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_auto_pch_p0" "control_logic:l_auto_pch" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_busy_p0" "control_logic:l_busy" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_d_req_last_p0" "control_logic:l_d_req_last" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_d_req_p0" "control_logic:l_d_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_r_req_p0" "control_logic:l_r_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_r_valid_last_p0" "control_logic:l_r_valid_last" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_w_req_p0" "control_logic:l_w_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:BANK_0_VDDI_STATUS" "reset_syn_1:BANK_x_VDDI_STATUS" "reset_syn_2:BANK_x_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:BANK_1_CALIB_STATUS" "reset_syn_1:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:BANK_6_VDDI_STATUS" "reset_syn_1:BANK_y_VDDI_STATUS" "reset_syn_2:BANK_y_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:DEVICE_INIT_DONE" "reset_syn_2:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:FABRIC_POR_N" "reset_syn_1:FPGA_POR_N" "reset_syn_2:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"control_logic:RESETN" "counter_0:RESETN" "reset_syn_2:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"control_logic:err_flg" "ddr_rd_wrt_err" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_syn_1:EXT_RST_N" "resetn" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "DDR3_0_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "DDR3_0_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:DM" "DM" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:DQ" "DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:DQS" "DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:DQS_N" "DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_addr_p0" "control_logic:l_addr" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_b_size_p0" "control_logic:l_b_size" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_datain_p0" "control_logic:l_datain" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_dataout" "PF_TPSRAM_C0_0:W_DATA" "control_logic:l_dataout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR3_0_0:l_dm_in_p0" "control_logic:l_dm_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TPSRAM_C0_0:R_ADDR" "R_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TPSRAM_C0_0:R_DATA" "R_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TPSRAM_C0_0:W_ADDR" "counter_0:count" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"control_logic:data_pattern" "data_pattern" }


# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
