# Creating SmartDesign "RTG4_DDR3"
set sd_name {RTG4_DDR3}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_BREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_RREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_WLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_WVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_BASE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CORE_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_0_IN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_1_IN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_CLK_50MHz} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_PRESET_N} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_BVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_RLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_RVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_WREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CLK_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CLK} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_0_OUT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_1_OUT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARLEN} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARLOCK} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_ARSIZE} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWLEN} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWLOCK} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_AWSIZE} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_WDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_WID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_WSTRB} -port_direction {IN} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_BID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_BRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_RDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_RID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_SLAVE_AXI_S_RRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_ADDR} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DM_RDQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1}

# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI_SLAVE} -port_bif_vlnv {AMBA:AMBA3:AXI:r1p0_5} -port_bif_role {slave} -port_bif_mapping {\
"AWID:AXI_SLAVE_AXI_S_AWID" \
"AWADDR:AXI_SLAVE_AXI_S_AWADDR" \
"AWLEN:AXI_SLAVE_AXI_S_AWLEN" \
"AWSIZE:AXI_SLAVE_AXI_S_AWSIZE" \
"AWBURST:AXI_SLAVE_AXI_S_AWBURST" \
"AWLOCK:AXI_SLAVE_AXI_S_AWLOCK" \
"AWVALID:AXI_SLAVE_AXI_S_AWVALID" \
"AWREADY:AXI_SLAVE_AXI_S_AWREADY" \
"WID:AXI_SLAVE_AXI_S_WID" \
"WDATA:AXI_SLAVE_AXI_S_WDATA" \
"WSTRB:AXI_SLAVE_AXI_S_WSTRB" \
"WLAST:AXI_SLAVE_AXI_S_WLAST" \
"WVALID:AXI_SLAVE_AXI_S_WVALID" \
"WREADY:AXI_SLAVE_AXI_S_WREADY" \
"BID:AXI_SLAVE_AXI_S_BID" \
"BRESP:AXI_SLAVE_AXI_S_BRESP" \
"BVALID:AXI_SLAVE_AXI_S_BVALID" \
"BREADY:AXI_SLAVE_AXI_S_BREADY" \
"ARID:AXI_SLAVE_AXI_S_ARID" \
"ARADDR:AXI_SLAVE_AXI_S_ARADDR" \
"ARLEN:AXI_SLAVE_AXI_S_ARLEN" \
"ARSIZE:AXI_SLAVE_AXI_S_ARSIZE" \
"ARBURST:AXI_SLAVE_AXI_S_ARBURST" \
"ARLOCK:AXI_SLAVE_AXI_S_ARLOCK" \
"ARVALID:AXI_SLAVE_AXI_S_ARVALID" \
"ARREADY:AXI_SLAVE_AXI_S_ARREADY" \
"RID:AXI_SLAVE_AXI_S_RID" \
"RDATA:AXI_SLAVE_AXI_S_RDATA" \
"RRESP:AXI_SLAVE_AXI_S_RRESP" \
"RLAST:AXI_SLAVE_AXI_S_RLAST" \
"RVALID:AXI_SLAVE_AXI_S_RVALID" \
"RREADY:AXI_SLAVE_AXI_S_RREADY" } 

# Add COREABC_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREABC_C1} -instance_name {COREABC_C1_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREABC_C1_0:PRESETN}



# Add CoreAPB3_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C1} -instance_name {CoreAPB3_C1_0}



# Add RTG4FDDRC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FDDRC_C0} -instance_name {RTG4FDDRC_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_BASE" "RTG4FDDRC_C0_0:CLK_BASE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C1_0:IO_IN" "RTG4FDDRC_C0_0:FPLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C1_0:IO_OUT" "INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C1_0:NSYSRESET" "INIT_PRESET_N" "RTG4FDDRC_C0_0:APB_S_PRESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C1_0:PCLK" "INIT_CLK_50MHz" "RTG4FDDRC_C0_0:APB_S_PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_RESET_N" "RTG4FDDRC_C0_0:CORE_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CAS_N" "RTG4FDDRC_C0_0:FDDR_CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CKE" "RTG4FDDRC_C0_0:FDDR_CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CLK" "RTG4FDDRC_C0_0:FDDR_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CLK_N" "RTG4FDDRC_C0_0:FDDR_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CS_N" "RTG4FDDRC_C0_0:FDDR_CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_0_IN" "RTG4FDDRC_C0_0:FDDR_DQS_TMATCH_0_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_0_OUT" "RTG4FDDRC_C0_0:FDDR_DQS_TMATCH_0_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_1_IN" "RTG4FDDRC_C0_0:FDDR_DQS_TMATCH_1_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_1_OUT" "RTG4FDDRC_C0_0:FDDR_DQS_TMATCH_1_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_ODT" "RTG4FDDRC_C0_0:FDDR_ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_RAS_N" "RTG4FDDRC_C0_0:FDDR_RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_RESET_N" "RTG4FDDRC_C0_0:FDDR_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_WE_N" "RTG4FDDRC_C0_0:FDDR_WE_N" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_ADDR" "RTG4FDDRC_C0_0:FDDR_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_BA" "RTG4FDDRC_C0_0:FDDR_BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DM_RDQS" "RTG4FDDRC_C0_0:FDDR_DM_RDQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQ" "RTG4FDDRC_C0_0:FDDR_DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS" "RTG4FDDRC_C0_0:FDDR_DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_N" "RTG4FDDRC_C0_0:FDDR_DQS_N" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_SLAVE" "RTG4FDDRC_C0_0:AXI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C1_0:APB3Initiator" "CoreAPB3_C1_0:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C1_0:APBmslave0" "RTG4FDDRC_C0_0:APB_SLAVE" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "RTG4_DDR3"
generate_component -component_name ${sd_name}
