# Creating SmartDesign "BAR1_LSRAM"
set sd_name {BAR1_LSRAM}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WEN} -port_direction {IN}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {RADDR} -port_direction {IN} -port_range {[8:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WADDR} -port_direction {IN} -port_range {[9:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WD} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {RD} -port_direction {OUT} -port_range {[63:0]}


# Add RTG4TPSRAM_0 instance
sd_instantiate_core -sd_name ${sd_name} -core_vlnv Actel:SgCore:RTG4TPSRAM:$RTG4TPSRAMver -instance_name {RTG4TPSRAM_0}
# Exporting Parameters of instance RTG4TPSRAM_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {RTG4TPSRAM_0} -params {\
"A_DOUT_EN_PN:RD_EN" \
"A_DOUT_EN_POLARITY:2" \
"A_DOUT_SRST_PN:RD_SRST_N" \
"A_DOUT_SRST_POLARITY:2" \
"A_WBYTE_EN_PN:A_WBYTE_EN" \
"ARST_N_POLARITY:2" \
"BYTE_ENABLE_WIDTH:0" \
"BYTEENABLES:0" \
"CASCADE:0" \
"CLK_EDGE:RISE" \
"CLKS:1" \
"CLOCK_PN:CLK" \
"DATA_IN_PN:WD" \
"DATA_OUT_PN:RD" \
"ECC:0" \
"FAMILY:25" \
"IMPORT_FILE:" \
"INIT_RAM:F" \
"LPMTYPE:LPM_RAM" \
"PTYPE:1" \
"RADDRESS_PN:RADDR" \
"RCLK_EDGE:RISE" \
"RCLOCK_PN:RCLK" \
"RDEPTH:512" \
"RE_PN:REN" \
"RE_POLARITY:2" \
"RESET_PN:ARST_N" \
"RPMODE:0" \
"RWIDTH:64" \
"SD_EXPORT_HIDDEN_PORTS:false" \
"WADDRESS_PN:WADDR" \
"WCLK_EDGE:RISE" \
"WCLOCK_PN:WCLK" \
"WDEPTH:1024" \
"WE_PN:WEN" \
"WE_POLARITY:1" \
"WWIDTH:32" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {RTG4TPSRAM_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK" "RTG4TPSRAM_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4TPSRAM_0:WEN" "WEN" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"RADDR" "RTG4TPSRAM_0:RADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RD" "RTG4TPSRAM_0:RD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4TPSRAM_0:WADDR" "WADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4TPSRAM_0:WD" "WD" }


# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "BAR1_LSRAM"
generate_component -component_name ${sd_name}
