# Exporting Component Description of RTG4FDDRC_C0 to TCL
# Family: RTG4
# Part Number: RT4G150-1CG1657
# Create and Configure the core component RTG4FDDRC_C0
create_and_configure_core -core_vlnv Actel:SgCore:RTG4FDDRC:$RTG4FDDRCver -component_name {RTG4FDDRC_C0} -params {\
"DDR_FIC_ERR_INT_ENABLE_CR:0x0"  \
"DDR_FIC_HPB_ERR_ADDR_1_SR:0x0"  \
"DDR_FIC_HPB_ERR_ADDR_2_SR:0x0"  \
"DDR_FIC_HPD_SW_RW_EN_CR:0x0"  \
"DDR_FIC_HPD_SW_RW_INVAL_CR:0x0"  \
"DDR_FIC_HPD_SW_WRB_EMPTY_SR:0x0"  \
"DDR_FIC_LOCK_TIMEOUT_EN_CR:0x0"  \
"DDR_FIC_LOCK_TIMEOUTVAL_1_CR:0x0"  \
"DDR_FIC_LOCK_TIMEOUTVAL_2_CR:0x0"  \
"DDR_FIC_NB_ADDR_CR:0x0"  \
"DDR_FIC_NBRWB_SIZE_CR:0x0"  \
"DDR_FIC_NUM_AHB_MASTERS_CR:0x0"  \
"DDR_FIC_RDWR_ERR_SR:0x0"  \
"DDR_FIC_SW_ERR_ADDR_1_SR:0x0"  \
"DDR_FIC_SW_ERR_ADDR_2_SR:0x0"  \
"DDR_FIC_SW_HPB_LOCKOUT_SR:0x0"  \
"DDR_FIC_SW_HPD_WERR_SR:0x0"  \
"DDR_FIC_SW_WR_ERCLR_CR:0x0"  \
"DDR_FIC_WB_TIMEOUT_CR:0x0"  \
"DDRC_ADDR_MAP_BANK_CR:0xAAA"  \
"DDRC_ADDR_MAP_COL_1_CR:0x3333"  \
"DDRC_ADDR_MAP_COL_2_CR:0x3FFF"  \
"DDRC_ADDR_MAP_COL_3_CR:0x3300"  \
"DDRC_ADDR_MAP_ROW_1_CR:0x9999"  \
"DDRC_ADDR_MAP_ROW_2_CR:0x999"  \
"DDRC_AXI_FABRIC_PRI_ID_CR:0x0"  \
"DDRC_CKE_RSTN_CYCLES_1_CR:0x4242"  \
"DDRC_CKE_RSTN_CYCLES_2_CR:0x8"  \
"DDRC_DEBUG_CR:0x3300"  \
"DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR:0x309"  \
"DDRC_DFI_MAX_CTRLUPD_TIMING_CR:0x40"  \
"DDRC_DFI_MIN_CTRLUPD_TIMING_CR:0x3"  \
"DDRC_DFI_RD_LVL_CONTROL_1_CR:0x0"  \
"DDRC_DFI_RD_LVL_CONTROL_2_CR:0x0"  \
"DDRC_DFI_RDDATA_EN_CR:0x5"  \
"DDRC_DFI_WR_LVL_CONTROL_1_CR:0x0"  \
"DDRC_DFI_WR_LVL_CONTROL_2_CR:0x0"  \
"DDRC_DOUBLE_ERR_CNT_SR:0x0"  \
"DDRC_DRAM_BANK_ACT_TIMING_CR:0x19c7"  \
"DDRC_DRAM_BANK_TIMING_PARAM_CR:0xce0"  \
"DDRC_DRAM_MR_TIMING_PARAM_CR:0x64"  \
"DDRC_DRAM_RAS_TIMING_CR:0x10f"  \
"DDRC_DRAM_RD_WR_LATENCY_CR:0x86"  \
"DDRC_DRAM_RD_WR_PRE_CR:0x235"  \
"DDRC_DRAM_RD_WR_TRNARND_TIME_CR:0x178"  \
"DDRC_DRAM_T_PD_CR:0x33"  \
"DDRC_DYN_DEBUG_CR:0x0"  \
"DDRC_DYN_POWERDOWN_CR:0x2"  \
"DDRC_DYN_REFRESH_1_CR:0x2788"  \
"DDRC_DYN_REFRESH_2_CR:0x30f"  \
"DDRC_DYN_SOFT_RESET_ALIAS_CR:0x1"  \
"DDRC_DYN_SOFT_RESET_CR:0x0"  \
"DDRC_ECC_DATA_MASK_CR:0x0"  \
"DDRC_ECC_INT_CLR_REG:0x0"  \
"DDRC_ECC_INT_SR:0x0"  \
"DDRC_ECC_OUTPUT_DATA_SR:0x0"  \
"DDRC_HPR_QUEUE_PARAM_1_CR:0x80F8"  \
"DDRC_HPR_QUEUE_PARAM_2_CR:0x7"  \
"DDRC_INIT_1_CR:0x1"  \
"DDRC_INIT_EMR2_CR:0x0"  \
"DDRC_INIT_EMR3_CR:0x0"  \
"DDRC_INIT_EMR_CR:0x44"  \
"DDRC_INIT_MR_CR:0x520"  \
"DDRC_LCB_MASK_1_SR:0x0"  \
"DDRC_LCB_MASK_2_SR:0x0"  \
"DDRC_LCB_MASK_3_SR:0x0"  \
"DDRC_LCB_MASK_4_SR:0x0"  \
"DDRC_LCB_NUMBER_SR:0x0"  \
"DDRC_LCE_ADDRESS_1_SR:0x0"  \
"DDRC_LCE_ADDRESS_2_SR:0x0"  \
"DDRC_LCE_SYNDROME_1_SR:0x0"  \
"DDRC_LCE_SYNDROME_2_SR:0x0"  \
"DDRC_LCE_SYNDROME_3_SR:0x0"  \
"DDRC_LCE_SYNDROME_4_SR:0x0"  \
"DDRC_LCE_SYNDROME_5_SR:0x0"  \
"DDRC_LPR_QUEUE_PARAM_1_CR:0x80F8"  \
"DDRC_LPR_QUEUE_PARAM_2_CR:0x7"  \
"DDRC_LUE_ADDRESS_1_SR:0x0"  \
"DDRC_LUE_ADDRESS_2_SR:0x0"  \
"DDRC_LUE_SYNDROME_1_SR:0x0"  \
"DDRC_LUE_SYNDROME_2_SR:0x0"  \
"DDRC_LUE_SYNDROME_3_SR:0x0"  \
"DDRC_LUE_SYNDROME_4_SR:0x0"  \
"DDRC_LUE_SYNDROME_5_SR:0x0"  \
"DDRC_MODE_CR:0x100"  \
"DDRC_MODE_REG_DATA_CR:0x0"  \
"DDRC_MODE_REG_RD_WR_CR:0x0"  \
"DDRC_ODT_PARAM_1_CR:0x14"  \
"DDRC_ODT_PARAM_2_CR:0x18"  \
"DDRC_PERF_PARAM_1_CR:0x4083"  \
"DDRC_PERF_PARAM_2_CR:0x0"  \
"DDRC_PERF_PARAM_3_CR:0x0"  \
"DDRC_PWR_SAVE_1_CR:0x406"  \
"DDRC_PWR_SAVE_2_CR:0x0"  \
"DDRC_RESERVED0:0x0"  \
"DDRC_SINGLE_ERR_CNT_SR:0x0"  \
"DDRC_SR:0x0"  \
"DDRC_WR_QUEUE_PARAM_CR:0x200"  \
"DDRC_ZQ_LONG_TIME_CR:0x200"  \
"DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR:0x12"  \
"DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR:0x2"  \
"DDRC_ZQ_SHORT_TIME_CR:0x40"  \
"DM_WIDTH:3"  \
"DQ_ECC_WIDTH:3"  \
"DQ_WIDTH:31"  \
"DQS_WIDTH:3"  \
"ENABLE_INTERRUPTS:false"  \
"FAB_PLL_LOCK_USED:false"  \
"LOCATION_ID:FDDR_W"  \
"MEMORY_ECC:NO"  \
"MEMORY_TYPE:DDR3"  \
"MEMORY_WIDTH:32"  \
"MODE:MODE_AXI64"  \
"NUMBER_OF_BANK_BITS:3"  \
"NUMBER_OF_COLUMN_BITS:10"  \
"NUMBER_OF_ROW_BITS:16"  \
"PHY_BIST_ERROR_1_SR:0x0"  \
"PHY_BIST_ERROR_2_SR:0x0"  \
"PHY_BIST_ERROR_3_SR:0x0"  \
"PHY_BIST_TEST_SHIFT_PATTERN_1_CR:0x0"  \
"PHY_BIST_TEST_SHIFT_PATTERN_2_CR:0x0"  \
"PHY_BIST_TEST_SHIFT_PATTERN_3_CR:0x0"  \
"PHY_BOARD_LOOPBACK_CR:0x0"  \
"PHY_CTRL_OF_OUTPUT_DELAY_SR:0x0"  \
"PHY_CTRL_OUTPUT_FILTER_SR:0x0"  \
"PHY_CTRL_SLAVE_DELAY_CR:0x0"  \
"PHY_CTRL_SLAVE_DLL_VAL_SR:0x0"  \
"PHY_CTRL_SLAVE_FORCE_CR:0x0"  \
"PHY_CTRL_SLAVE_RATIO_CR:0x80"  \
"PHY_DATA_SLICE_IN_USE_CR:0xF"  \
"PHY_DIS_CALIB_RST_CR:0x0"  \
"PHY_DLL_LOCK_AND_SLAVE_VAL_SR:0x0"  \
"PHY_DLL_LOCK_DIFF_CR:0xB"  \
"PHY_DLL_SLAVE_VALUE_1_SR:0x0"  \
"PHY_DLL_SLAVE_VALUE_2_SR:0x0"  \
"PHY_DQ_OFFSET_1_CR:0x0"  \
"PHY_DQ_OFFSET_2_CR:0x0"  \
"PHY_DQ_OFFSET_3_CR:0x0"  \
"PHY_DYN_BIST_TEST_CR:0x0"  \
"PHY_DYN_BIST_TEST_ERRCLR_1_CR:0x0"  \
"PHY_DYN_BIST_TEST_ERRCLR_2_CR:0x0"  \
"PHY_DYN_BIST_TEST_ERRCLR_3_CR:0x0"  \
"PHY_DYN_CONFIG_CR:0x0"  \
"PHY_DYN_RESET_CR:0x1"  \
"PHY_FIFO_1_SR:0x0"  \
"PHY_FIFO_2_SR:0x0"  \
"PHY_FIFO_3_SR:0x0"  \
"PHY_FIFO_4_SR:0x0"  \
"PHY_FIFO_WE_IN_DELAY_1_CR:0x0"  \
"PHY_FIFO_WE_IN_DELAY_2_CR:0x0"  \
"PHY_FIFO_WE_IN_DELAY_3_CR:0x0"  \
"PHY_FIFO_WE_IN_FORCE_CR:0x0"  \
"PHY_FIFO_WE_SLAVE_DLL_VAL_1_SR:0x0"  \
"PHY_FIFO_WE_SLAVE_DLL_VAL_2_SR:0x0"  \
"PHY_FIFO_WE_SLAVE_DLL_VAL_3_SR:0x0"  \
"PHY_FIFO_WE_SLAVE_RATIO_1_CR:0x80"  \
"PHY_FIFO_WE_SLAVE_RATIO_2_CR:0x2004"  \
"PHY_FIFO_WE_SLAVE_RATIO_3_CR:0x100"  \
"PHY_FIFO_WE_SLAVE_RATIO_4_CR:0x8"  \
"PHY_GATELVL_INIT_MODE_CR:0x0"  \
"PHY_GATELVL_INIT_RATIO_1_CR:0x0"  \
"PHY_GATELVL_INIT_RATIO_2_CR:0x0"  \
"PHY_GATELVL_INIT_RATIO_3_CR:0x0"  \
"PHY_GATELVL_INIT_RATIO_4_CR:0x0"  \
"PHY_INVERT_CLKOUT_CR:0x0"  \
"PHY_LEVELLING_FAILURE_SR:0x0"  \
"PHY_LOCAL_ODT_CR:0x1"  \
"PHY_LOOPBACK_TEST_CR:0x0"  \
"PHY_LVL_NUM_OF_DQ0_CR:0x0"  \
"PHY_MASTER_DLL_SR:0x0"  \
"PHY_RD_DQS_SLAVE_DELAY_1_CR:0x0"  \
"PHY_RD_DQS_SLAVE_DELAY_2_CR:0x0"  \
"PHY_RD_DQS_SLAVE_DELAY_3_CR:0x0"  \
"PHY_RD_DQS_SLAVE_DLL_VAL_1_SR:0x0"  \
"PHY_RD_DQS_SLAVE_DLL_VAL_2_SR:0x0"  \
"PHY_RD_DQS_SLAVE_DLL_VAL_3_SR:0x0"  \
"PHY_RD_DQS_SLAVE_FORCE_CR:0x0"  \
"PHY_RD_DQS_SLAVE_RATIO_1_CR:0x4050"  \
"PHY_RD_DQS_SLAVE_RATIO_2_CR:0x501"  \
"PHY_RD_DQS_SLAVE_RATIO_3_CR:0x5014"  \
"PHY_RD_DQS_SLAVE_RATIO_4_CR:0x0"  \
"PHY_RD_WR_GATE_LVL_CR:0x0"  \
"PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR:0x0"  \
"PHY_RDC_WE_TO_RE_DELAY_CR:0x3"  \
"PHY_RDLVL_DQS_RATIO_1_SR:0x0"  \
"PHY_RDLVL_DQS_RATIO_2_SR:0x0"  \
"PHY_RDLVL_DQS_RATIO_3_SR:0x0"  \
"PHY_RDLVL_DQS_RATIO_4_SR:0x0"  \
"PHY_STATUS_OF_IN_DELAY_VAL_1_SR:0x0"  \
"PHY_STATUS_OF_IN_DELAY_VAL_2_SR:0x0"  \
"PHY_STATUS_OF_OUT_DELAY_VAL_1_SR:0x0"  \
"PHY_STATUS_OF_OUT_DELAY_VAL_2_SR:0x0"  \
"PHY_USE_FIXED_RE_CR:0x1"  \
"PHY_USE_LVL_TRNG_LEVEL_CR:0x0"  \
"PHY_USE_RANK0_DELAYS_CR:0x1"  \
"PHY_WR_DATA_SLAVE_DELAY_1_CR:0x0"  \
"PHY_WR_DATA_SLAVE_DELAY_2_CR:0x0"  \
"PHY_WR_DATA_SLAVE_DELAY_3_CR:0x0"  \
"PHY_WR_DATA_SLAVE_DLL_VAL_1_SR:0x0"  \
"PHY_WR_DATA_SLAVE_DLL_VAL_2_SR:0x0"  \
"PHY_WR_DATA_SLAVE_DLL_VAL_3_SR:0x0"  \
"PHY_WR_DATA_SLAVE_FORCE_CR:0x0"  \
"PHY_WR_DATA_SLAVE_RATIO_1_CR:0x50"  \
"PHY_WR_DATA_SLAVE_RATIO_2_CR:0x501"  \
"PHY_WR_DATA_SLAVE_RATIO_3_CR:0x5010"  \
"PHY_WR_DATA_SLAVE_RATIO_4_CR:0x0"  \
"PHY_WR_DQS_SLAVE_DELAY_1_CR:0x0"  \
"PHY_WR_DQS_SLAVE_DELAY_2_CR:0x0"  \
"PHY_WR_DQS_SLAVE_DELAY_3_CR:0x0"  \
"PHY_WR_DQS_SLAVE_DLL_VAL_1_SR:0x0"  \
"PHY_WR_DQS_SLAVE_DLL_VAL_2_SR:0x0"  \
"PHY_WR_DQS_SLAVE_DLL_VAL_3_SR:0x0"  \
"PHY_WR_DQS_SLAVE_FORCE_CR:0x0"  \
"PHY_WR_DQS_SLAVE_RATIO_1_CR:0x0"  \
"PHY_WR_DQS_SLAVE_RATIO_2_CR:0x0"  \
"PHY_WR_DQS_SLAVE_RATIO_3_CR:0x0"  \
"PHY_WR_DQS_SLAVE_RATIO_4_CR:0x0"  \
"PHY_WR_RD_RL_CR:0x43"  \
"PHY_WRLVL_DQ_RATIO_1_SR:0x0"  \
"PHY_WRLVL_DQ_RATIO_2_SR:0x0"  \
"PHY_WRLVL_DQ_RATIO_3_SR:0x0"  \
"PHY_WRLVL_DQ_RATIO_4_SR:0x0"  \
"PHY_WRLVL_DQS_RATIO_1_SR:0x0"  \
"PHY_WRLVL_DQS_RATIO_2_SR:0x0"  \
"PHY_WRLVL_DQS_RATIO_3_SR:0x0"  \
"PHY_WRLVL_DQS_RATIO_4_SR:0x0"  \
"PHY_WRLVL_INIT_MODE_CR:0x0"  \
"PHY_WRLVL_INIT_RATIO_1_CR:0x0"  \
"PHY_WRLVL_INIT_RATIO_2_CR:0x0"  \
"PHY_WRLVL_INIT_RATIO_3_CR:0x0"  \
"PHY_WRLVL_INIT_RATIO_4_CR:0x0"  \
"PLL_CLK_FDDR_FREQ:320"  \
"PLL_CLK_FIC64_DIV:4"  \
"PLL_LOCK_DELAY:1024"  \
"PLL_LOCK_WINDOW:3000"  \
"PLL_SUPPLY_VOLTAGE:25_V"   }
# Exporting Component Description of RTG4FDDRC_C0 to TCL done
