# Import source files
import_files -hdl_source {./src/hdl/AXI_MASTER_TO_SLAVE.v}
import_files -hdl_source {./src/hdl/Controller.v}
import_files -hdl_source {./src/hdl/DDR_AXI_IF.v}
import_files -hdl_source {./src/hdl/Debounce.v}
import_files -hdl_source {./src/hdl/HOTRESET_DETECT.v}
import_files -hdl_source {./src/hdl/PCIe_AXI_IF.v}
import_files -hdl_source {./src/hdl/reset_synchronizer.v}


build_design_hierarchy 
# Create, configure and generate core components
source ./src/components/RTG4FCCCECALIB_C0.tcl
source ./src/components/DDR_AXI_IF.tcl
source ./src/components/PCIe_AXI_IF.tcl
source ./src/components/Controller.tcl
source ./src/components/AXI_MASTER_TO_SLAVE.tcl
source ./src/components/BAR1_LSRAM.tcl
source ./src/components/LSRAM.tcl
source ./src/components/COREABC_C0.tcl
source ./src/components/COREABC_C1.tcl
source ./src/components/CoreAPB3_C0.tcl
source ./src/components/CoreAPB3_C1.tcl
source ./src/components/CoreGPIO_C0.tcl
source ./src/components/PCIE_SERDES_IF_C0.tcl
source ./src/components/RTG4FCCC_C0.tcl
source ./src/components/RTG4FDDRC_C0.tcl

# Generate SmartDesign Components
build_design_hierarchy 
source ./src/components/pcie_init.tcl
build_design_hierarchy 
source ./src/components/RTG4_DDR3.tcl
build_design_hierarchy 
source ./src/components/DMA_Controller.tcl
build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
