# Exporting Component Description of COREABC_C0 to TCL
# Family: RTG4
# Part Number: RT4G150-1CG1657
# Create and Configure the core component COREABC_C0
create_and_configure_core -core_vlnv Actel:DirectCore:COREABC:$COREABCver -component_name {COREABC_C0} -params {\
"ABCCODE:// --------------------------------------
// CoreABC SERDES Initialization Sequence
// --------------------------------------

// Allow time for the APB interface to be ready after reset
NOP
NOP
NOP

// SYSTEM_CONFIG_PHY_MODE_1
APBWRT DAT 0 0x2028 0x11C
// LANE0_RXIDLE_MAX_ERRCNT_THR
APBWRT DAT 0 0x1008 0xF8
// SYSTEM_CONFIG_PHY_MODE_1
APBWRT DAT 0 0x2028 0xF1C
// SYSTEM_SERDES_APB_SOFT_RSTN_SEL
APBWRT DAT 0 0x206c 0x0

//disable low power capability
APBWRT DAT 0 0x2018 0x80

// De-assert PHY_RESET_N
IOWRT DAT 0x2

// actual_ref_div  = 2
// actual_fb_div   = 2
// actual_vco_div  = 8
// actual_vco_freq = 640
// highvco_ref_div = 2
// highvco_fb_div  = 3
// highvco_vco_div = 8
// highvco_vco_freq= 960

// PLL_CONFIG_LOW for high vco configuration
APBWRT DAT 0 0x2000 0x30081

// Assert SPLL POWERDOWN (PLL_CONFIG_HIGH:PLL_PD=1)
APBWRT DAT 0 0x2004 0xd02e3

// SPLL PLL_PD pulse time
// Using 2us settling time @ 50MHz
//   - #cycles = 2*1000/20=100
//   - loop value = #cycles / 6 (2 instructions)
LOADZ 0x10
$WaitpdSettling
DECZ
JUMP IFNOT ZZERO $WaitpdSettling

// De-assert SPLL POWERDOWN (PLL_CONFIG_HIGH:PLL_PD=0)
APBWRT DAT 0 0x2004 0xc02e3

// SPLL high vco settling time
// Using 100us settling time @ 50MHz
//   - #cycles = 100*1000/20=5000
//   - loop value = #cycles / 6 (2 instructions)
LOADZ 0x341
$WaitHighVCOSettling
DECZ
JUMP IFNOT ZZERO $WaitHighVCOSettling

// PLL_CONFIG_LOW for actual configuration
APBWRT DAT 0 0x2000 0x30041

// SPLL actual vco loss lock after reconfiguration
// Using 5us settling time @ 50MHz
//   - #cycles = 5*1000/20=250
//   - loop value = #cycles / 6 (2 instructions)
LOADZ 0x29
$WaitActualVCOLockLoss
DECZ
JUMP IFNOT ZZERO $WaitActualVCOLockLoss

// Poll for SPLL Lock (IO_IN[0])
WAIT UNTIL INPUT0

// Lane selection before PCIE_0 PMA STATUS polling
APBREAD 0 0x2028
AND 0xFFFFF0FF
OR 0x100
APBWRT ACC 0 0x2028

// Wait for PCIE_0 PMA READY
$WaitPcie0PmaReady
APBREAD 0 0x10c0
AND 0x80
JUMP IF ZERO $WaitPcie0PmaReady

// PCIE_AXI_MASTER_WINDOW0_1
APBWRT DAT 0 0x104 0xFFFF0001
// PCIE_AXI_MASTER_WINDOW0_2
APBWRT DAT 0 0x108 0x1
// PCIE_AXI_MASTER_WINDOW1_0
APBWRT DAT 0 0x110 0x100000
// PCIE_AXI_MASTER_WINDOW1_1
APBWRT DAT 0 0x114 0xFFFFF001
// PCIE_AXI_MASTER_WINDOW1_2
APBWRT DAT 0 0x118 0x2
// PCIE_MSI_0
APBWRT DAT 0 0x80 0x18100800
// PCIE_MSI_CTRL_STATUS
APBWRT DAT 0 0x40 0x50000

// Issue Soft Reset on PCIE_0 controller
APBREAD 0 0x2008
AND 0xFFFFFFFE
APBWRT ACC 0 0x2008
OR 0x00000001
APBWRT ACC 0 0x2008

// De-assert CORE_RESET_N
IOWRT DAT 0x6

// Assert INIT_DONE
IOWRT DAT 0x7

// Hot Reset and L2 Exit detection loop (IO_IN[1])
$WaitHotResetL2Exit
IOREAD
AND 0x00000002
JUMP IF ZERO $WaitHotResetL2Exit

// Issue Soft Reset on PCIE_0 controler (bit 0) and AXI (bit 7)
//APBREAD 0 0x2008
//AND 0xFFFFFF7E
//APBWRT ACC 0 0x2008
//OR 0x00000081
//APBWRT ACC 0 0x2008

//Asserting a soft reset on PCIe_Controller(Bit 0) and AXI (bit 9)
APBREAD 0 0x2008
AND 0xFFFFFFFF
XOR 0x00000201
APBWRT ACC 0 0x2008

//De-Asserting a soft reset on PCIe_Controller(Bit 0) and AXI (bit 9)
XOR 0x00000201
APBWRT ACC 0 0x2008

// Clear GPIO[1:0] interrupts; jump back Hot Reset and L2 Exit detection loop
APBWRT DAT 1 0x80 0x3
JUMP $WaitHotResetL2Exit

HALT
 "  \
"ACT_CALIBRATIONDATA:true"  \
"APB_AWIDTH:16"  \
"APB_DWIDTH:32"  \
"APB_SDEPTH:2"  \
"APB_TIMEOUT_COUNT:80"  \
"CODEHEXDUMP:"  \
"CODEHEXDUMP2:"  \
"DEBUG:true"  \
"EN_ACM:false"  \
"EN_ADD:false"  \
"EN_ALURAM:false"  \
"EN_AND:true"  \
"EN_CALL:false"  \
"EN_DATAM:2"  \
"EN_INC:false"  \
"EN_INDIRECT:false"  \
"EN_INT:0"  \
"EN_IOREAD:true"  \
"EN_IOWRT:true"  \
"EN_MULT:0"  \
"EN_OR:true"  \
"EN_PUSH:false"  \
"EN_RAM:true"  \
"EN_RAM_ECC:false"  \
"EN_SHL:false"  \
"EN_SHR:false"  \
"EN_XOR:true"  \
"HI_REL:false"  \
"ICWIDTH:12"  \
"IFWIDTH:1"  \
"IIWIDTH:2"  \
"IMEM_APB_ACCESS:0"  \
"INITDATAWIDTH:9"  \
"INITWIDTH:11"  \
"INSMODE:0"  \
"INVALID_STACK_ACC:true"  \
"IOWIDTH:3"  \
"ISRADDR:1"  \
"MAX_NVMDWIDTH:32"  \
"STWIDTH:4"  \
"TESTMODE:0"  \
"UNIQ_STRING:COREABC_C0_COREABC_C0_0"  \
"UNIQ_STRING_LENGTH:23"  \
"VERILOGCODE:"  \
"VERILOGVARS:"  \
"ZRWIDTH:16"   }
# Exporting Component Description of COREABC_C0 to TCL done
