# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_0_IN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_1_IN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_PERST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD0_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD0_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD1_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD1_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD2_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD2_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD3_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD3_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SWITCH_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SWITCH} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CLK_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CLK} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_0_OUT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_1_OUT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD0_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD1_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD1_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD2_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD2_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD3_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD3_P} -port_direction {OUT} -port_is_pad {1}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {DIP_SWITCH} -port_direction {IN} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_ADDR} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {LED} -port_direction {OUT} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DM_RDQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1}

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add AND2_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_2}



# Add AND2_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_3}



# Add AND2_4 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_4}



# Add AND2_5 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_5}



# Add AND2_6 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_6}



# Add DEBOUNCE_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DEBOUNCE} -hdl_file {hdl\Debounce.v} -instance_name {DEBOUNCE_0}



# Add DEBOUNCE_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DEBOUNCE} -hdl_file {hdl\Debounce.v} -instance_name {DEBOUNCE_1}



# Add DMA_Controller_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DMA_Controller} -instance_name {DMA_Controller_0}



# Add pcie_init_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {pcie_init} -instance_name {pcie_init_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pcie_init_0:INIT_DONE}



# Add PCIE_SERDES_IF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PCIE_SERDES_IF_C0} -instance_name {PCIE_SERDES_IF_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PCIE_SERDES_IF_C0_0:PCIE_LTSSM} -pin_slices {[4:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_LTSSM[4:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PCIE_SERDES_IF_C0_0:PCIE_LTSSM} -pin_slices {[5:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_SYSTEM_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PLL_LOCK_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PLL_LOCKLOST_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_WAKE_N}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_WAKE_REQ} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_L2P2_AIDDQ}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_RESET_PHASE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE_SERDES_IF_C0_0:PCIE_EV_1US}



# Add RCOSC_50MHZ_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}



# Add reset_synchronizer_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}



# Add reset_synchronizer_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_1}



# Add RGRESET_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {RGRESET} -instance_name {RGRESET_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RGRESET_0:A} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RGRESET_0:A} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RGRESET_0:A} -pin_slices {[2:2]}



# Add RGRESET_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {RGRESET} -instance_name {RGRESET_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RGRESET_1:A} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RGRESET_1:A} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RGRESET_1:A} -pin_slices {[2:2]}



# Add RTG4_DDR3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_DDR3} -instance_name {RTG4_DDR3_0}



# Add RTG4FCCC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_C0} -instance_name {RTG4FCCC_C0_0}



# Add RTG4FCCCECALIB_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCCECALIB_C0} -instance_name {RTG4FCCCECALIB_C0_0}



# Add SYSRESET_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "AND2_2:A" "AND2_3:A" "RTG4FCCCECALIB_C0_0:CCC_0_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "AND2_2:B" "AND2_3:B" "AND2_4:B" "AND2_5:B" "AND2_6:B" "RTG4FCCCECALIB_C0_0:CCC_0_PLL_POWERDOWN_N" "RTG4FCCCECALIB_C0_0:CCC_1_PLL_POWERDOWN_N" "RTG4FCCCECALIB_C0_0:PLL_RST_N" "RTG4FCCCECALIB_C0_0:READY_VDDPLL" "SYSRESET_0:POWER_ON_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "RGRESET_0:A[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "pcie_init_0:CORE_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "RTG4_DDR3_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "PCIE_SERDES_IF_C0_0:CORE_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:Y" "RGRESET_0:A[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_3:Y" "RGRESET_0:A[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_4:A" "AND2_5:A" "AND2_6:A" "RTG4FCCCECALIB_C0_0:CCC_1_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_4:Y" "RGRESET_1:A[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_5:Y" "RGRESET_1:A[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_6:Y" "RGRESET_1:A[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEBOUNCE_0:CLK" "DEBOUNCE_1:CLK" "DMA_Controller_0:CLK" "PCIE_SERDES_IF_C0_0:CLK_BASE" "RTG4FCCCECALIB_C0_0:CCC_0_GL0" "RTG4_DDR3_0:CLK_BASE" "reset_synchronizer_1:clock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEBOUNCE_0:INTERRUPT" "PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEBOUNCE_0:RESET_N" "DEBOUNCE_1:RESET_N" "DMA_Controller_0:RESETn" "RTG4_DDR3_0:CORE_RESET_N" "reset_synchronizer_1:reset_sync" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEBOUNCE_0:SWITCH" "SWITCH" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEBOUNCE_1:INTERRUPT" "PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEBOUNCE_1:SWITCH" "SWITCH_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVRST_N" "SYSRESET_0:DEVRST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_Controller_0:CH0_INTR" "PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_Controller_0:CH1_INTR" "PCIE_SERDES_IF_C0_0:PCIE_INTERRUPT[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CAS_N" "RTG4_DDR3_0:FDDR_CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CKE" "RTG4_DDR3_0:FDDR_CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CLK" "RTG4_DDR3_0:FDDR_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CLK_N" "RTG4_DDR3_0:FDDR_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CS_N" "RTG4_DDR3_0:FDDR_CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_0_IN" "RTG4_DDR3_0:FDDR_DQS_TMATCH_0_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_0_OUT" "RTG4_DDR3_0:FDDR_DQS_TMATCH_0_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_1_IN" "RTG4_DDR3_0:FDDR_DQS_TMATCH_1_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_1_OUT" "RTG4_DDR3_0:FDDR_DQS_TMATCH_1_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_ODT" "RTG4_DDR3_0:FDDR_ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_RAS_N" "RTG4_DDR3_0:FDDR_RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_RESET_N" "RTG4_DDR3_0:FDDR_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_WE_N" "RTG4_DDR3_0:FDDR_WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_PERST_N" "PCIE_SERDES_IF_C0_0:PCIE_PERST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:APB_S_PCLK" "RTG4FCCCECALIB_C0_0:CCC_1_GL1" "RTG4_DDR3_0:INIT_CLK_50MHz" "pcie_init_0:INIT_CLK" "reset_synchronizer_0:clock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:APB_S_PRESET_N" "RTG4_DDR3_0:INIT_PRESET_N" "pcie_init_0:INIT_RESET_N" "reset_synchronizer_0:reset_sync" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:PCIE_L2P2_ACTIVE" "pcie_init_0:PCIE_L2P2_ACTIVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:PCIE_LTSSM[5:5]" "pcie_init_0:PCIE_LTSSM_5" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:PHY_RESET_N" "pcie_init_0:PHY_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:REFCLK_N" "REFCLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:REFCLK_P" "REFCLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD0_N" "RXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD0_P" "RXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD1_N" "RXD1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD1_P" "RXD1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD2_N" "RXD2_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD2_P" "RXD2_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD3_N" "RXD3_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:RXD3_P" "RXD3_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:SPLL_LOCK" "pcie_init_0:SPLL_LOCK_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD0_N" "TXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD0_P" "TXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD1_N" "TXD1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD1_P" "TXD1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD2_N" "TXD2_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD2_P" "TXD2_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD3_N" "TXD3_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:TXD3_P" "TXD3_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCCECALIB_C0_0:CCC_0_RCOSC_50MHZ" "RTG4FCCCECALIB_C0_0:CCC_1_RCOSC_50MHZ" "RTG4FCCC_C0_0:RCOSC_50MHZ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGRESET_0:Y" "reset_synchronizer_1:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGRESET_1:Y" "reset_synchronizer_0:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FCCCECALIB_C0_0:CLK_50MHZ" "RTG4FCCC_C0_0:GL0" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"DIP_SWITCH" "DMA_Controller_0:DIP_SWITCH" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_Controller_0:LED" "LED" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_ADDR" "RTG4_DDR3_0:FDDR_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_BA" "RTG4_DDR3_0:FDDR_BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DM_RDQS" "RTG4_DDR3_0:FDDR_DM_RDQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQ" "RTG4_DDR3_0:FDDR_DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS" "RTG4_DDR3_0:FDDR_DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_N" "RTG4_DDR3_0:FDDR_DQS_N" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_Controller_0:DDR_AXI" "RTG4_DDR3_0:AXI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_Controller_0:DMA_AXI_S" "PCIE_SERDES_IF_C0_0:AXI_MASTER" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_Controller_0:PCIE_AXI_M" "PCIE_SERDES_IF_C0_0:AXI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_SERDES_IF_C0_0:APB_SLAVE" "pcie_init_0:INIT_APB" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
