# Exporting core DDR_AXI_IF to TCL
# Exporting Create HDL core command for module DDR_AXI_IF
create_hdl_core -file {hdl/DDR_AXI_IF.v} -module {DDR_AXI_IF} -library {work} -package {}
# Exporting BIF information of  HDL core command for module DDR_AXI_IF
hdl_core_add_bif -hdl_core_name {DDR_AXI_IF} -bif_definition {AXI:AMBA:AMBA3:master} -bif_name {BIF_1} -signal_map {\
"AWID:AWID" \
"AWADDR:AWADDR" \
"AWLEN:AWLEN" \
"AWSIZE:AWSIZE" \
"AWBURST:AWBURST" \
"AWVALID:AWVALID" \
"AWREADY:AWREADY" \
"WID:WID" \
"WDATA:WDATA" \
"WSTRB:WSTRB" \
"WLAST:WLAST" \
"WVALID:WVALID" \
"WREADY:WREADY" \
"BID:BID" \
"BRESP:BRESP" \
"BVALID:BVALID" \
"BREADY:BREADY" \
"ARID:ARID" \
"ARADDR:ARADDR" \
"ARLEN:ARLEN" \
"ARSIZE:ARSIZE" \
"ARBURST:ARBURST" \
"ARVALID:ARVALID" \
"ARREADY:ARREADY" \
"RID:RID" \
"RDATA:RDATA" \
"RRESP:RRESP" \
"RLAST:RLAST" \
"RVALID:RVALID" \
"RREADY:RREADY" }
