///////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------------
//-- Title      : AXI Master to Slave Interface
//-------------------------------------------------------------------------------
//-- File       : AXI_MASTER_TO_SLAVE.v
//-- Author     : Corporate Applications Engineering
//-- Company    : Microsemi Corporation
//-- Device     : RTG4
//-- Standard   : Verilog
//-------------------------------------------------------------------------------
//-- Description: This code implementes the wire logic to connect the  
//--              AXI master IF to slave IF.
//-------------------------------------------------------------------------------
//-- Copyright (c) 2015   Microsemi Corporation
//--                      All rights reserved.
//-------------------------------------------------------------------------------
//-- Revisions  : V1.0
//-------------------------------------------------------------------------------
/////////////////////////////////////////////////////////////////////////////////////////////////// 
module AXI_MASTER_TO_SLAVE(
                           // AXI Mirror Slave interface
                           AWID,
                           AWADDR,
                           AWLEN,
                           AWSIZE,
                           AWBURST,
                           AWLOCK,
                           AWCACHE,
                           AWPROT,
                           AWVALID,
                           AWREADY,
                           WID,
                           WDATA,
                           WSTRB,
                           WLAST,
                           WVALID,
                           WREADY,
                           BID,
                           BRESP,
                           BVALID,
                           BREADY,
                           ARID,
                           ARADDR,
                           ARLEN,
                           ARSIZE,
                           ARBURST,
                           ARLOCK,
                           ARCACHE,
                           ARPROT,
                           ARVALID,
                           ARREADY,
                           RID,
                           RDATA,
                           RLAST,
                           RRESP,
                           RVALID,
                           RREADY,
                           // AXI Mirror Master interface
                           MM_AWID,
                           MM_AWADDR,
                           MM_AWLEN,
                           MM_AWSIZE,
                           MM_AWBURST,
                           MM_AWLOCK,
                           MM_AWCACHE,
                           MM_AWPROT,
                           MM_AWVALID,
                           MM_AWREADY,
                           MM_WID,
                           MM_WDATA,
                           MM_WSTRB,
                           MM_WLAST,
                           MM_WVALID,
                           MM_WREADY,
                           MM_BID,
                           MM_BRESP,
                           MM_BVALID,
                           MM_BREADY,
                           MM_ARID,
                           MM_ARADDR,
                           MM_ARLEN,
                           MM_ARSIZE,
                           MM_ARBURST,
                           MM_ARLOCK,
                           MM_ARCACHE,
                           MM_ARPROT,
                           MM_ARVALID,
                           MM_ARREADY,
                           MM_RID,
                           MM_RDATA,
                           MM_RRESP,
                           MM_RLAST,
                           MM_RVALID,
                           MM_RREADY);
  // Parameters
  parameter ID_BITS = 4;
  parameter ADDR_WIDTH = 32;
  // AXI Mirror Slave interface
  output[(ID_BITS - 1) : 0] AWID;
  output[(ADDR_WIDTH - 1) : 0] AWADDR;
  output[3 : 0] AWLEN;
  output[2 : 0] AWSIZE;
  output[1 : 0] AWBURST;
  output[1 : 0] AWLOCK;
  output[3 : 0] AWCACHE;
  output[2 : 0] AWPROT;
  output AWVALID;
  input AWREADY;
  output[(ID_BITS - 1) : 0] WID;
  output[63 : 0] WDATA;
  output[7 : 0] WSTRB;
  output WLAST;
  output WVALID;
  input WREADY;
  input[(ID_BITS - 1) : 0] BID;
  input[1 : 0] BRESP;
  input BVALID;
  output BREADY;
  output[(ID_BITS - 1) : 0] ARID;
  output[(ADDR_WIDTH - 1) : 0] ARADDR;
  output[3 : 0] ARLEN;
  output[2 : 0] ARSIZE;
  output[1 : 0] ARBURST;
  output[1 : 0] ARLOCK;
  output[3 : 0] ARCACHE;
  output[2 : 0] ARPROT;
  output ARVALID;
  input ARREADY;
  input[(ID_BITS - 1) : 0] RID;
  input[63 : 0] RDATA;
  input RLAST;
  input[1 : 0] RRESP;
  input RVALID;
  output RREADY;
  // AXI Mirror Master interface
  input[(ID_BITS - 1) : 0] MM_AWID;
  input[(ADDR_WIDTH - 1) : 0] MM_AWADDR;
  input[3 : 0] MM_AWLEN;
  input[2 : 0] MM_AWSIZE;
  input[1 : 0] MM_AWBURST;
  input[1 : 0] MM_AWLOCK;
  input[3 : 0] MM_AWCACHE;
  input[2 : 0] MM_AWPROT;
  input MM_AWVALID;
  output MM_AWREADY;
  input[(ID_BITS - 1) : 0] MM_WID;
  input[63 : 0] MM_WDATA;
  input[7 : 0] MM_WSTRB;
  input MM_WLAST;
  input MM_WVALID;
  output MM_WREADY;
  output[(ID_BITS - 1) : 0] MM_BID;
  output[1 : 0] MM_BRESP;
  output MM_BVALID;
  input MM_BREADY;
  input[(ID_BITS - 1) : 0] MM_ARID;
  input[(ADDR_WIDTH - 1) : 0] MM_ARADDR;
  input[3 : 0] MM_ARLEN;
  input[2 : 0] MM_ARSIZE;
  input[1 : 0] MM_ARBURST;
  input[1 : 0] MM_ARLOCK;
  input[3 : 0] MM_ARCACHE;
  input[2 : 0] MM_ARPROT;
  input MM_ARVALID;
  output MM_ARREADY;
  output[(ID_BITS - 1) : 0] MM_RID;
  output[63 : 0] MM_RDATA;
  output[1 : 0] MM_RRESP;
  output MM_RLAST;
  output MM_RVALID;
  input MM_RREADY;
  assign AWID = MM_AWID;
  assign AWADDR = MM_AWADDR;
  assign AWLEN = MM_AWLEN;
  assign AWSIZE = MM_AWSIZE;
  assign AWBURST = MM_AWBURST;
  assign AWLOCK = MM_AWLOCK;
  assign AWCACHE = MM_AWCACHE;
  assign AWPROT = MM_AWPROT;
  assign AWVALID = MM_AWVALID;
  assign MM_AWREADY = AWREADY;
  assign WID = MM_WID;
  assign WDATA = MM_WDATA;
  assign WSTRB = MM_WSTRB;
  assign WLAST = MM_WLAST;
  assign WVALID = MM_WVALID;
  assign MM_WREADY = WREADY;
  assign MM_BID = BID;
  assign MM_BRESP = BRESP;
  assign MM_BVALID = BVALID;
  assign BREADY = MM_BREADY;
  assign ARID = MM_ARID;
  assign ARADDR = MM_ARADDR;
  assign ARLEN = MM_ARLEN;
  assign ARSIZE = MM_ARSIZE;
  assign ARBURST = MM_ARBURST;
  assign ARLOCK = MM_ARLOCK;
  assign ARCACHE = MM_ARCACHE;
  assign ARPROT = MM_ARPROT;
  assign ARVALID = MM_ARVALID;
  assign MM_ARREADY = ARREADY;
  assign MM_RID = RID;
  assign MM_RDATA = RDATA;
  assign MM_RLAST = RLAST;
  assign MM_RRESP = RRESP;
  assign MM_RVALID = RVALID;
  assign RREADY = MM_RREADY;
endmodule
