# Creating SmartDesign "DMA_Controller"
set sd_name {DMA_Controller}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARREADY_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AWREADY_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BVALID_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_ARVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_AWVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_BREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_RREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_WLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_WVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETn} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RLAST_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RVALID_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WREADY_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WREADY} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ARVALID_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AWVALID_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BREADY_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CH0_INT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CH1_INT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_ARREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_AWREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_BVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_RLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_RVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MM_WREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RREADY_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WLAST_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WVALID_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WVALID} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {BID_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BRESP_0} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DIP_SWITCH} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARCACHE} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARLEN} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARLOCK} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARPROT} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_ARSIZE} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWCACHE} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWLEN} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWLOCK} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWPROT} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_AWSIZE} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_WDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_WID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_WSTRB} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RDATA_0} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RID_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RRESP_0} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {RRESP} -port_direction {IN} -port_range {[1:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {ARADDR_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARBURST_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARCACHE_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARID_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARLEN_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARLEN} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARLOCK_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARPROT_0} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARSIZE_0} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWADDR_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWBURST_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWCACHE_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWID_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWLEN_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWLEN} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWLOCK_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWPROT_0} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWSIZE_0} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LED} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_BID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_BRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_RDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_RID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MM_RRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WDATA_0} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WID_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WSTRB_0} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {WSTRB} -port_direction {OUT} -port_range {[7:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {PCIE_AXI_M} -port_bif_vlnv {AMBA:AMBA3:AXI:r1p0_5} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AWID" \
"AWADDR:AWADDR" \
"AWLEN:AWLEN" \
"AWSIZE:AWSIZE" \
"AWBURST:AWBURST" \
"AWLOCK:AWLOCK" \
"AWCACHE:AWCACHE" \
"AWPROT:AWPROT" \
"AWVALID:AWVALID" \
"AWREADY:AWREADY" \
"WID:WID" \
"WDATA:WDATA" \
"WSTRB:WSTRB" \
"WLAST:WLAST" \
"WVALID:WVALID" \
"WREADY:WREADY" \
"BID:BID" \
"BRESP:BRESP" \
"BVALID:BVALID" \
"BREADY:BREADY" \
"ARID:ARID" \
"ARADDR:ARADDR" \
"ARLEN:ARLEN" \
"ARSIZE:ARSIZE" \
"ARBURST:ARBURST" \
"ARLOCK:ARLOCK" \
"ARCACHE:ARCACHE" \
"ARPROT:ARPROT" \
"ARVALID:ARVALID" \
"ARREADY:ARREADY" \
"RID:RID" \
"RDATA:RDATA" \
"RRESP:RRESP" \
"RLAST:RLAST" \
"RVALID:RVALID" \
"RREADY:RREADY" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_AXI} -port_bif_vlnv {AMBA:AMBA3:AXI:r1p0_5} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AWID_0" \
"AWADDR:AWADDR_0" \
"AWLEN:AWLEN_0" \
"AWSIZE:AWSIZE_0" \
"AWBURST:AWBURST_0" \
"AWLOCK:AWLOCK_0" \
"AWCACHE:AWCACHE_0" \
"AWPROT:AWPROT_0" \
"AWVALID:AWVALID_0" \
"AWREADY:AWREADY_0" \
"WID:WID_0" \
"WDATA:WDATA_0" \
"WSTRB:WSTRB_0" \
"WLAST:WLAST_0" \
"WVALID:WVALID_0" \
"WREADY:WREADY_0" \
"BID:BID_0" \
"BRESP:BRESP_0" \
"BVALID:BVALID_0" \
"BREADY:BREADY_0" \
"ARID:ARID_0" \
"ARADDR:ARADDR_0" \
"ARLEN:ARLEN_0" \
"ARSIZE:ARSIZE_0" \
"ARBURST:ARBURST_0" \
"ARLOCK:ARLOCK_0" \
"ARCACHE:ARCACHE_0" \
"ARPROT:ARPROT_0" \
"ARVALID:ARVALID_0" \
"ARREADY:ARREADY_0" \
"RID:RID_0" \
"RDATA:RDATA_0" \
"RRESP:RRESP_0" \
"RLAST:RLAST_0" \
"RVALID:RVALID_0" \
"RREADY:RREADY_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DMA_AXI_S} -port_bif_vlnv {AMBA:AMBA3:AXI:r1p0_5} -port_bif_role {mirroredMaster} -port_bif_mapping {\
"AWID:MM_AWID" \
"AWADDR:MM_AWADDR" \
"AWLEN:MM_AWLEN" \
"AWSIZE:MM_AWSIZE" \
"AWBURST:MM_AWBURST" \
"AWLOCK:MM_AWLOCK" \
"AWCACHE:MM_AWCACHE" \
"AWPROT:MM_AWPROT" \
"AWVALID:MM_AWVALID" \
"AWREADY:MM_AWREADY" \
"WID:MM_WID" \
"WDATA:MM_WDATA" \
"WSTRB:MM_WSTRB" \
"WLAST:MM_WLAST" \
"WVALID:MM_WVALID" \
"WREADY:MM_WREADY" \
"BID:MM_BID" \
"BRESP:MM_BRESP" \
"BVALID:MM_BVALID" \
"BREADY:MM_BREADY" \
"ARID:MM_ARID" \
"ARADDR:MM_ARADDR" \
"ARLEN:MM_ARLEN" \
"ARSIZE:MM_ARSIZE" \
"ARBURST:MM_ARBURST" \
"ARLOCK:MM_ARLOCK" \
"ARCACHE:MM_ARCACHE" \
"ARPROT:MM_ARPROT" \
"ARVALID:MM_ARVALID" \
"ARREADY:MM_ARREADY" \
"RID:MM_RID" \
"RDATA:MM_RDATA" \
"RRESP:MM_RRESP" \
"RLAST:MM_RLAST" \
"RVALID:MM_RVALID" \
"RREADY:MM_RREADY" } 

# Add AXI_MASTER_TO_SLAVE_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI_MASTER_TO_SLAVE} -instance_name {AXI_MASTER_TO_SLAVE_0}
# Exporting Parameters of instance AXI_MASTER_TO_SLAVE_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_0} -params {\
"ADDR_WIDTH:32" \
"ID_BITS:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_0}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_0}



# Add AXI_MASTER_TO_SLAVE_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI_MASTER_TO_SLAVE} -instance_name {AXI_MASTER_TO_SLAVE_1}
# Exporting Parameters of instance AXI_MASTER_TO_SLAVE_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_1} -params {\
"ADDR_WIDTH:32" \
"ID_BITS:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_1}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_1}



# Add AXI_MASTER_TO_SLAVE_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI_MASTER_TO_SLAVE} -instance_name {AXI_MASTER_TO_SLAVE_2}
# Exporting Parameters of instance AXI_MASTER_TO_SLAVE_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_2} -params {\
"ADDR_WIDTH:32" \
"ID_BITS:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_2}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI_MASTER_TO_SLAVE_2}



# Add Controller_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Controller} -instance_name {Controller_0}



# Add DDR_AXI_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {DDR_AXI_IF} -instance_name {DDR_AXI_IF_0}



# Add PCIe_AXI_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PCIe_AXI_IF} -instance_name {PCIe_AXI_IF_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CH0_INT" "Controller_0:CH0_INT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CH1_INT" "Controller_0:CH1_INT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK" "Controller_0:CLK" "DDR_AXI_IF_0:CLK" "PCIe_AXI_IF_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:DDR_READ_DONE" "DDR_AXI_IF_0:READ_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:DDR_WRITE_DONE" "DDR_AXI_IF_0:WRITE_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:PCIE_READ_DONE" "PCIe_AXI_IF_0:READ_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:PCIE_WRITE_DONE" "PCIe_AXI_IF_0:WRITE_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:PC_BASE_ADDR_VALID" "PCIe_AXI_IF_0:PC_BASE_ADDR_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:RESETn" "DDR_AXI_IF_0:RESETn" "PCIe_AXI_IF_0:RESETn" "RESETn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:PCI_WRITE_START" "PCIe_AXI_IF_0:WRITE_START" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:PC_RD_BUSY" "PCIe_AXI_IF_0:PC_RD_BUSY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:RD_BUSY" "PCIe_AXI_IF_0:RD_BUSY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:WRITE_START" "PCIe_AXI_IF_0:DDR_WRITE_START" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:DIP_SWITCH" "DIP_SWITCH" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:DMA_DIR" "DDR_AXI_IF_0:DMA_DIR" "PCIe_AXI_IF_0:DMA_DIR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:DMA_SIZE" "DDR_AXI_IF_0:DMA_SIZE" "PCIe_AXI_IF_0:DMA_SIZE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:LED" "LED" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Controller_0:PC_BASE_ADDR" "PCIe_AXI_IF_0:PC_BASE_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:DATA_PCIe" "PCIe_AXI_IF_0:DATA_TO_DDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:DATA_TO_PCIe" "PCIe_AXI_IF_0:DATA_DDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:DDR_WRITE_CNT" "PCIe_AXI_IF_0:DDR_WRITE_CNT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:PC2DDR_RAM_ADDR" "PCIe_AXI_IF_0:PC2DDR_RAM_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:RAM_ADDR" "PCIe_AXI_IF_0:RAM_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI_IF_0:WRITE_CNT" "PCIe_AXI_IF_0:WRITE_CNT" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_MASTER_TO_SLAVE_0:M" "DMA_AXI_S" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_MASTER_TO_SLAVE_0:S" "Controller_0:BIF_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_MASTER_TO_SLAVE_1:M" "PCIe_AXI_IF_0:BIF_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_MASTER_TO_SLAVE_1:S" "PCIE_AXI_M" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_MASTER_TO_SLAVE_2:M" "DDR_AXI_IF_0:BIF_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_MASTER_TO_SLAVE_2:S" "DDR_AXI" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "DMA_Controller"
generate_component -component_name ${sd_name}
