# Creating SmartDesign "pcie_init"
set sd_name {pcie_init}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_L2P2_ACTIVE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_LTSSM_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PREADYS0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PSLVERRS0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPLL_LOCK_IN} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CORE_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PENABLES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PSELS0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PWRITES} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {PRDATAS0} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {PADDRS} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PWDATAS} -port_direction {OUT} -port_range {[31:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {INIT_APB} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"PADDR:PADDRS" \
"PSELx:PSELS0" \
"PENABLE:PENABLES" \
"PWRITE:PWRITES" \
"PRDATA:PRDATAS0" \
"PWDATA:PWDATAS" \
"PREADY:PREADYS0" \
"PSLVERR:PSLVERRS0" } 

# Add COREABC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREABC_C0} -instance_name {COREABC_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABC_C0_0:IO_IN} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABC_C0_0:IO_IN} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABC_C0_0:IO_OUT} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABC_C0_0:IO_OUT} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABC_C0_0:IO_OUT} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREABC_C0_0:PRESETN}



# Add CoreAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0}



# Add CoreGPIO_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_C0} -instance_name {CoreGPIO_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_IN} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_IN} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:GPIO_OUT}



# Add HOTRESET_DETECT_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {HOTRESET_DETECT} -hdl_file {hdl\HOTRESET_DETECT.v} -instance_name {HOTRESET_DETECT_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:IO_IN[0:0]" "SPLL_LOCK_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:IO_IN[1:1]" "CoreGPIO_C0_0:INT_OR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:IO_OUT[0:0]" "INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:IO_OUT[1:1]" "PHY_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:IO_OUT[2:2]" "CORE_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:NSYSRESET" "CoreGPIO_C0_0:PRESETN" "HOTRESET_DETECT_0:SRESET_N" "INIT_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:PCLK" "CoreGPIO_C0_0:PCLK" "HOTRESET_DETECT_0:INIT_CLK" "HOTRESET_DETECT_0:PCIE_LTSSM_CLK" "INIT_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_IN[0:0]" "HOTRESET_DETECT_0:HOTRESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_IN[1:1]" "PCIE_L2P2_ACTIVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HOTRESET_DETECT_0:PCIE_LTSSM_5" "PCIE_LTSSM_5" }


# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:APB3Initiator" "CoreAPB3_C0_0:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APBmslave0" "INIT_APB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APBmslave1" "CoreGPIO_C0_0:APB_bif" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "pcie_init"
generate_component -component_name ${sd_name}
