# Exporting Component Description of BAR1_LSRAM to TCL
# Family: RTG4
# Part Number: RT4G150-1CG1657
# Create and Configure the core component BAR1_LSRAM
create_and_configure_core -core_vlnv Actel:SgCore:RTG4TPSRAM:$RTG4TPSRAMver -component_name {BAR1_LSRAM} -params {\
"A_DOUT_EN_PN:RD_EN"  \
"A_DOUT_EN_POLARITY:2"  \
"A_DOUT_SRST_PN:RD_SRST_N"  \
"A_DOUT_SRST_POLARITY:2"  \
"A_WBYTE_EN_PN:A_WBYTE_EN"  \
"ARST_N_POLARITY:2"  \
"BYTE_ENABLE_WIDTH:0"  \
"BYTEENABLES:0"  \
"CASCADE:0"  \
"CLK_EDGE:RISE"  \
"CLKS:1"  \
"CLOCK_PN:CLK"  \
"DATA_IN_PN:WD"  \
"DATA_OUT_PN:RD"  \
"ECC:0"  \
"IMPORT_FILE:"  \
"INIT_RAM:F"  \
"LPMTYPE:LPM_RAM"  \
"PTYPE:1"  \
"RADDRESS_PN:RADDR"  \
"RCLK_EDGE:RISE"  \
"RCLOCK_PN:RCLK"  \
"RDEPTH:512"  \
"RE_PN:REN"  \
"RE_POLARITY:2"  \
"RESET_PN:ARST_N"  \
"RPMODE:0"  \
"RWIDTH:64"  \
"WADDRESS_PN:WADDR"  \
"WCLK_EDGE:RISE"  \
"WCLOCK_PN:WCLK"  \
"WDEPTH:1024"  \
"WE_PN:WEN"  \
"WE_POLARITY:1"  \
"WWIDTH:32"   }
# Exporting Component Description of BAR1_LSRAM to TCL done
