# Exporting core AXI_MASTER_TO_SLAVE to TCL
# Exporting Create HDL core command for module AXI_MASTER_TO_SLAVE
create_hdl_core -file {hdl/AXI_MASTER_TO_SLAVE.v} -module {AXI_MASTER_TO_SLAVE} -library {work} -package {}
# Exporting BIF information of  HDL core command for module AXI_MASTER_TO_SLAVE
hdl_core_add_bif -hdl_core_name {AXI_MASTER_TO_SLAVE} -bif_definition {AXI:AMBA:AMBA3:mirroredMaster} -bif_name {M} -signal_map {\
"AWID:MM_AWID" \
"AWADDR:MM_AWADDR" \
"AWLEN:MM_AWLEN" \
"AWSIZE:MM_AWSIZE" \
"AWBURST:MM_AWBURST" \
"AWLOCK:MM_AWLOCK" \
"AWCACHE:MM_AWCACHE" \
"AWPROT:MM_AWPROT" \
"AWVALID:MM_AWVALID" \
"AWREADY:MM_AWREADY" \
"WID:MM_WID" \
"WDATA:MM_WDATA" \
"WSTRB:MM_WSTRB" \
"WLAST:MM_WLAST" \
"WVALID:MM_WVALID" \
"WREADY:MM_WREADY" \
"BID:MM_BID" \
"BRESP:MM_BRESP" \
"BVALID:MM_BVALID" \
"BREADY:MM_BREADY" \
"ARID:MM_ARID" \
"ARADDR:MM_ARADDR" \
"ARLEN:MM_ARLEN" \
"ARSIZE:MM_ARSIZE" \
"ARBURST:MM_ARBURST" \
"ARLOCK:MM_ARLOCK" \
"ARCACHE:MM_ARCACHE" \
"ARPROT:MM_ARPROT" \
"ARVALID:MM_ARVALID" \
"ARREADY:MM_ARREADY" \
"RID:MM_RID" \
"RDATA:MM_RDATA" \
"RRESP:MM_RRESP" \
"RLAST:MM_RLAST" \
"RVALID:MM_RVALID" \
"RREADY:MM_RREADY" }
hdl_core_add_bif -hdl_core_name {AXI_MASTER_TO_SLAVE} -bif_definition {AXI:AMBA:AMBA3:mirroredSlave} -bif_name {S} -signal_map {\
"AWID:AWID" \
"AWADDR:AWADDR" \
"AWLEN:AWLEN" \
"AWSIZE:AWSIZE" \
"AWBURST:AWBURST" \
"AWLOCK:AWLOCK" \
"AWCACHE:AWCACHE" \
"AWPROT:AWPROT" \
"AWVALID:AWVALID" \
"AWREADY:AWREADY" \
"WID:WID" \
"WDATA:WDATA" \
"WSTRB:WSTRB" \
"WLAST:WLAST" \
"WVALID:WVALID" \
"WREADY:WREADY" \
"BID:BID" \
"BRESP:BRESP" \
"BVALID:BVALID" \
"BREADY:BREADY" \
"ARID:ARID" \
"ARADDR:ARADDR" \
"ARLEN:ARLEN" \
"ARSIZE:ARSIZE" \
"ARBURST:ARBURST" \
"ARLOCK:ARLOCK" \
"ARCACHE:ARCACHE" \
"ARPROT:ARPROT" \
"ARVALID:ARVALID" \
"ARREADY:ARREADY" \
"RID:RID" \
"RDATA:RDATA" \
"RRESP:RRESP" \
"RLAST:RLAST" \
"RVALID:RVALID" \
"RREADY:RREADY" }
