   1              		.file	"core_spi.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0_m2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              		.section	.text.recover_from_rx_overflow.isra.0,"ax",@progbits
   8              		.align	2
  10              	recover_from_rx_overflow.isra.0:
  11 0000 130101FF 		addi	sp,sp,-16
  12 0004 23248100 		sw	s0,8(sp)
  13 0008 13040500 		mv	s0,a0
  14 000c 03250500 		lw	a0,0(a0)
  15 0010 93060000 		li	a3,0
  16 0014 13061000 		li	a2,1
  17 0018 93050000 		li	a1,0
  18 001c 23261100 		sw	ra,12(sp)
  19 0020 97000000 		call	HW_set_8bit_reg_field
  19      E7800000 
  20 0028 03250400 		lw	a0,0(s0)
  21 002c 93053000 		li	a1,3
  22 0030 1305C501 		addi	a0,a0,28
  23 0034 97000000 		call	HW_set_8bit_reg
  23      E7800000 
  24 003c 03250400 		lw	a0,0(s0)
  25 0040 9305F00F 		li	a1,255
  26 0044 13054500 		addi	a0,a0,4
  27 0048 97000000 		call	HW_set_8bit_reg
  27      E7800000 
  28 0050 03250400 		lw	a0,0(s0)
  29 0054 03248100 		lw	s0,8(sp)
  30 0058 8320C100 		lw	ra,12(sp)
  31 005c 93061000 		li	a3,1
  32 0060 13061000 		li	a2,1
  33 0064 93050000 		li	a1,0
  34 0068 13010101 		addi	sp,sp,16
  35 006c 17030000 		tail	HW_set_8bit_reg_field
  35      67000300 
  37              		.section	.text.fill_slave_tx_fifo,"ax",@progbits
  38              		.align	2
  40              	fill_slave_tx_fifo:
  41 0000 03270501 		lw	a4,16(a0)
  42 0004 8327C500 		lw	a5,12(a0)
  43 0008 130101FF 		addi	sp,sp,-16
  44 000c 23248100 		sw	s0,8(sp)
  45 0010 23261100 		sw	ra,12(sp)
  46 0014 13040500 		mv	s0,a0
  47 0018 636EF702 		bltu	a4,a5,.L5
  48 001c 6F000007 		j	.L8
  49              	.L7:
  50 0020 03270401 		lw	a4,16(s0)
  51 0024 83278400 		lw	a5,8(s0)
  52 0028 03250400 		lw	a0,0(s0)
  53 002c B387E700 		add	a5,a5,a4
  54 0030 83C50700 		lbu	a1,0(a5)
  55 0034 1305C500 		addi	a0,a0,12
  56 0038 97000000 		call	HW_set_32bit_reg
  56      E7800000 
  57 0040 83270401 		lw	a5,16(s0)
  58 0044 0327C400 		lw	a4,12(s0)
  59 0048 93871700 		addi	a5,a5,1
  60 004c 2328F400 		sw	a5,16(s0)
  61 0050 63FEE702 		bgeu	a5,a4,.L8
  62              	.L5:
  63 0054 03250400 		lw	a0,0(s0)
  64 0058 13068000 		li	a2,8
  65 005c 93053000 		li	a1,3
  66 0060 13050502 		addi	a0,a0,32
  67 0064 97000000 		call	HW_get_8bit_reg_field
  67      E7800000 
  68 006c E30A05FA 		beq	a0,zero,.L7
  69 0070 03270401 		lw	a4,16(s0)
  70 0074 8327C400 		lw	a5,12(s0)
  71 0078 637AF700 		bgeu	a4,a5,.L8
  72              	.L4:
  73 007c 8320C100 		lw	ra,12(sp)
  74 0080 03248100 		lw	s0,8(sp)
  75 0084 13010101 		addi	sp,sp,16
  76 0088 67800000 		jr	ra
  77              	.L8:
  78 008c 0327C401 		lw	a4,28(s0)
  79 0090 83278401 		lw	a5,24(s0)
  80 0094 E374F7FE 		bgeu	a4,a5,.L4
  81 0098 03250400 		lw	a0,0(s0)
  82 009c 13068000 		li	a2,8
  83 00a0 93053000 		li	a1,3
  84 00a4 13050502 		addi	a0,a0,32
  85 00a8 97000000 		call	HW_get_8bit_reg_field
  85      E7800000 
  86 00b0 E31605FC 		bne	a0,zero,.L4
  87              	.L10:
  88 00b4 0327C401 		lw	a4,28(s0)
  89 00b8 83274401 		lw	a5,20(s0)
  90 00bc 03250400 		lw	a0,0(s0)
  91 00c0 B387E700 		add	a5,a5,a4
  92 00c4 83C50700 		lbu	a1,0(a5)
  93 00c8 1305C500 		addi	a0,a0,12
  94 00cc 97000000 		call	HW_set_32bit_reg
  94      E7800000 
  95 00d4 8327C401 		lw	a5,28(s0)
  96 00d8 03278401 		lw	a4,24(s0)
  97 00dc 93871700 		addi	a5,a5,1
  98 00e0 232EF400 		sw	a5,28(s0)
  99 00e4 E3FCE7F8 		bgeu	a5,a4,.L4
 100 00e8 03250400 		lw	a0,0(s0)
 101 00ec 13068000 		li	a2,8
 102 00f0 93053000 		li	a1,3
 103 00f4 13050502 		addi	a0,a0,32
 104 00f8 97000000 		call	HW_get_8bit_reg_field
 104      E7800000 
 105 0100 E30A05FA 		beq	a0,zero,.L10
 106 0104 8320C100 		lw	ra,12(sp)
 107 0108 03248100 		lw	s0,8(sp)
 108 010c 13010101 		addi	sp,sp,16
 109 0110 67800000 		jr	ra
 111              		.section	.text.read_slave_rx_fifo,"ax",@progbits
 112              		.align	2
 114              	read_slave_rx_fifo:
 115 0000 83278504 		lw	a5,72(a0)
 116 0004 130101FF 		addi	sp,sp,-16
 117 0008 23248100 		sw	s0,8(sp)
 118 000c 23261100 		sw	ra,12(sp)
 119 0010 13071000 		li	a4,1
 120 0014 13040500 		mv	s0,a0
 121 0018 03250500 		lw	a0,0(a0)
 122 001c 6380E70A 		beq	a5,a4,.L17
 123 0020 13072000 		li	a4,2
 124 0024 6390E70C 		bne	a5,a4,.L34
 125 0028 13064000 		li	a2,4
 126 002c 93052000 		li	a1,2
 127 0030 13050502 		addi	a0,a0,32
 128 0034 97000000 		call	HW_get_8bit_reg_field
 128      E7800000 
 129 003c 631C0502 		bne	a0,zero,.L16
 130              	.L26:
 131 0040 03250400 		lw	a0,0(s0)
 132 0044 13058500 		addi	a0,a0,8
 133 0048 97000000 		call	HW_get_32bit_reg
 133      E7800000 
 134 0050 83274403 		lw	a5,52(s0)
 135 0054 6396070A 		bne	a5,zero,.L24
 136 0058 03250400 		lw	a0,0(s0)
 137              	.L35:
 138 005c 13064000 		li	a2,4
 139 0060 93052000 		li	a1,2
 140 0064 13050502 		addi	a0,a0,32
 141 0068 97000000 		call	HW_get_8bit_reg_field
 141      E7800000 
 142 0070 E30805FC 		beq	a0,zero,.L26
 143              	.L16:
 144 0074 8320C100 		lw	ra,12(sp)
 145 0078 03248100 		lw	s0,8(sp)
 146 007c 13010101 		addi	sp,sp,16
 147 0080 67800000 		jr	ra
 148              	.L20:
 149 0084 03250400 		lw	a0,0(s0)
 150 0088 13058500 		addi	a0,a0,8
 151 008c 97000000 		call	HW_get_32bit_reg
 151      E7800000 
 152 0094 83270403 		lw	a5,48(s0)
 153 0098 0327C402 		lw	a4,44(s0)
 154 009c 63FAE700 		bgeu	a5,a4,.L19
 155 00a0 03278402 		lw	a4,40(s0)
 156 00a4 B307F700 		add	a5,a4,a5
 157 00a8 2380A700 		sb	a0,0(a5)
 158 00ac 83270403 		lw	a5,48(s0)
 159              	.L19:
 160 00b0 03250400 		lw	a0,0(s0)
 161 00b4 93871700 		addi	a5,a5,1
 162 00b8 2328F402 		sw	a5,48(s0)
 163              	.L17:
 164 00bc 13064000 		li	a2,4
 165 00c0 93052000 		li	a1,2
 166 00c4 13050502 		addi	a0,a0,32
 167 00c8 97000000 		call	HW_get_8bit_reg_field
 167      E7800000 
 168 00d0 E30A05FA 		beq	a0,zero,.L20
 169 00d4 8320C100 		lw	ra,12(sp)
 170 00d8 03248100 		lw	s0,8(sp)
 171 00dc 13010101 		addi	sp,sp,16
 172 00e0 67800000 		jr	ra
 173              	.L34:
 174 00e4 03248100 		lw	s0,8(sp)
 175 00e8 8320C100 		lw	ra,12(sp)
 176 00ec 93051000 		li	a1,1
 177 00f0 1305C501 		addi	a0,a0,28
 178 00f4 13010101 		addi	sp,sp,16
 179 00f8 17030000 		tail	HW_set_8bit_reg
 179      67000300 
 180              	.L24:
 181 0100 E7800700 		jalr	a5
 182 0104 03250400 		lw	a0,0(s0)
 183 0108 6FF05FF5 		j	.L35
 185              		.section	.text.SPI_init,"ax",@progbits
 186              		.align	2
 187              		.globl	SPI_init
 189              	SPI_init:
 190 0000 130101FF 		addi	sp,sp,-16
 191 0004 23248100 		sw	s0,8(sp)
 192 0008 23229100 		sw	s1,4(sp)
 193 000c 23202101 		sw	s2,0(sp)
 194 0010 23261100 		sw	ra,12(sp)
 195 0014 13040500 		mv	s0,a0
 196 0018 93840500 		mv	s1,a1
 197 001c 13090600 		mv	s2,a2
 198 0020 630E0502 		beq	a0,zero,.L52
 199              	.L37:
 200 0024 63940400 		bne	s1,zero,.L38
 201              	 #APP
 202              	# 70 "../drivers/CoreSPI/core_spi.c" 1
   1              	/***************************************************************************//**
   2              	 * Copyright 2013-2023 Microchip FPGA Embedded Systems Solutions.
   3              	 *
   4              	 * SPDX-License-Identifier: MIT
   5              	 *
   6              	 * CoreSPI bare metal driver implementation for CoreSPI.
   7              	 *
   8              	 * This Core SPI driver provides functions for implementing SPI master or
   9              	 * SPI slave operations with the CoreSPI version 4.2.xxx It is not compatible
  10              	 * with CoreSPI version 3.0.xxx.
  11              	 *
  12              	 * @file core_spi.c
  13              	 * @author Microchip FPGA Embedded Systems Solutions
  14              	 * @brief CoreSPI software configuration
  15              	 *
  16              	 */
  17              	
  18              	#include "core_spi.h"
  19              	#include "corespi_regs.h"
  20              	#include <string.h>
  21              	
  22              	/*******************************************************************************
  23              	 * Null parameters with appropriate type definitions
  24              	 */
  25              	#define NULL_ADDR              ( ( addr_t ) 0u )
  26              	#define NULL_INSTANCE          ( ( spi_instance_t * ) 0u )
  27              	#define NULL_BUFF              ( ( uint8_t * ) 0u )
  28              	#define NULL_FRAME_HANDLER     ( ( spi_frame_rx_handler_t ) 0u )
  29              	#define NULL_BLOCK_HANDLER     ( ( spi_block_rx_handler_t ) 0u )
  30              	#define NULL_SLAVE_TX_UPDATE_HANDLER ( ( spi_slave_frame_tx_handler_t ) 0u )
  31              	#define NULL_SLAVE_CMD_HANDLER  NULL_BLOCK_HANDLER
  32              	
  33              	#define SPI_ALL_INTS (0xFFu) /* For clearing all active interrupts */
  34              	
  35              	/*******************************************************************************
  36              	 * Possible states for different register bit fields
  37              	 */
  38              	
  39              	#define    DISABLE 0u
  40              	#define    ENABLE  1u
  41              	
  42              	
  43              	/*******************************************************************************
  44              	 * Function return values
  45              	 */
  46              	enum {
  47              	    FAILURE = 0u,
  48              	    SUCCESS = 1u
  49              	};
  50              	
  51              	/*******************************************************************************
  52              	 * Local function declarations
  53              	 */
  54              	static void fill_slave_tx_fifo( spi_instance_t * this_spi );
  55              	static void read_slave_rx_fifo( spi_instance_t * this_spi );
  56              	static void recover_from_rx_overflow( const spi_instance_t * this_spi );
  57              	
  58              	/*******************************************************************************
  59              	 * SPI_init()
  60              	 * See "core_spi.h" for details of how to use this function.
  61              	 */
  62              	void SPI_init
  63              	(
  64              	    spi_instance_t * this_spi,
  65              	    addr_t base_addr,
  66              	    uint16_t fifo_depth
  67              	)
  68              	{
  69              	    HAL_ASSERT( NULL_INSTANCE != this_spi );
  70 0028 73001000 	    HAL_ASSERT( NULL_ADDR != base_addr );
  71              	    HAL_ASSERT( SPI_MAX_FIFO_DEPTH  >= fifo_depth );
 203              		ebreak
 204              	# 0 "" 2
 205              	 #NO_APP
 206              	.L38:
 207 002c 93070002 		li	a5,32
 208 0030 63E42701 		bgtu	s2,a5,.L51
 209 0034 63140900 		bne	s2,zero,.L40
 210              	.L51:
 211              	 #APP
 212              	# 72 "../drivers/CoreSPI/core_spi.c" 1
  72 0038 73001000 	    HAL_ASSERT( SPI_MIN_FIFO_DEPTH  <= fifo_depth );
  73              	
 213              		ebreak
 214              	# 0 "" 2
 215              	 #NO_APP
 216              	.L40:
 217 003c 63040400 		beq	s0,zero,.L36
 218 0040 63920402 		bne	s1,zero,.L53
 219              	.L36:
 220 0044 8320C100 		lw	ra,12(sp)
 221 0048 03248100 		lw	s0,8(sp)
 222 004c 83244100 		lw	s1,4(sp)
 223 0050 03290100 		lw	s2,0(sp)
 224 0054 13010101 		addi	sp,sp,16
 225 0058 67800000 		jr	ra
 226              	.L52:
 227              	 #APP
 228              	# 69 "../drivers/CoreSPI/core_spi.c" 1
 229              		ebreak
 230              	# 0 "" 2
 231              	 #NO_APP
 232 0060 6FF05FFC 		j	.L37
 233              	.L53:
 234 0064 13068004 		li	a2,72
 235 0068 93050000 		li	a1,0
 236 006c 13054400 		addi	a0,s0,4
 237 0070 97000000 		call	memset
 237      E7800000 
 238 0078 9307F9FF 		addi	a5,s2,-1
 239 007c 93970701 		slli	a5,a5,16
 240 0080 23209400 		sw	s1,0(s0)
 241 0084 93D70701 		srli	a5,a5,16
 242 0088 1307F001 		li	a4,31
 243 008c 636AF708 		bgtu	a5,a4,.L54
 244              	.L42:
 245 0090 93060000 		li	a3,0
 246 0094 13061000 		li	a2,1
 247 0098 13850400 		mv	a0,s1
 248 009c 23122405 		sh	s2,68(s0)
 249 00a0 93050000 		li	a1,0
 250 00a4 97000000 		call	HW_set_8bit_reg_field
 250      E7800000 
 251 00ac 03250400 		lw	a0,0(s0)
 252 00b0 93050000 		li	a1,0
 253 00b4 13054502 		addi	a0,a0,36
 254 00b8 97000000 		call	HW_set_8bit_reg
 254      E7800000 
 255 00c0 03250400 		lw	a0,0(s0)
 256 00c4 93053000 		li	a1,3
 257 00c8 1305C501 		addi	a0,a0,28
 258 00cc 97000000 		call	HW_set_8bit_reg
 258      E7800000 
 259 00d4 03250400 		lw	a0,0(s0)
 260 00d8 9305F00F 		li	a1,255
 261 00dc 13054500 		addi	a0,a0,4
 262 00e0 97000000 		call	HW_set_8bit_reg
 262      E7800000 
 263 00e8 03250400 		lw	a0,0(s0)
 264 00ec 93050000 		li	a1,0
 265 00f0 13058501 		addi	a0,a0,24
 266 00f4 97000000 		call	HW_set_8bit_reg
 266      E7800000 
 267 00fc 03250400 		lw	a0,0(s0)
 268 0100 03248100 		lw	s0,8(sp)
 269 0104 8320C100 		lw	ra,12(sp)
 270 0108 83244100 		lw	s1,4(sp)
 271 010c 03290100 		lw	s2,0(sp)
 272 0110 93053000 		li	a1,3
 273 0114 13010101 		addi	sp,sp,16
 274 0118 17030000 		tail	HW_set_8bit_reg
 274      67000300 
 275              	.L54:
 276 0120 13091000 		li	s2,1
 277 0124 6FF0DFF6 		j	.L42
 279              		.section	.text.SPI_configure_slave_mode,"ax",@progbits
 280              		.align	2
 281              		.globl	SPI_configure_slave_mode
 283              	SPI_configure_slave_mode:
 284 0000 63040508 		beq	a0,zero,.L60
 285 0004 130101FF 		addi	sp,sp,-16
 286 0008 23248100 		sw	s0,8(sp)
 287 000c 13040500 		mv	s0,a0
 288 0010 03250500 		lw	a0,0(a0)
 289 0014 23261100 		sw	ra,12(sp)
 290 0018 93060000 		li	a3,0
 291 001c 13061000 		li	a2,1
 292 0020 93050000 		li	a1,0
 293 0024 23240404 		sw	zero,72(s0)
 294 0028 97000000 		call	HW_set_8bit_reg_field
 294      E7800000 
 295 0030 03250400 		lw	a0,0(s0)
 296 0034 93053000 		li	a1,3
 297 0038 1305C501 		addi	a0,a0,28
 298 003c 97000000 		call	HW_set_8bit_reg
 298      E7800000 
 299 0044 03250400 		lw	a0,0(s0)
 300 0048 9305F00F 		li	a1,255
 301 004c 13054500 		addi	a0,a0,4
 302 0050 97000000 		call	HW_set_8bit_reg
 302      E7800000 
 303 0058 03250400 		lw	a0,0(s0)
 304 005c 93050000 		li	a1,0
 305 0060 13058501 		addi	a0,a0,24
 306 0064 97000000 		call	HW_set_8bit_reg
 306      E7800000 
 307 006c 03250400 		lw	a0,0(s0)
 308 0070 03248100 		lw	s0,8(sp)
 309 0074 8320C100 		lw	ra,12(sp)
 310 0078 93051000 		li	a1,1
 311 007c 13010101 		addi	sp,sp,16
 312 0080 17030000 		tail	HW_set_8bit_reg
 312      67000300 
 313              	.L60:
 314              	 #APP
 315              	# 130 "../drivers/CoreSPI/core_spi.c" 1
  74              	    if( ( NULL_INSTANCE != this_spi ) && ( base_addr != NULL_ADDR ) )
  75              	    {
  76              	        /*
  77              	         * Initialize all transmit / receive buffers and handlers
  78              	         *
  79              	         * Relies on the fact that byte filling with 0x00 will equate
  80              	         * to 0 for any non byte sized items too.
  81              	         */
  82              	
  83              	        /* First fill struct with 0s */
  84              	        memset( this_spi, 0, sizeof(spi_instance_t) );
  85              	
  86              	        /* Configure CoreSPI instance attributes */
  87              	        this_spi->base_addr = (addr_t)base_addr;
  88              	
  89              	        /* Store FIFO depth or fall back to minimum if out of range */
  90              	        if( ( SPI_MAX_FIFO_DEPTH  >= fifo_depth ) && ( SPI_MIN_FIFO_DEPTH  <= fifo_depth ) )
  91              	        {
  92              	            this_spi->fifo_depth = fifo_depth;
  93              	        }
  94              	        else
  95              	        {
  96              	            this_spi->fifo_depth = SPI_MIN_FIFO_DEPTH;
  97              	        }
  98              	        /* Make sure the CoreSPI is disabled while we configure it */
  99              	        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 100              	
 101              	        /* Ensure all slaves are deselected */
 102              	        HAL_set_8bit_reg( this_spi->base_addr, SSEL, 0u );
 103              	
 104              	        /* Flush the receive and transmit FIFOs*/
 105              	        HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
 106              	
 107              	        /* Clear all interrupts */
 108              	        HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
 109              	
 110              	        /* Ensure RXAVAIL, TXRFM, SSEND and CMDINT are disabled */
 111              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL2, 0u );
 112              	        /*
 113              	         * Enable the CoreSPI in the reset default of master mode
 114              	         * with TXUNDERRUN, RXOVFLOW and TXDONE interrupts disabled.
 115              	         * The driver does not currently use interrupts in master mode.
 116              	         */
 117              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL1,  ENABLE | CTRL1_MASTER_MASK );
 118              	    }
 119              	}
 120              	
 121              	/***************************************************************************//**
 122              	 * SPI_configure_slave_mode()
 123              	 * See "core_spi.h" for details of how to use this function.
 124              	 */
 125              	void SPI_configure_slave_mode
 126              	(
 127              	    spi_instance_t * this_spi
 128              	)
 129              	{
 130 0088 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 131              	
 316              		ebreak
 317              	# 0 "" 2
 318              	 #NO_APP
 319 008c 67800000 		ret
 321              		.section	.text.SPI_configure_master_mode,"ax",@progbits
 322              		.align	2
 323              		.globl	SPI_configure_master_mode
 325              	SPI_configure_master_mode:
 326 0000 63040508 		beq	a0,zero,.L66
 327 0004 130101FF 		addi	sp,sp,-16
 328 0008 23248100 		sw	s0,8(sp)
 329 000c 13040500 		mv	s0,a0
 330 0010 03250500 		lw	a0,0(a0)
 331 0014 93060000 		li	a3,0
 332 0018 13061000 		li	a2,1
 333 001c 93050000 		li	a1,0
 334 0020 23261100 		sw	ra,12(sp)
 335 0024 97000000 		call	HW_set_8bit_reg_field
 335      E7800000 
 336 002c 03250400 		lw	a0,0(s0)
 337 0030 93053000 		li	a1,3
 338 0034 23240404 		sw	zero,72(s0)
 339 0038 1305C501 		addi	a0,a0,28
 340 003c 97000000 		call	HW_set_8bit_reg
 340      E7800000 
 341 0044 03250400 		lw	a0,0(s0)
 342 0048 9305F00F 		li	a1,255
 343 004c 13054500 		addi	a0,a0,4
 344 0050 97000000 		call	HW_set_8bit_reg
 344      E7800000 
 345 0058 03250400 		lw	a0,0(s0)
 346 005c 93050000 		li	a1,0
 347 0060 13058501 		addi	a0,a0,24
 348 0064 97000000 		call	HW_set_8bit_reg
 348      E7800000 
 349 006c 03250400 		lw	a0,0(s0)
 350 0070 03248100 		lw	s0,8(sp)
 351 0074 8320C100 		lw	ra,12(sp)
 352 0078 93053000 		li	a1,3
 353 007c 13010101 		addi	sp,sp,16
 354 0080 17030000 		tail	HW_set_8bit_reg
 354      67000300 
 355              	.L66:
 356              	 #APP
 357              	# 166 "../drivers/CoreSPI/core_spi.c" 1
 132              	    if( NULL_INSTANCE != this_spi )
 133              	        {
 134              	        /* Don't yet know what slave transfer mode will be used */
 135              	        this_spi->slave_xfer_mode = SPI_SLAVE_XFER_NONE;
 136              	
 137              	        /* Make sure the CoreSPI is disabled while we configure it */
 138              	        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 139              	
 140              	        /* Flush the receive and transmit FIFOs*/
 141              	        HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
 142              	
 143              	        /* Clear all interrupts */
 144              	        HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
 145              	
 146              	        /* Ensure RXAVAIL, TXRFM, SSEND and CMDINT are disabled */
 147              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL2, 0u );
 148              	        /*
 149              	         * Enable the CoreSPI in slave mode with TXUNDERRUN, RXOVFLOW and TXDONE
 150              	         * interrupts disabled. The appropriate interrupts will be enabled later
 151              	         * on when the transfer mode is configured.
 152              	         */
 153              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL1, ENABLE );
 154              	    }
 155              	}
 156              	
 157              	/***************************************************************************//**
 158              	 * SPI_configure_master_mode()
 159              	 * See "core_spi.h" for details of how to use this function.
 160              	 */
 161              	void SPI_configure_master_mode
 162              	(
 163              	    spi_instance_t * this_spi
 164              	)
 165              	{
 166 0088 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 167              	    
 358              		ebreak
 359              	# 0 "" 2
 360              	 #NO_APP
 361 008c 67800000 		ret
 363              		.section	.text.SPI_set_slave_select,"ax",@progbits
 364              		.align	2
 365              		.globl	SPI_set_slave_select
 367              	SPI_set_slave_select:
 368 0000 630C0504 		beq	a0,zero,.L82
 369 0004 93077000 		li	a5,7
 370 0008 63F6B700 		bleu	a1,a5,.L83
 371              	.L69:
 372              	 #APP
 373              	# 203 "../drivers/CoreSPI/core_spi.c" 1
 168              	    if( NULL_INSTANCE != this_spi )
 169              	    {
 170              	        /* Disable the CoreSPI for a little while, while we configure the CoreSPI */
 171              	        HAL_set_8bit_reg_field(this_spi->base_addr, CTRL1_ENABLE, DISABLE);
 172              	
 173              	        /* Reset slave transfer mode to unknown in case it has been set previously */
 174              	        this_spi->slave_xfer_mode = SPI_SLAVE_XFER_NONE;
 175              	
 176              	        /* Flush the receive and transmit FIFOs*/
 177              	        HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
 178              	
 179              	        /* Clear all interrupts */
 180              	        HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
 181              	
 182              	        /* Ensure RXAVAIL, TXRFM, SSEND and CMDINT are disabled */
 183              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL2, 0u );
 184              	
 185              	        /* Enable the CoreSPI in master mode with TXUNDERRUN, RXOVFLOW and TXDONE interrupts disabl
 186              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL1, ENABLE | CTRL1_MASTER_MASK );
 187              	    }
 188              	}
 189              	
 190              	/***************************************************************************//**
 191              	 * SPI_set_slave_select()
 192              	 * See "core_spi.h" for details of how to use this function.
 193              	 */
 194              	void SPI_set_slave_select
 195              	(
 196              	    spi_instance_t * this_spi,
 197              	    spi_slave_t slave
 198              	)
 199              	{
 200              	    spi_slave_t temp = (spi_slave_t)(0x00u) ;
 201              	
 202              	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 203 000c 73001000 	    HAL_ASSERT( SPI_MAX_NB_OF_SLAVES > slave );
 204              	    
 374              		ebreak
 375              	# 0 "" 2
 376              	 #NO_APP
 377 0010 67800000 		ret
 378              	.L83:
 379 0014 130101FF 		addi	sp,sp,-16
 380 0018 23248100 		sw	s0,8(sp)
 381 001c 13040500 		mv	s0,a0
 382 0020 03250500 		lw	a0,0(a0)
 383 0024 23229100 		sw	s1,4(sp)
 384 0028 13062000 		li	a2,2
 385 002c 93840500 		mv	s1,a1
 386 0030 93051000 		li	a1,1
 387 0034 23261100 		sw	ra,12(sp)
 388 0038 97000000 		call	HW_get_8bit_reg_field
 388      E7800000 
 389 0040 63140502 		bne	a0,zero,.L84
 390 0044 8320C100 		lw	ra,12(sp)
 391 0048 03248100 		lw	s0,8(sp)
 392 004c 83244100 		lw	s1,4(sp)
 393 0050 13010101 		addi	sp,sp,16
 394 0054 67800000 		jr	ra
 395              	.L82:
 396              	 #APP
 397              	# 202 "../drivers/CoreSPI/core_spi.c" 1
 398              		ebreak
 399              	# 0 "" 2
 400              	 #NO_APP
 401 005c 93077000 		li	a5,7
 402 0060 E3E6B7FA 		bgtu	a1,a5,.L69
 403 0064 67800000 		ret
 404              	.L84:
 405 0068 03250400 		lw	a0,0(s0)
 406 006c 13060001 		li	a2,16
 407 0070 93054000 		li	a1,4
 408 0074 13050502 		addi	a0,a0,32
 409 0078 97000000 		call	HW_get_8bit_reg_field
 409      E7800000 
 410 0080 93071000 		li	a5,1
 411 0084 6300F504 		beq	a0,a5,.L85
 412              	.L72:
 413 0088 03250400 		lw	a0,0(s0)
 414 008c 13054502 		addi	a0,a0,36
 415 0090 97000000 		call	HW_get_8bit_reg
 415      E7800000 
 416 0098 83270400 		lw	a5,0(s0)
 417 009c 93051000 		li	a1,1
 418 00a0 03248100 		lw	s0,8(sp)
 419 00a4 B3959500 		sll	a1,a1,s1
 420 00a8 8320C100 		lw	ra,12(sp)
 421 00ac 83244100 		lw	s1,4(sp)
 422 00b0 B3E5A500 		or	a1,a1,a0
 423 00b4 13854702 		addi	a0,a5,36
 424 00b8 13010101 		addi	sp,sp,16
 425 00bc 17030000 		tail	HW_set_8bit_reg
 425      67000300 
 426              	.L85:
 427 00c4 13050400 		mv	a0,s0
 428 00c8 97000000 		call	recover_from_rx_overflow.isra.0
 428      E7800000 
 429 00d0 6FF09FFB 		j	.L72
 431              		.section	.text.SPI_clear_slave_select,"ax",@progbits
 432              		.align	2
 433              		.globl	SPI_clear_slave_select
 435              	SPI_clear_slave_select:
 436 0000 630C0504 		beq	a0,zero,.L101
 437 0004 93077000 		li	a5,7
 438 0008 63F6B700 		bleu	a1,a5,.L102
 439              	.L88:
 440              	 #APP
 441              	# 235 "../drivers/CoreSPI/core_spi.c" 1
 205              	    if( ( NULL_INSTANCE != this_spi ) && ( SPI_MAX_NB_OF_SLAVES > slave ) )
 206              	    {
 207              	        /* This function is only intended to be used with an SPI master */
 208              	        if( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
 209              	        {
 210              	            /* Recover from receiver overflow because of previous slave */
 211              	            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW ) )
 212              	            {
 213              	                 recover_from_rx_overflow( this_spi );
 214              	            }
 215              	            /* Set the correct slave select bit */
 216              	            temp = (spi_slave_t)( HAL_get_8bit_reg( this_spi->base_addr, SSEL ) | ((uint32_t)1u << 
 217              	            HAL_set_8bit_reg( this_spi->base_addr, SSEL, (uint_fast8_t)temp );
 218              	        }
 219              	    }
 220              	}
 221              	
 222              	/***************************************************************************//**
 223              	 * SPI_clear_slave_select()
 224              	 * See "core_spi.h" for details of how to use this function.
 225              	 */
 226              	void SPI_clear_slave_select
 227              	(
 228              	    spi_instance_t * this_spi,
 229              	    spi_slave_t slave
 230              	)
 231              	{
 232              	    spi_slave_t temp = (spi_slave_t) (0x00u) ;
 233              	
 234              	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 235 000c 73001000 	    HAL_ASSERT( SPI_MAX_NB_OF_SLAVES > slave );
 236              	    
 442              		ebreak
 443              	# 0 "" 2
 444              	 #NO_APP
 445 0010 67800000 		ret
 446              	.L102:
 447 0014 130101FF 		addi	sp,sp,-16
 448 0018 23248100 		sw	s0,8(sp)
 449 001c 13040500 		mv	s0,a0
 450 0020 03250500 		lw	a0,0(a0)
 451 0024 23229100 		sw	s1,4(sp)
 452 0028 13062000 		li	a2,2
 453 002c 93840500 		mv	s1,a1
 454 0030 93051000 		li	a1,1
 455 0034 23261100 		sw	ra,12(sp)
 456 0038 97000000 		call	HW_get_8bit_reg_field
 456      E7800000 
 457 0040 63140502 		bne	a0,zero,.L103
 458 0044 8320C100 		lw	ra,12(sp)
 459 0048 03248100 		lw	s0,8(sp)
 460 004c 83244100 		lw	s1,4(sp)
 461 0050 13010101 		addi	sp,sp,16
 462 0054 67800000 		jr	ra
 463              	.L101:
 464              	 #APP
 465              	# 234 "../drivers/CoreSPI/core_spi.c" 1
 466              		ebreak
 467              	# 0 "" 2
 468              	 #NO_APP
 469 005c 93077000 		li	a5,7
 470 0060 E3E6B7FA 		bgtu	a1,a5,.L88
 471 0064 67800000 		ret
 472              	.L103:
 473 0068 03250400 		lw	a0,0(s0)
 474 006c 13060001 		li	a2,16
 475 0070 93054000 		li	a1,4
 476 0074 13050502 		addi	a0,a0,32
 477 0078 97000000 		call	HW_get_8bit_reg_field
 477      E7800000 
 478 0080 93071000 		li	a5,1
 479 0084 6302F504 		beq	a0,a5,.L104
 480              	.L91:
 481 0088 03250400 		lw	a0,0(s0)
 482 008c 13054502 		addi	a0,a0,36
 483 0090 97000000 		call	HW_get_8bit_reg
 483      E7800000 
 484 0098 83270400 		lw	a5,0(s0)
 485 009c 93051000 		li	a1,1
 486 00a0 03248100 		lw	s0,8(sp)
 487 00a4 B3959500 		sll	a1,a1,s1
 488 00a8 8320C100 		lw	ra,12(sp)
 489 00ac 83244100 		lw	s1,4(sp)
 490 00b0 93C5F5FF 		not	a1,a1
 491 00b4 B3F5A500 		and	a1,a1,a0
 492 00b8 13854702 		addi	a0,a5,36
 493 00bc 13010101 		addi	sp,sp,16
 494 00c0 17030000 		tail	HW_set_8bit_reg
 494      67000300 
 495              	.L104:
 496 00c8 13050400 		mv	a0,s0
 497 00cc 97000000 		call	recover_from_rx_overflow.isra.0
 497      E7800000 
 498 00d4 6FF05FFB 		j	.L91
 500              		.section	.text.SPI_transfer_frame,"ax",@progbits
 501              		.align	2
 502              		.globl	SPI_transfer_frame
 504              	SPI_transfer_frame:
 505 0000 130101FE 		addi	sp,sp,-32
 506 0004 232E1100 		sw	ra,28(sp)
 507 0008 232C8100 		sw	s0,24(sp)
 508 000c 232A9100 		sw	s1,20(sp)
 509 0010 23260100 		sw	zero,12(sp)
 510 0014 630E0502 		beq	a0,zero,.L113
 511 0018 13040500 		mv	s0,a0
 512 001c 03250500 		lw	a0,0(a0)
 513 0020 93840500 		mv	s1,a1
 514 0024 13062000 		li	a2,2
 515 0028 93051000 		li	a1,1
 516 002c 97000000 		call	HW_get_8bit_reg_field
 516      E7800000 
 517 0034 631C0502 		bne	a0,zero,.L109
 518 0038 8320C101 		lw	ra,28(sp)
 519 003c 03248101 		lw	s0,24(sp)
 520 0040 0325C100 		lw	a0,12(sp)
 521 0044 83244101 		lw	s1,20(sp)
 522 0048 13010102 		addi	sp,sp,32
 523 004c 67800000 		jr	ra
 524              	.L113:
 525              	 #APP
 526              	# 266 "../drivers/CoreSPI/core_spi.c" 1
 237              	    if( ( NULL_INSTANCE != this_spi ) && ( SPI_MAX_NB_OF_SLAVES > slave ) )
 238              	    {
 239              	        /* This function is only intended to be used with an SPI master. */
 240              	        if( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
 241              	        {
 242              	            /* Recover from receiver overflow because of previous slave */
 243              	            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW) )
 244              	            {
 245              	                 recover_from_rx_overflow( this_spi );
 246              	            }
 247              	            /* Clear the correct slave select bit */
 248              	            temp = (spi_slave_t)( HAL_get_8bit_reg( this_spi->base_addr, SSEL ) & ~((uint32_t)1u <<
 249              	            HAL_set_8bit_reg( this_spi->base_addr, SSEL, (uint_fast8_t)temp ) ;
 250              	        }
 251              	    }
 252              	}
 253              	
 254              	/***************************************************************************//**
 255              	 * SPI_transfer_frame()
 256              	 * See "core_spi.h" for details of how to use this function.
 257              	 */
 258              	uint32_t SPI_transfer_frame
 259              	(
 260              	    spi_instance_t * this_spi,
 261              	    uint32_t tx_bits
 262              	)
 263              	{
 264              	    volatile uint32_t rx_data = 0u; /* Ensure consistent return value if in slave mode */
 265              	
 266 0050 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 267              	
 527              		ebreak
 528              	# 0 "" 2
 529              	 #NO_APP
 530 0054 8320C101 		lw	ra,28(sp)
 531 0058 03248101 		lw	s0,24(sp)
 532 005c 0325C100 		lw	a0,12(sp)
 533 0060 83244101 		lw	s1,20(sp)
 534 0064 13010102 		addi	sp,sp,32
 535 0068 67800000 		jr	ra
 536              	.L109:
 537 006c 03250400 		lw	a0,0(s0)
 538 0070 93053000 		li	a1,3
 539 0074 1305C501 		addi	a0,a0,28
 540 0078 97000000 		call	HW_set_8bit_reg
 540      E7800000 
 541 0080 03250400 		lw	a0,0(s0)
 542 0084 93850400 		mv	a1,s1
 543 0088 13058502 		addi	a0,a0,40
 544 008c 97000000 		call	HW_set_32bit_reg
 544      E7800000 
 545              	.L108:
 546 0094 03250400 		lw	a0,0(s0)
 547 0098 13062000 		li	a2,2
 548 009c 93051000 		li	a1,1
 549 00a0 13050502 		addi	a0,a0,32
 550 00a4 97000000 		call	HW_get_8bit_reg_field
 550      E7800000 
 551 00ac 93071000 		li	a5,1
 552 00b0 E312F5FE 		bne	a0,a5,.L108
 553 00b4 03250400 		lw	a0,0(s0)
 554 00b8 13058500 		addi	a0,a0,8
 555 00bc 97000000 		call	HW_get_32bit_reg
 555      E7800000 
 556 00c4 8320C101 		lw	ra,28(sp)
 557 00c8 03248101 		lw	s0,24(sp)
 558 00cc 2326A100 		sw	a0,12(sp)
 559 00d0 0325C100 		lw	a0,12(sp)
 560 00d4 83244101 		lw	s1,20(sp)
 561 00d8 13010102 		addi	sp,sp,32
 562 00dc 67800000 		jr	ra
 564              		.section	.text.SPI_transfer_block,"ax",@progbits
 565              		.align	2
 566              		.globl	SPI_transfer_block
 568              	SPI_transfer_block:
 569 0000 63060508 		beq	a0,zero,.L163
 570 0004 130101FD 		addi	sp,sp,-48
 571 0008 23248102 		sw	s0,40(sp)
 572 000c 13040500 		mv	s0,a0
 573 0010 03250500 		lw	a0,0(a0)
 574 0014 232A5101 		sw	s5,20(sp)
 575 0018 23267101 		sw	s7,12(sp)
 576 001c 930A0600 		mv	s5,a2
 577 0020 938B0500 		mv	s7,a1
 578 0024 13062000 		li	a2,2
 579 0028 93051000 		li	a1,1
 580 002c 232E3101 		sw	s3,28(sp)
 581 0030 23286101 		sw	s6,16(sp)
 582 0034 23261102 		sw	ra,44(sp)
 583 0038 23229102 		sw	s1,36(sp)
 584 003c 23202103 		sw	s2,32(sp)
 585 0040 232C4101 		sw	s4,24(sp)
 586 0044 93090700 		mv	s3,a4
 587 0048 138B0600 		mv	s6,a3
 588 004c 97000000 		call	HW_get_8bit_reg_field
 588      E7800000 
 589 0054 63060500 		beq	a0,zero,.L114
 590 0058 33873A01 		add	a4,s5,s3
 591 005c 631C0702 		bne	a4,zero,.L164
 592              	.L114:
 593 0060 8320C102 		lw	ra,44(sp)
 594 0064 03248102 		lw	s0,40(sp)
 595 0068 83244102 		lw	s1,36(sp)
 596 006c 03290102 		lw	s2,32(sp)
 597 0070 8329C101 		lw	s3,28(sp)
 598 0074 032A8101 		lw	s4,24(sp)
 599 0078 832A4101 		lw	s5,20(sp)
 600 007c 032B0101 		lw	s6,16(sp)
 601 0080 832BC100 		lw	s7,12(sp)
 602 0084 13010103 		addi	sp,sp,48
 603 0088 67800000 		jr	ra
 604              	.L163:
 605              	 #APP
 606              	# 314 "../drivers/CoreSPI/core_spi.c" 1
 268              	    if( NULL_INSTANCE != this_spi )
 269              	    {
 270              	        /* This function is only intended to be used with an SPI master. */
 271              	        if( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
 272              	        {
 273              	            /* Flush the receive and transmit FIFOs by resetting both */
 274              	            HAL_set_8bit_reg(this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK);
 275              	
 276              	            /* Send frame. */
 277              	            HAL_set_32bit_reg( this_spi->base_addr, TXLAST, tx_bits );
 278              	
 279              	            /* Wait for frame Tx to complete. */
 280              	            while ( ENABLE != HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_DONE ) )
 281              	            {
 282              	                ;
 283              	            }
 284              	
 285              	            /* Read received frame. */
 286              	            rx_data = HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
 287              	        }
 288              	    }
 289              	
 290              	    /* Finally, return the frame we received from the slave or 0 */
 291              	    return( rx_data );
 292              	}
 293              	
 294              	
 295              	/***************************************************************************//**
 296              	 * SPI_transfer_block()
 297              	 * See "core_spi.h" for details of how to use this function.
 298              	 */
 299              	void SPI_transfer_block
 300              	(
 301              	    spi_instance_t * this_spi,
 302              	    const uint8_t * cmd_buffer,
 303              	    uint16_t cmd_byte_size,
 304              	    uint8_t * rx_buffer,
 305              	    uint16_t rx_byte_size
 306              	)
 307              	{
 308              	    uint32_t transfer_size = 0U;   /* Total number of bytes to  transfer. */
 309              	    uint16_t transfer_idx = 0U;    /* Number of bytes transferred so far */
 310              	    uint16_t tx_idx = 0u;          /* Number of valid data bytes sent */
 311              	    uint16_t rx_idx = 0u;          /* Number of valid response bytes received */
 312              	    uint16_t transit = 0U;         /* Number of bytes "in flight" to avoid FIFO errors */
 313              	
 314 008c 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 315              	
 607              		ebreak
 608              	# 0 "" 2
 609              	 #NO_APP
 610 0090 67800000 		ret
 611              	.L164:
 612 0094 03250400 		lw	a0,0(s0)
 613 0098 93053000 		li	a1,3
 614 009c 9309F7FF 		addi	s3,a4,-1
 615 00a0 1305C501 		addi	a0,a0,28
 616 00a4 97000000 		call	HW_set_8bit_reg
 616      E7800000 
 617 00ac 03250400 		lw	a0,0(s0)
 618 00b0 13060001 		li	a2,16
 619 00b4 93054000 		li	a1,4
 620 00b8 13050502 		addi	a0,a0,32
 621 00bc 97000000 		call	HW_get_8bit_reg_field
 621      E7800000 
 622 00c4 93071000 		li	a5,1
 623 00c8 6304F538 		beq	a0,a5,.L165
 624              	.L118:
 625 00cc 03250400 		lw	a0,0(s0)
 626 00d0 93060000 		li	a3,0
 627 00d4 13061000 		li	a2,1
 628 00d8 93050000 		li	a1,0
 629 00dc 97000000 		call	HW_set_8bit_reg_field
 629      E7800000 
 630 00e4 63860938 		beq	s3,zero,.L166
 631 00e8 83544404 		lhu	s1,68(s0)
 632 00ec 03250400 		lw	a0,0(s0)
 633 00f0 63880408 		beq	s1,zero,.L121
 634 00f4 93040000 		li	s1,0
 635 00f8 93070000 		li	a5,0
 636 00fc 6F000003 		j	.L125
 637              	.L167:
 638 0100 83450700 		lbu	a1,0(a4)
 639 0104 97000000 		call	HW_set_32bit_reg
 639      E7800000 
 640              	.L123:
 641 010c 93841400 		addi	s1,s1,1
 642 0110 93940401 		slli	s1,s1,16
 643 0114 93D40401 		srli	s1,s1,16
 644 0118 93870400 		mv	a5,s1
 645 011c 03250400 		lw	a0,0(s0)
 646 0120 63F63403 		bgeu	s1,s3,.L124
 647 0124 03574404 		lhu	a4,68(s0)
 648 0128 63FCE404 		bleu	a4,s1,.L121
 649              	.L125:
 650 012c 3387FB00 		add	a4,s7,a5
 651 0130 9307C500 		addi	a5,a0,12
 652 0134 93050000 		li	a1,0
 653 0138 13850700 		mv	a0,a5
 654 013c E3E254FD 		bgtu	s5,s1,.L167
 655 0140 97000000 		call	HW_set_32bit_reg
 655      E7800000 
 656 0148 6FF05FFC 		j	.L123
 657              	.L124:
 658 014c 639A3403 		bne	s1,s3,.L121
 659              	.L120:
 660 0150 83574404 		lhu	a5,68(s0)
 661 0154 63F6F402 		bleu	a5,s1,.L121
 662 0158 13058502 		addi	a0,a0,40
 663 015c 63F25431 		bgeu	s1,s5,.L126
 664 0160 B3873B01 		add	a5,s7,s3
 665 0164 83C50700 		lbu	a1,0(a5)
 666 0168 97000000 		call	HW_set_32bit_reg
 666      E7800000 
 667              	.L127:
 668 0170 93841400 		addi	s1,s1,1
 669 0174 03250400 		lw	a0,0(s0)
 670 0178 93940401 		slli	s1,s1,16
 671 017c 93D40401 		srli	s1,s1,16
 672              	.L121:
 673 0180 93061000 		li	a3,1
 674 0184 13061000 		li	a2,1
 675 0188 93050000 		li	a1,0
 676 018c 97000000 		call	HW_set_8bit_reg_field
 676      E7800000 
 677 0194 13890400 		mv	s2,s1
 678 0198 130A0000 		li	s4,0
 679              	.L162:
 680 019c 63F8540B 		bgeu	s1,s5,.L128
 681 01a0 03574404 		lhu	a4,68(s0)
 682 01a4 83270400 		lw	a5,0(s0)
 683 01a8 637CE902 		bleu	a4,s2,.L129
 684 01ac 33879B00 		add	a4,s7,s1
 685 01b0 1385C700 		addi	a0,a5,12
 686 01b4 83450700 		lbu	a1,0(a4)
 687 01b8 6382340D 		beq	s1,s3,.L168
 688 01bc 97000000 		call	HW_set_32bit_reg
 688      E7800000 
 689              	.L131:
 690 01c4 93841400 		addi	s1,s1,1
 691 01c8 13091900 		addi	s2,s2,1
 692 01cc 83270400 		lw	a5,0(s0)
 693 01d0 13190901 		slli	s2,s2,16
 694 01d4 93940401 		slli	s1,s1,16
 695 01d8 13590901 		srli	s2,s2,16
 696 01dc 93D40401 		srli	s1,s1,16
 697              	.L129:
 698 01e0 13064000 		li	a2,4
 699 01e4 93052000 		li	a1,2
 700 01e8 13850702 		addi	a0,a5,32
 701 01ec 97000000 		call	HW_get_8bit_reg_field
 701      E7800000 
 702 01f4 E31405FA 		bne	a0,zero,.L162
 703 01f8 03250400 		lw	a0,0(s0)
 704 01fc 130A1A00 		addi	s4,s4,1
 705 0200 1309F9FF 		addi	s2,s2,-1
 706 0204 13058500 		addi	a0,a0,8
 707 0208 131A0A01 		slli	s4,s4,16
 708 020c 13190901 		slli	s2,s2,16
 709 0210 97000000 		call	HW_get_32bit_reg
 709      E7800000 
 710 0218 135A0A01 		srli	s4,s4,16
 711 021c 13590901 		srli	s2,s2,16
 712 0220 6FF0DFF7 		j	.L162
 713              	.L170:
 714 0224 03250400 		lw	a0,0(s0)
 715 0228 130A1A00 		addi	s4,s4,1
 716 022c 1309F9FF 		addi	s2,s2,-1
 717 0230 13058500 		addi	a0,a0,8
 718 0234 131A0A01 		slli	s4,s4,16
 719 0238 13190901 		slli	s2,s2,16
 720 023c 97000000 		call	HW_get_32bit_reg
 720      E7800000 
 721 0244 135A0A01 		srli	s4,s4,16
 722 0248 13590901 		srli	s2,s2,16
 723              	.L128:
 724 024c 63785A07 		bleu	s5,s4,.L134
 725 0250 83574404 		lhu	a5,68(s0)
 726 0254 03250400 		lw	a0,0(s0)
 727 0258 6374F900 		bleu	a5,s2,.L135
 728 025c 63E83403 		bgtu	s3,s1,.L169
 729              	.L135:
 730 0260 13064000 		li	a2,4
 731 0264 93052000 		li	a1,2
 732 0268 13050502 		addi	a0,a0,32
 733 026c 97000000 		call	HW_get_8bit_reg_field
 733      E7800000 
 734 0274 E31C05FC 		bne	a0,zero,.L128
 735 0278 6FF0DFFA 		j	.L170
 736              	.L168:
 737 027c 13858702 		addi	a0,a5,40
 738 0280 97000000 		call	HW_set_32bit_reg
 738      E7800000 
 739 0288 6FF0DFF3 		j	.L131
 740              	.L169:
 741 028c 1305C500 		addi	a0,a0,12
 742 0290 93050000 		li	a1,0
 743 0294 93841400 		addi	s1,s1,1
 744 0298 13091900 		addi	s2,s2,1
 745 029c 97000000 		call	HW_set_32bit_reg
 745      E7800000 
 746 02a4 13190901 		slli	s2,s2,16
 747 02a8 93940401 		slli	s1,s1,16
 748 02ac 03250400 		lw	a0,0(s0)
 749 02b0 13590901 		srli	s2,s2,16
 750 02b4 93D40401 		srli	s1,s1,16
 751 02b8 6FF09FFA 		j	.L135
 752              	.L134:
 753 02bc 930A0000 		li	s5,0
 754              	.L138:
 755 02c0 63F2340B 		bgeu	s1,s3,.L142
 756 02c4 83574404 		lhu	a5,68(s0)
 757 02c8 03250400 		lw	a0,0(s0)
 758 02cc 6362F90C 		bgtu	a5,s2,.L171
 759              	.L139:
 760 02d0 13064000 		li	a2,4
 761 02d4 93052000 		li	a1,2
 762 02d8 13050502 		addi	a0,a0,32
 763 02dc 97000000 		call	HW_get_8bit_reg_field
 763      E7800000 
 764 02e4 E31E05FC 		bne	a0,zero,.L138
 765 02e8 03250400 		lw	a0,0(s0)
 766 02ec 130A1A00 		addi	s4,s4,1
 767 02f0 1309F9FF 		addi	s2,s2,-1
 768 02f4 13058500 		addi	a0,a0,8
 769 02f8 97000000 		call	HW_get_32bit_reg
 769      E7800000 
 770 0300 B3075B01 		add	a5,s6,s5
 771 0304 938A1A00 		addi	s5,s5,1
 772 0308 939A0A01 		slli	s5,s5,16
 773 030c 131A0A01 		slli	s4,s4,16
 774 0310 13190901 		slli	s2,s2,16
 775 0314 2380A700 		sb	a0,0(a5)
 776 0318 93DA0A01 		srli	s5,s5,16
 777 031c 135A0A01 		srli	s4,s4,16
 778 0320 13590901 		srli	s2,s2,16
 779 0324 6FF0DFF9 		j	.L138
 780              	.L174:
 781 0328 03250400 		lw	a0,0(s0)
 782 032c 130A1A00 		addi	s4,s4,1
 783 0330 1309F9FF 		addi	s2,s2,-1
 784 0334 13058500 		addi	a0,a0,8
 785 0338 97000000 		call	HW_get_32bit_reg
 785      E7800000 
 786 0340 B3075B01 		add	a5,s6,s5
 787 0344 938A1A00 		addi	s5,s5,1
 788 0348 939A0A01 		slli	s5,s5,16
 789 034c 131A0A01 		slli	s4,s4,16
 790 0350 13190901 		slli	s2,s2,16
 791 0354 2380A700 		sb	a0,0(a5)
 792 0358 93DA0A01 		srli	s5,s5,16
 793 035c 135A0A01 		srli	s4,s4,16
 794 0360 13590901 		srli	s2,s2,16
 795              	.L142:
 796 0364 63963409 		bne	s1,s3,.L172
 797 0368 83574404 		lhu	a5,68(s0)
 798 036c 03250400 		lw	a0,0(s0)
 799 0370 6368F904 		bgtu	a5,s2,.L173
 800              	.L143:
 801 0374 13064000 		li	a2,4
 802 0378 93052000 		li	a1,2
 803 037c 13050502 		addi	a0,a0,32
 804 0380 97000000 		call	HW_get_8bit_reg_field
 804      E7800000 
 805 0388 E31E05FC 		bne	a0,zero,.L142
 806 038c 6FF0DFF9 		j	.L174
 807              	.L171:
 808 0390 1305C500 		addi	a0,a0,12
 809 0394 93050000 		li	a1,0
 810 0398 93841400 		addi	s1,s1,1
 811 039c 13091900 		addi	s2,s2,1
 812 03a0 97000000 		call	HW_set_32bit_reg
 812      E7800000 
 813 03a8 13190901 		slli	s2,s2,16
 814 03ac 93940401 		slli	s1,s1,16
 815 03b0 03250400 		lw	a0,0(s0)
 816 03b4 13590901 		srli	s2,s2,16
 817 03b8 93D40401 		srli	s1,s1,16
 818 03bc 6FF05FF1 		j	.L139
 819              	.L173:
 820 03c0 13058502 		addi	a0,a0,40
 821 03c4 93050000 		li	a1,0
 822 03c8 93841400 		addi	s1,s1,1
 823 03cc 13091900 		addi	s2,s2,1
 824 03d0 97000000 		call	HW_set_32bit_reg
 824      E7800000 
 825 03d8 13190901 		slli	s2,s2,16
 826 03dc 93940401 		slli	s1,s1,16
 827 03e0 03250400 		lw	a0,0(s0)
 828 03e4 13590901 		srli	s2,s2,16
 829 03e8 93D40401 		srli	s1,s1,16
 830 03ec 6FF09FF8 		j	.L143
 831              	.L172:
 832 03f0 B38A4A41 		sub	s5,s5,s4
 833              	.L146:
 834 03f4 B3075A01 		add	a5,s4,s5
 835 03f8 93940701 		slli	s1,a5,16
 836 03fc 93D40401 		srli	s1,s1,16
 837 0400 6F008001 		j	.L147
 838              	.L148:
 839 0404 03250400 		lw	a0,0(s0)
 840 0408 13050502 		addi	a0,a0,32
 841 040c 97000000 		call	HW_get_8bit_reg_field
 841      E7800000 
 842 0414 630A0500 		beq	a0,zero,.L175
 843              	.L147:
 844 0418 13064000 		li	a2,4
 845 041c 93052000 		li	a1,2
 846 0420 E3F249FF 		bgeu	s3,s4,.L148
 847 0424 6FF0DFC3 		j	.L114
 848              	.L175:
 849 0428 03250400 		lw	a0,0(s0)
 850 042c 130A1A00 		addi	s4,s4,1
 851 0430 131A0A01 		slli	s4,s4,16
 852 0434 13058500 		addi	a0,a0,8
 853 0438 97000000 		call	HW_get_32bit_reg
 853      E7800000 
 854 0440 B3079B00 		add	a5,s6,s1
 855 0444 2380A700 		sb	a0,0(a5)
 856 0448 135A0A01 		srli	s4,s4,16
 857 044c 6FF09FFA 		j	.L146
 858              	.L165:
 859 0450 13050400 		mv	a0,s0
 860 0454 97000000 		call	recover_from_rx_overflow.isra.0
 860      E7800000 
 861 045c 6FF01FC7 		j	.L118
 862              	.L126:
 863 0460 93050000 		li	a1,0
 864 0464 97000000 		call	HW_set_32bit_reg
 864      E7800000 
 865 046c 6FF05FD0 		j	.L127
 866              	.L166:
 867 0470 03250400 		lw	a0,0(s0)
 868 0474 93040000 		li	s1,0
 869 0478 6FF09FCD 		j	.L120
 871              		.section	.text.SPI_transfer_block_store_all_resp,"ax",@progbits
 872              		.align	2
 873              		.globl	SPI_transfer_block_store_all_resp
 875              	SPI_transfer_block_store_all_resp:
 876 0000 630C0508 		beq	a0,zero,.L225
 877 0004 130101FD 		addi	sp,sp,-48
 878 0008 23248102 		sw	s0,40(sp)
 879 000c 13040500 		mv	s0,a0
 880 0010 03250500 		lw	a0,0(a0)
 881 0014 232A5101 		sw	s5,20(sp)
 882 0018 23267101 		sw	s7,12(sp)
 883 001c 930A0600 		mv	s5,a2
 884 0020 938B0500 		mv	s7,a1
 885 0024 13062000 		li	a2,2
 886 0028 93051000 		li	a1,1
 887 002c 232E3101 		sw	s3,28(sp)
 888 0030 23286101 		sw	s6,16(sp)
 889 0034 23248101 		sw	s8,8(sp)
 890 0038 23261102 		sw	ra,44(sp)
 891 003c 23229102 		sw	s1,36(sp)
 892 0040 23202103 		sw	s2,32(sp)
 893 0044 232C4101 		sw	s4,24(sp)
 894 0048 138C0700 		mv	s8,a5
 895 004c 93090700 		mv	s3,a4
 896 0050 138B0600 		mv	s6,a3
 897 0054 97000000 		call	HW_get_8bit_reg_field
 897      E7800000 
 898 005c 63060500 		beq	a0,zero,.L176
 899 0060 33873A01 		add	a4,s5,s3
 900 0064 631E0702 		bne	a4,zero,.L226
 901              	.L176:
 902 0068 8320C102 		lw	ra,44(sp)
 903 006c 03248102 		lw	s0,40(sp)
 904 0070 83244102 		lw	s1,36(sp)
 905 0074 03290102 		lw	s2,32(sp)
 906 0078 8329C101 		lw	s3,28(sp)
 907 007c 032A8101 		lw	s4,24(sp)
 908 0080 832A4101 		lw	s5,20(sp)
 909 0084 032B0101 		lw	s6,16(sp)
 910 0088 832BC100 		lw	s7,12(sp)
 911 008c 032C8100 		lw	s8,8(sp)
 912 0090 13010103 		addi	sp,sp,48
 913 0094 67800000 		jr	ra
 914              	.L225:
 915              	 #APP
 916              	# 516 "../drivers/CoreSPI/core_spi.c" 1
 316              	    if( NULL_INSTANCE != this_spi )
 317              	    {
 318              	        /* This function is only intended to be used with an SPI master. */
 319              	        if( ( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) ) &&
 320              	            /* Check for empty transfer as well */
 321              	            ( 0u != ( (uint32_t)cmd_byte_size + (uint32_t)rx_byte_size ) ) )
 322              	        {
 323              	            /*
 324              	             * tansfer_size is one less than the real amount as we have to write
 325              	             * the last frame separately to trigger the slave deselect in case
 326              	             * the SPS option is in place.
 327              	             */
 328              	            transfer_size = ( (uint32_t)cmd_byte_size + (uint32_t)rx_byte_size ) - 1u;
 329              	            /* Flush the receive and transmit FIFOs */
 330              	            HAL_set_8bit_reg(this_spi->base_addr, CMD, (uint32_t)(CMD_TXFIFORST_MASK | CMD_RXFIFORS
 331              	
 332              	            /* Recover from receiver overflow because of previous slave */
 333              	            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW) )
 334              	            {
 335              	                 recover_from_rx_overflow( this_spi );
 336              	            }
 337              	
 338              	            /* Disable the Core SPI for a little bit, while we load the TX FIFO */
 339              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 340              	
 341              	            while( ( tx_idx < transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
 342              	            {
 343              	                if( tx_idx < cmd_byte_size )
 344              	                {
 345              	                    /* Push out valid data */
 346              	                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)cmd_buffer[tx_idx] );
 347              	                }
 348              	                else
 349              	                {
 350              	                    /* Push out 0s to get data back from slave */
 351              	                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
 352              	                }
 353              	                ++transit;
 354              	                ++tx_idx;
 355              	            }
 356              	
 357              	            /* If room left to put last frame in before the off, then do it */
 358              	            if( ( tx_idx == transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
 359              	            {
 360              	                if( tx_idx < cmd_byte_size )
 361              	                {
 362              	                    /* Push out valid data, not expecting any reply this time */
 363              	                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, (uint32_t)cmd_buffer[tx_idx] );
 364              	                }
 365              	                else
 366              	                {
 367              	                    /* Push out last 0 to get data back from slave */
 368              	                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, 0U );
 369              	                }
 370              	
 371              	                ++transit;
 372              	                ++tx_idx;
 373              	            }
 374              	
 375              	            /* FIFO is all loaded up so enable Core SPI to start transfer */
 376              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 377              	
 378              	            /* Perform the remainder of the transfer by sending a byte every time a byte
 379              	             * has been received. This should ensure that no Rx overflow can happen in
 380              	             * case of an interrupt occurring during this function.
 381              	             *
 382              	             * We break the transfer down into stages to minimise the processing in
 383              	             * each loop as the SPI interface is very demanding at higher clock rates.
 384              	             * This works well with FIFOs but might be less efficient if there is only
 385              	             * a single frame buffer.
 386              	             *
 387              	             * First stage transfers remaining command bytes (if any).
 388              	             * At this stage anything in the RX FIFO can be discarded as it is
 389              	             * not part of a valid response.
 390              	             */
 391              	            while( tx_idx < cmd_byte_size )
 392              	            {
 393              	                if( transit < this_spi->fifo_depth )
 394              	                {
 395              	                    /* Send another byte. */
 396              	                    if( tx_idx == transfer_size ) /* Last frame is special... */
 397              	                    {
 398              	                        HAL_set_32bit_reg( this_spi->base_addr, TXLAST, (uint32_t)cmd_buffer[tx_idx
 399              	                    }
 400              	                    else
 401              	                    {
 402              	                        HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)cmd_buffer[tx_idx
 403              	                    }
 404              	                    ++tx_idx;
 405              	                    ++transit;
 406              	                }
 407              	                if( !HAL_get_8bit_reg_field( this_spi->base_addr, STATUS_RXEMPTY ) )
 408              	                {
 409              	                    /* Read and discard. */
 410              	                    HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
 411              	                    ++transfer_idx;
 412              	                    --transit;
 413              	                }
 414              	            }
 415              	            /*
 416              	             * Now, we are writing dummy bytes to push through the response from
 417              	             * the slave but we still have to keep discarding any read data that
 418              	             * corresponds with one of our command bytes.
 419              	             */
 420              	            while( transfer_idx < cmd_byte_size )
 421              	            {
 422              	                if( transit < this_spi->fifo_depth )
 423              	                {
 424              	                    if( tx_idx < transfer_size )
 425              	                    {
 426              	                        HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
 427              	                        ++tx_idx;
 428              	                        ++transit;
 429              	                    }
 430              	                }
 431              	                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
 432              	                {
 433              	                    /* Read and discard. */
 434              	                    HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
 435              	                    ++transfer_idx;
 436              	                    --transit;
 437              	                }
 438              	            }
 439              	            /*
 440              	             * Now we are now only sending dummy data to push through the
 441              	             * valid response data which we store in the response buffer.
 442              	             */
 443              	            while( tx_idx < transfer_size )
 444              	            {
 445              	                if( transit < this_spi->fifo_depth )
 446              	                {
 447              	                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
 448              	                    ++tx_idx;
 449              	                    ++transit;
 450              	                }
 451              	                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
 452              	                {
 453              	                    /* Process received byte. */
 454              	                    rx_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
 455              	                    ++rx_idx;
 456              	                    ++transfer_idx;
 457              	                    --transit;
 458              	                }
 459              	            }
 460              	            /* If we still need to send the last frame */
 461              	            while( tx_idx == transfer_size )
 462              	            {
 463              	                if( transit < this_spi->fifo_depth )
 464              	                {
 465              	                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, 0U );
 466              	                    ++tx_idx;
 467              	                    ++transit;
 468              	                }
 469              	                if( !HAL_get_8bit_reg_field( this_spi->base_addr, STATUS_RXEMPTY ) )
 470              	                {
 471              	                    /* Process received byte. */
 472              	                    rx_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
 473              	                    ++rx_idx;
 474              	                    ++transfer_idx;
 475              	                    --transit;
 476              	                }
 477              	            }
 478              	            /*
 479              	             * Finally, we are now finished sending data and are only reading
 480              	             * valid response data which we store in the response buffer.
 481              	             */
 482              	            while( transfer_idx <= transfer_size )
 483              	            {
 484              	                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
 485              	                {
 486              	                    /* Process received byte. */
 487              	                    rx_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
 488              	                    ++rx_idx;
 489              	                    ++transfer_idx;
 490              	                }
 491              	            }
 492              	        }
 493              	    }
 494              	}
 495              	
 496              	/***************************************************************************//**
 497              	 * SPI_transfer_block_store_all_resp()
 498              	 * See "core_spi.h" for details of how to use this function. 
 499              	 */
 500              	void SPI_transfer_block_store_all_resp
 501              	(
 502              	    spi_instance_t * this_spi,
 503              	    const uint8_t * cmd_buffer,
 504              	    uint16_t cmd_byte_size,
 505              	    uint8_t * rx_data_buffer,
 506              	    uint16_t rx_byte_size,
 507              	    uint8_t * cmd_response_buffer
 508              	)
 509              	{
 510              	    uint32_t transfer_size = 0U;   /* Total number of bytes to  transfer. */
 511              	    uint16_t transfer_idx = 0U;    /* Number of bytes transferred so far */
 512              	    uint16_t tx_idx = 0u;          /* Number of valid data bytes sent */
 513              	    uint16_t rx_idx = 0u;          /* Number of valid response bytes received */
 514              	    uint16_t transit = 0U;         /* Number of bytes "in flight" to avoid FIFO errors */
 515              	
 516 0098 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 517              	
 917              		ebreak
 918              	# 0 "" 2
 919              	 #NO_APP
 920 009c 67800000 		ret
 921              	.L226:
 922 00a0 03250400 		lw	a0,0(s0)
 923 00a4 93053000 		li	a1,3
 924 00a8 9309F7FF 		addi	s3,a4,-1
 925 00ac 1305C501 		addi	a0,a0,28
 926 00b0 97000000 		call	HW_set_8bit_reg
 926      E7800000 
 927 00b8 03250400 		lw	a0,0(s0)
 928 00bc 13060001 		li	a2,16
 929 00c0 93054000 		li	a1,4
 930 00c4 13050502 		addi	a0,a0,32
 931 00c8 97000000 		call	HW_get_8bit_reg_field
 931      E7800000 
 932 00d0 93071000 		li	a5,1
 933 00d4 630CF538 		beq	a0,a5,.L227
 934              	.L180:
 935 00d8 03250400 		lw	a0,0(s0)
 936 00dc 93060000 		li	a3,0
 937 00e0 13061000 		li	a2,1
 938 00e4 93050000 		li	a1,0
 939 00e8 97000000 		call	HW_set_8bit_reg_field
 939      E7800000 
 940 00f0 638E0938 		beq	s3,zero,.L228
 941 00f4 83544404 		lhu	s1,68(s0)
 942 00f8 03250400 		lw	a0,0(s0)
 943 00fc 63880408 		beq	s1,zero,.L183
 944 0100 93040000 		li	s1,0
 945 0104 93070000 		li	a5,0
 946 0108 6F000003 		j	.L187
 947              	.L229:
 948 010c 83C50700 		lbu	a1,0(a5)
 949 0110 97000000 		call	HW_set_32bit_reg
 949      E7800000 
 950              	.L185:
 951 0118 93841400 		addi	s1,s1,1
 952 011c 93940401 		slli	s1,s1,16
 953 0120 93D40401 		srli	s1,s1,16
 954 0124 93870400 		mv	a5,s1
 955 0128 03250400 		lw	a0,0(s0)
 956 012c 63F63403 		bgeu	s1,s3,.L186
 957 0130 03574404 		lhu	a4,68(s0)
 958 0134 63FCE404 		bleu	a4,s1,.L183
 959              	.L187:
 960 0138 1307C500 		addi	a4,a0,12
 961 013c B387FB00 		add	a5,s7,a5
 962 0140 93050000 		li	a1,0
 963 0144 13050700 		mv	a0,a4
 964 0148 E3E254FD 		bgtu	s5,s1,.L229
 965 014c 97000000 		call	HW_set_32bit_reg
 965      E7800000 
 966 0154 6FF05FFC 		j	.L185
 967              	.L186:
 968 0158 639A3403 		bne	s1,s3,.L183
 969              	.L182:
 970 015c 83574404 		lhu	a5,68(s0)
 971 0160 63F6F402 		bleu	a5,s1,.L183
 972 0164 13058502 		addi	a0,a0,40
 973 0168 63FA5431 		bgeu	s1,s5,.L188
 974 016c B3873B01 		add	a5,s7,s3
 975 0170 83C50700 		lbu	a1,0(a5)
 976 0174 97000000 		call	HW_set_32bit_reg
 976      E7800000 
 977              	.L189:
 978 017c 93841400 		addi	s1,s1,1
 979 0180 03250400 		lw	a0,0(s0)
 980 0184 93940401 		slli	s1,s1,16
 981 0188 93D40401 		srli	s1,s1,16
 982              	.L183:
 983 018c 93061000 		li	a3,1
 984 0190 13061000 		li	a2,1
 985 0194 93050000 		li	a1,0
 986 0198 97000000 		call	HW_set_8bit_reg_field
 986      E7800000 
 987 01a0 13890400 		mv	s2,s1
 988 01a4 130A0000 		li	s4,0
 989              	.L224:
 990 01a8 63F0540D 		bgeu	s1,s5,.L190
 991 01ac 03574404 		lhu	a4,68(s0)
 992 01b0 83270400 		lw	a5,0(s0)
 993 01b4 637CE902 		bleu	a4,s2,.L191
 994 01b8 33879B00 		add	a4,s7,s1
 995 01bc 1385C700 		addi	a0,a5,12
 996 01c0 83450700 		lbu	a1,0(a4)
 997 01c4 638A340D 		beq	s1,s3,.L230
 998 01c8 97000000 		call	HW_set_32bit_reg
 998      E7800000 
 999              	.L193:
 1000 01d0 93841400 		addi	s1,s1,1
 1001 01d4 13091900 		addi	s2,s2,1
 1002 01d8 83270400 		lw	a5,0(s0)
 1003 01dc 13190901 		slli	s2,s2,16
 1004 01e0 93940401 		slli	s1,s1,16
 1005 01e4 13590901 		srli	s2,s2,16
 1006 01e8 93D40401 		srli	s1,s1,16
 1007              	.L191:
 1008 01ec 13064000 		li	a2,4
 1009 01f0 93052000 		li	a1,2
 1010 01f4 13850702 		addi	a0,a5,32
 1011 01f8 97000000 		call	HW_get_8bit_reg_field
 1011      E7800000 
 1012 0200 E31405FA 		bne	a0,zero,.L224
 1013 0204 03250400 		lw	a0,0(s0)
 1014 0208 1309F9FF 		addi	s2,s2,-1
 1015 020c 13190901 		slli	s2,s2,16
 1016 0210 13058500 		addi	a0,a0,8
 1017 0214 97000000 		call	HW_get_32bit_reg
 1017      E7800000 
 1018 021c B3074C01 		add	a5,s8,s4
 1019 0220 130A1A00 		addi	s4,s4,1
 1020 0224 131A0A01 		slli	s4,s4,16
 1021 0228 2380A700 		sb	a0,0(a5)
 1022 022c 135A0A01 		srli	s4,s4,16
 1023 0230 13590901 		srli	s2,s2,16
 1024 0234 6FF05FF7 		j	.L224
 1025              	.L232:
 1026 0238 03250400 		lw	a0,0(s0)
 1027 023c 1309F9FF 		addi	s2,s2,-1
 1028 0240 13190901 		slli	s2,s2,16
 1029 0244 13058500 		addi	a0,a0,8
 1030 0248 97000000 		call	HW_get_32bit_reg
 1030      E7800000 
 1031 0250 B3074C01 		add	a5,s8,s4
 1032 0254 130A1A00 		addi	s4,s4,1
 1033 0258 131A0A01 		slli	s4,s4,16
 1034 025c 2380A700 		sb	a0,0(a5)
 1035 0260 135A0A01 		srli	s4,s4,16
 1036 0264 13590901 		srli	s2,s2,16
 1037              	.L190:
 1038 0268 63785A07 		bleu	s5,s4,.L196
 1039 026c 83574404 		lhu	a5,68(s0)
 1040 0270 03250400 		lw	a0,0(s0)
 1041 0274 6374F900 		bleu	a5,s2,.L197
 1042 0278 63E83403 		bgtu	s3,s1,.L231
 1043              	.L197:
 1044 027c 13064000 		li	a2,4
 1045 0280 93052000 		li	a1,2
 1046 0284 13050502 		addi	a0,a0,32
 1047 0288 97000000 		call	HW_get_8bit_reg_field
 1047      E7800000 
 1048 0290 E31C05FC 		bne	a0,zero,.L190
 1049 0294 6FF05FFA 		j	.L232
 1050              	.L230:
 1051 0298 13858702 		addi	a0,a5,40
 1052 029c 97000000 		call	HW_set_32bit_reg
 1052      E7800000 
 1053 02a4 6FF0DFF2 		j	.L193
 1054              	.L231:
 1055 02a8 1305C500 		addi	a0,a0,12
 1056 02ac 93050000 		li	a1,0
 1057 02b0 93841400 		addi	s1,s1,1
 1058 02b4 13091900 		addi	s2,s2,1
 1059 02b8 97000000 		call	HW_set_32bit_reg
 1059      E7800000 
 1060 02c0 13190901 		slli	s2,s2,16
 1061 02c4 93940401 		slli	s1,s1,16
 1062 02c8 03250400 		lw	a0,0(s0)
 1063 02cc 13590901 		srli	s2,s2,16
 1064 02d0 93D40401 		srli	s1,s1,16
 1065 02d4 6FF09FFA 		j	.L197
 1066              	.L196:
 1067 02d8 930A0000 		li	s5,0
 1068              	.L200:
 1069 02dc 63F2340B 		bgeu	s1,s3,.L204
 1070 02e0 83574404 		lhu	a5,68(s0)
 1071 02e4 03250400 		lw	a0,0(s0)
 1072 02e8 6362F90C 		bgtu	a5,s2,.L233
 1073              	.L201:
 1074 02ec 13064000 		li	a2,4
 1075 02f0 93052000 		li	a1,2
 1076 02f4 13050502 		addi	a0,a0,32
 1077 02f8 97000000 		call	HW_get_8bit_reg_field
 1077      E7800000 
 1078 0300 E31E05FC 		bne	a0,zero,.L200
 1079 0304 03250400 		lw	a0,0(s0)
 1080 0308 130A1A00 		addi	s4,s4,1
 1081 030c 1309F9FF 		addi	s2,s2,-1
 1082 0310 13058500 		addi	a0,a0,8
 1083 0314 97000000 		call	HW_get_32bit_reg
 1083      E7800000 
 1084 031c B3075B01 		add	a5,s6,s5
 1085 0320 938A1A00 		addi	s5,s5,1
 1086 0324 939A0A01 		slli	s5,s5,16
 1087 0328 131A0A01 		slli	s4,s4,16
 1088 032c 13190901 		slli	s2,s2,16
 1089 0330 2380A700 		sb	a0,0(a5)
 1090 0334 93DA0A01 		srli	s5,s5,16
 1091 0338 135A0A01 		srli	s4,s4,16
 1092 033c 13590901 		srli	s2,s2,16
 1093 0340 6FF0DFF9 		j	.L200
 1094              	.L236:
 1095 0344 03250400 		lw	a0,0(s0)
 1096 0348 130A1A00 		addi	s4,s4,1
 1097 034c 1309F9FF 		addi	s2,s2,-1
 1098 0350 13058500 		addi	a0,a0,8
 1099 0354 97000000 		call	HW_get_32bit_reg
 1099      E7800000 
 1100 035c B3075B01 		add	a5,s6,s5
 1101 0360 938A1A00 		addi	s5,s5,1
 1102 0364 939A0A01 		slli	s5,s5,16
 1103 0368 131A0A01 		slli	s4,s4,16
 1104 036c 13190901 		slli	s2,s2,16
 1105 0370 2380A700 		sb	a0,0(a5)
 1106 0374 93DA0A01 		srli	s5,s5,16
 1107 0378 135A0A01 		srli	s4,s4,16
 1108 037c 13590901 		srli	s2,s2,16
 1109              	.L204:
 1110 0380 63963409 		bne	s1,s3,.L234
 1111 0384 83574404 		lhu	a5,68(s0)
 1112 0388 03250400 		lw	a0,0(s0)
 1113 038c 6368F904 		bgtu	a5,s2,.L235
 1114              	.L205:
 1115 0390 13064000 		li	a2,4
 1116 0394 93052000 		li	a1,2
 1117 0398 13050502 		addi	a0,a0,32
 1118 039c 97000000 		call	HW_get_8bit_reg_field
 1118      E7800000 
 1119 03a4 E31E05FC 		bne	a0,zero,.L204
 1120 03a8 6FF0DFF9 		j	.L236
 1121              	.L233:
 1122 03ac 1305C500 		addi	a0,a0,12
 1123 03b0 93050000 		li	a1,0
 1124 03b4 93841400 		addi	s1,s1,1
 1125 03b8 13091900 		addi	s2,s2,1
 1126 03bc 97000000 		call	HW_set_32bit_reg
 1126      E7800000 
 1127 03c4 13190901 		slli	s2,s2,16
 1128 03c8 93940401 		slli	s1,s1,16
 1129 03cc 03250400 		lw	a0,0(s0)
 1130 03d0 13590901 		srli	s2,s2,16
 1131 03d4 93D40401 		srli	s1,s1,16
 1132 03d8 6FF05FF1 		j	.L201
 1133              	.L235:
 1134 03dc 13058502 		addi	a0,a0,40
 1135 03e0 93050000 		li	a1,0
 1136 03e4 93841400 		addi	s1,s1,1
 1137 03e8 13091900 		addi	s2,s2,1
 1138 03ec 97000000 		call	HW_set_32bit_reg
 1138      E7800000 
 1139 03f4 13190901 		slli	s2,s2,16
 1140 03f8 93940401 		slli	s1,s1,16
 1141 03fc 03250400 		lw	a0,0(s0)
 1142 0400 13590901 		srli	s2,s2,16
 1143 0404 93D40401 		srli	s1,s1,16
 1144 0408 6FF09FF8 		j	.L205
 1145              	.L234:
 1146 040c B38A4A41 		sub	s5,s5,s4
 1147              	.L208:
 1148 0410 B3075A01 		add	a5,s4,s5
 1149 0414 93940701 		slli	s1,a5,16
 1150 0418 93D40401 		srli	s1,s1,16
 1151 041c 6F008001 		j	.L209
 1152              	.L210:
 1153 0420 03250400 		lw	a0,0(s0)
 1154 0424 13050502 		addi	a0,a0,32
 1155 0428 97000000 		call	HW_get_8bit_reg_field
 1155      E7800000 
 1156 0430 630A0500 		beq	a0,zero,.L237
 1157              	.L209:
 1158 0434 13064000 		li	a2,4
 1159 0438 93052000 		li	a1,2
 1160 043c E3F249FF 		bgeu	s3,s4,.L210
 1161 0440 6FF09FC2 		j	.L176
 1162              	.L237:
 1163 0444 03250400 		lw	a0,0(s0)
 1164 0448 130A1A00 		addi	s4,s4,1
 1165 044c 131A0A01 		slli	s4,s4,16
 1166 0450 13058500 		addi	a0,a0,8
 1167 0454 97000000 		call	HW_get_32bit_reg
 1167      E7800000 
 1168 045c B3079B00 		add	a5,s6,s1
 1169 0460 2380A700 		sb	a0,0(a5)
 1170 0464 135A0A01 		srli	s4,s4,16
 1171 0468 6FF09FFA 		j	.L208
 1172              	.L227:
 1173 046c 13050400 		mv	a0,s0
 1174 0470 97000000 		call	recover_from_rx_overflow.isra.0
 1174      E7800000 
 1175 0478 6FF01FC6 		j	.L180
 1176              	.L188:
 1177 047c 93050000 		li	a1,0
 1178 0480 97000000 		call	HW_set_32bit_reg
 1178      E7800000 
 1179 0488 6FF05FCF 		j	.L189
 1180              	.L228:
 1181 048c 03250400 		lw	a0,0(s0)
 1182 0490 93040000 		li	s1,0
 1183 0494 6FF09FCC 		j	.L182
 1185              		.section	.text.SPI_set_frame_rx_handler,"ax",@progbits
 1186              		.align	2
 1187              		.globl	SPI_set_frame_rx_handler
 1189              	SPI_set_frame_rx_handler:
 1190 0000 63040504 		beq	a0,zero,.L246
 1191 0004 130101FF 		addi	sp,sp,-16
 1192 0008 23248100 		sw	s0,8(sp)
 1193 000c 13040500 		mv	s0,a0
 1194 0010 03250500 		lw	a0,0(a0)
 1195 0014 23229100 		sw	s1,4(sp)
 1196 0018 13062000 		li	a2,2
 1197 001c 93840500 		mv	s1,a1
 1198 0020 93051000 		li	a1,1
 1199 0024 23261100 		sw	ra,12(sp)
 1200 0028 97000000 		call	HW_get_8bit_reg_field
 1200      E7800000 
 1201 0030 63000502 		beq	a0,zero,.L242
 1202 0034 8320C100 		lw	ra,12(sp)
 1203 0038 03248100 		lw	s0,8(sp)
 1204 003c 83244100 		lw	s1,4(sp)
 1205 0040 13010101 		addi	sp,sp,16
 1206 0044 67800000 		jr	ra
 1207              	.L246:
 1208              	 #APP
 1209              	# 706 "../drivers/CoreSPI/core_spi.c" 1
 518              	    if( NULL_INSTANCE != this_spi )
 519              	    {
 520              	        /* This function is only intended to be used with an SPI master. */
 521              	        if( ( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) ) &&
 522              	            /* Check for empty transfer as well */
 523              	            ( 0u != ( (uint32_t)cmd_byte_size + (uint32_t)rx_byte_size ) ) )
 524              	        {
 525              	            /*
 526              	             * tansfer_size is one less than the real amount as we have to write
 527              	             * the last frame separately to trigger the slave deselect in case
 528              	             * the SPS option is in place.
 529              	             */
 530              	            transfer_size = ( (uint32_t)cmd_byte_size + (uint32_t)rx_byte_size ) - 1u;
 531              	            /* Flush the receive and transmit FIFOs */
 532              	            HAL_set_8bit_reg(this_spi->base_addr, CMD, (uint32_t)(CMD_TXFIFORST_MASK | CMD_RXFIFORS
 533              	
 534              	            /* Recover from receiver overflow because of previous slave */
 535              	            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW) )
 536              	            {
 537              	                 recover_from_rx_overflow( this_spi );
 538              	            }
 539              	
 540              	            /* Disable the Core SPI for a little bit, while we load the TX FIFO */
 541              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 542              	
 543              	            while( ( tx_idx < transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
 544              	            {
 545              	                if( tx_idx < cmd_byte_size )
 546              	                {
 547              	                    /* Push out valid data */
 548              	                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)cmd_buffer[tx_idx] );
 549              	                }
 550              	                else
 551              	                {
 552              	                    /* Push out 0s to get data back from slave */
 553              	                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
 554              	                }
 555              	                ++transit;
 556              	                ++tx_idx;
 557              	            }
 558              	
 559              	            /* If room left to put last frame in before the off, then do it */
 560              	            if( ( tx_idx == transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
 561              	            {
 562              	                if( tx_idx < cmd_byte_size )
 563              	                {
 564              	                    /* Push out valid data, not expecting any reply this time */
 565              	                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, (uint32_t)cmd_buffer[tx_idx] );
 566              	                }
 567              	                else
 568              	                {
 569              	                    /* Push out last 0 to get data back from slave */
 570              	                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, 0U );
 571              	                }
 572              	
 573              	                ++transit;
 574              	                ++tx_idx;
 575              	            }
 576              	
 577              	            /* FIFO is all loaded up so enable Core SPI to start transfer */
 578              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 579              	
 580              	            /* Perform the remainder of the transfer by sending a byte every time a byte
 581              	             * has been received. This should ensure that no Rx overflow can happen in
 582              	             * case of an interrupt occurring during this function.
 583              	             *
 584              	             * We break the transfer down into stages to minimise the processing in
 585              	             * each loop as the SPI interface is very demanding at higher clock rates.
 586              	             * This works well with FIFOs but might be less efficient if there is only
 587              	             * a single frame buffer.
 588              	             *
 589              	             * First stage transfers remaining command bytes (if any).
 590              	             * At this stage anything in the RX FIFO can be discarded as it is
 591              	             * not part of a valid response.
 592              	             */
 593              	            while( tx_idx < cmd_byte_size )
 594              	            {
 595              	                if( transit < this_spi->fifo_depth )
 596              	                {
 597              	                    /* Send another byte. */
 598              	                    if( tx_idx == transfer_size ) /* Last frame is special... */
 599              	                    {
 600              	                        HAL_set_32bit_reg( this_spi->base_addr, TXLAST, (uint32_t)cmd_buffer[tx_idx
 601              	                    }
 602              	                    else
 603              	                    {
 604              	                        HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)cmd_buffer[tx_idx
 605              	                    }
 606              	                    ++tx_idx;
 607              	                    ++transit;
 608              	                }
 609              	                if( !HAL_get_8bit_reg_field( this_spi->base_addr, STATUS_RXEMPTY ) )
 610              	                {
 611              	                    /* Process received command byte. */
 612              	                    cmd_response_buffer[transfer_idx] = HAL_get_32bit_reg( this_spi->base_addr, RXD
 613              	                    ++transfer_idx;
 614              	                    --transit;
 615              	                }
 616              	            }
 617              	            /*
 618              	             * Now, we are writing dummy bytes to push through the response from
 619              	             * the slave, which we store in the command response buffer.
 620              	             */
 621              	            while( transfer_idx < cmd_byte_size )
 622              	            {
 623              	                if( transit < this_spi->fifo_depth )
 624              	                {
 625              	                    if( tx_idx < transfer_size )
 626              	                    {
 627              	                        HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
 628              	                        ++tx_idx;
 629              	                        ++transit;
 630              	                    }
 631              	                }
 632              	                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
 633              	                {
 634              	                    /* Process received command byte. */
 635              	                    cmd_response_buffer[transfer_idx] = HAL_get_32bit_reg( this_spi->base_addr, RXD
 636              	                    ++transfer_idx;
 637              	                    --transit;
 638              	                }
 639              	            }
 640              	            /*
 641              	             * Now we are now only sending dummy data to push through the
 642              	             * valid response data which we store in the data response buffer.
 643              	             */
 644              	            while( tx_idx < transfer_size )
 645              	            {
 646              	                if( transit < this_spi->fifo_depth )
 647              	                {
 648              	                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
 649              	                    ++tx_idx;
 650              	                    ++transit;
 651              	                }
 652              	                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
 653              	                {
 654              	                    /* Process received data byte. */
 655              	                    rx_data_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDAT
 656              	                    ++rx_idx;
 657              	                    ++transfer_idx;
 658              	                    --transit;
 659              	                }
 660              	            }
 661              	            /* If we still need to send the last frame */
 662              	            while( tx_idx == transfer_size )
 663              	            {
 664              	                if( transit < this_spi->fifo_depth )
 665              	                {
 666              	                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, 0U );
 667              	                    ++tx_idx;
 668              	                    ++transit;
 669              	                }
 670              	                if( !HAL_get_8bit_reg_field( this_spi->base_addr, STATUS_RXEMPTY ) )
 671              	                {
 672              	                    /* Process received data byte. */
 673              	                    rx_data_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDAT
 674              	                    ++rx_idx;
 675              	                    ++transfer_idx;
 676              	                    --transit;
 677              	                }
 678              	            }
 679              	            /*
 680              	             * Finally, we are now finished sending data and are only reading
 681              	             * valid response data which we store in the data response buffer.
 682              	             */
 683              	            while( transfer_idx <= transfer_size )
 684              	            {
 685              	                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
 686              	                {
 687              	                    /* Process received data byte. */
 688              	                    rx_data_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDAT
 689              	                    ++rx_idx;
 690              	                    ++transfer_idx;
 691              	                }
 692              	            }
 693              	        }
 694              	    }
 695              	}
 696              	/***************************************************************************//**
 697              	 * SPI_set_frame_rx_handler()
 698              	 * See "core_spi.h" for details of how to use this function.
 699              	 */
 700              	void SPI_set_frame_rx_handler
 701              	(
 702              	    spi_instance_t * this_spi,
 703              	    spi_frame_rx_handler_t rx_handler
 704              	)
 705              	{
 706 0048 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 707              	
 1210              		ebreak
 1211              	# 0 "" 2
 1212              	 #NO_APP
 1213 004c 67800000 		ret
 1214              	.L242:
 1215 0050 03250400 		lw	a0,0(s0)
 1216 0054 93060000 		li	a3,0
 1217 0058 13061000 		li	a2,1
 1218 005c 93050000 		li	a1,0
 1219 0060 97000000 		call	HW_set_8bit_reg_field
 1219      E7800000 
 1220 0068 03250400 		lw	a0,0(s0)
 1221 006c 9305F00F 		li	a1,255
 1222 0070 13054500 		addi	a0,a0,4
 1223 0074 97000000 		call	HW_set_8bit_reg
 1223      E7800000 
 1224 007c 03250400 		lw	a0,0(s0)
 1225 0080 93060000 		li	a3,0
 1226 0084 13060002 		li	a2,32
 1227 0088 93055000 		li	a1,5
 1228 008c 13058501 		addi	a0,a0,24
 1229 0090 97000000 		call	HW_set_8bit_reg_field
 1229      E7800000 
 1230 0098 03250400 		lw	a0,0(s0)
 1231 009c 93060000 		li	a3,0
 1232 00a0 13060001 		li	a2,16
 1233 00a4 93054000 		li	a1,4
 1234 00a8 13058501 		addi	a0,a0,24
 1235 00ac 97000000 		call	HW_set_8bit_reg_field
 1235      E7800000 
 1236 00b4 03278404 		lw	a4,72(s0)
 1237 00b8 23200404 		sw	zero,64(s0)
 1238 00bc 232A9402 		sw	s1,52(s0)
 1239 00c0 93072000 		li	a5,2
 1240 00c4 630EF700 		beq	a4,a5,.L241
 1241 00c8 03250400 		lw	a0,0(s0)
 1242 00cc 93060000 		li	a3,0
 1243 00d0 13068000 		li	a2,8
 1244 00d4 93053000 		li	a1,3
 1245 00d8 97000000 		call	HW_set_8bit_reg_field
 1245      E7800000 
 1246              	.L241:
 1247 00e0 03250400 		lw	a0,0(s0)
 1248 00e4 93053000 		li	a1,3
 1249 00e8 1305C501 		addi	a0,a0,28
 1250 00ec 97000000 		call	HW_set_8bit_reg
 1250      E7800000 
 1251 00f4 03250400 		lw	a0,0(s0)
 1252 00f8 93061000 		li	a3,1
 1253 00fc 13060001 		li	a2,16
 1254 0100 93054000 		li	a1,4
 1255 0104 97000000 		call	HW_set_8bit_reg_field
 1255      E7800000 
 1256 010c 03250400 		lw	a0,0(s0)
 1257 0110 93061000 		li	a3,1
 1258 0114 13060002 		li	a2,32
 1259 0118 93055000 		li	a1,5
 1260 011c 97000000 		call	HW_set_8bit_reg_field
 1260      E7800000 
 1261 0124 03250400 		lw	a0,0(s0)
 1262 0128 93061000 		li	a3,1
 1263 012c 13060004 		li	a2,64
 1264 0130 93056000 		li	a1,6
 1265 0134 13058501 		addi	a0,a0,24
 1266 0138 97000000 		call	HW_set_8bit_reg_field
 1266      E7800000 
 1267 0140 93072000 		li	a5,2
 1268 0144 03250400 		lw	a0,0(s0)
 1269 0148 2324F404 		sw	a5,72(s0)
 1270 014c 03248100 		lw	s0,8(sp)
 1271 0150 8320C100 		lw	ra,12(sp)
 1272 0154 83244100 		lw	s1,4(sp)
 1273 0158 93061000 		li	a3,1
 1274 015c 13061000 		li	a2,1
 1275 0160 93050000 		li	a1,0
 1276 0164 13010101 		addi	sp,sp,16
 1277 0168 17030000 		tail	HW_set_8bit_reg_field
 1277      67000300 
 1279              		.section	.text.SPI_set_slave_tx_frame,"ax",@progbits
 1280              		.align	2
 1281              		.globl	SPI_set_slave_tx_frame
 1283              	SPI_set_slave_tx_frame:
 1284 0000 630A0504 		beq	a0,zero,.L255
 1285 0004 130101FF 		addi	sp,sp,-16
 1286 0008 23248100 		sw	s0,8(sp)
 1287 000c 13040500 		mv	s0,a0
 1288 0010 03250500 		lw	a0,0(a0)
 1289 0014 23229100 		sw	s1,4(sp)
 1290 0018 23202101 		sw	s2,0(sp)
 1291 001c 93840500 		mv	s1,a1
 1292 0020 13090600 		mv	s2,a2
 1293 0024 93051000 		li	a1,1
 1294 0028 13062000 		li	a2,2
 1295 002c 23261100 		sw	ra,12(sp)
 1296 0030 97000000 		call	HW_get_8bit_reg_field
 1296      E7800000 
 1297 0038 63020502 		beq	a0,zero,.L251
 1298 003c 8320C100 		lw	ra,12(sp)
 1299 0040 03248100 		lw	s0,8(sp)
 1300 0044 83244100 		lw	s1,4(sp)
 1301 0048 03290100 		lw	s2,0(sp)
 1302 004c 13010101 		addi	sp,sp,16
 1303 0050 67800000 		jr	ra
 1304              	.L255:
 1305              	 #APP
 1306              	# 768 "../drivers/CoreSPI/core_spi.c" 1
 708              	    if(NULL_INSTANCE != this_spi)
 709              	    {
 710              	        /* This function is only intended to be used with an SPI slave. */
 711              	        if(DISABLE == HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER))
 712              	        {
 713              	            /* Disable the Core SPI while we configure */
 714              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 715              	
 716              	            /* Clear all interrupts */
 717              	            HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
 718              	
 719              	            /* Disable SSEND and CMD interrupts as we are not doing block transfers */
 720              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTSSEND, DISABLE );
 721              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTCMD,   DISABLE );
 722              	
 723              	            /* Disable block Rx handler as they are mutually exclusive. */
 724              	            this_spi->block_rx_handler = 0U;
 725              	
 726              	            /* Keep a copy of the pointer to the Rx handler function. */
 727              	            this_spi->frame_rx_handler = rx_handler;
 728              	
 729              	            if( SPI_SLAVE_XFER_FRAME != this_spi->slave_xfer_mode )
 730              	            {
 731              	                /*
 732              	                 * Either just coming from init or were previously in block mode
 733              	                 * so no tx frame handler is set at this point in time...
 734              	                 *
 735              	                 * Don't allow TXDONE interrupts.
 736              	                 */
 737              	                HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_INTTXDONE, DISABLE );
 738              	            }
 739              	
 740              	            /* Flush the receive and transmit FIFOs*/
 741              	            HAL_set_8bit_reg(this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK);
 742              	
 743              	            /* Enable Rx and FIFO error interrupts */
 744              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_INTRXOVFLOW, ENABLE );
 745              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_INTTXURUN,   ENABLE );
 746              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTRXDATA,   ENABLE );
 747              	
 748              	            /* Make sure correct mode is selected */
 749              	            this_spi->slave_xfer_mode = SPI_SLAVE_XFER_FRAME;
 750              	
 751              	            /* Finally re-enable the CoreSPI */
 752              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 753              	        }
 754              	    }
 755              	}
 756              	
 757              	/***************************************************************************//**
 758              	 * SPI_set_slave_tx_frame()
 759              	 * See "core_spi.h" for details of how to use this function.
 760              	 */
 761              	void SPI_set_slave_tx_frame
 762              	(
 763              	    spi_instance_t * this_spi,
 764              	    uint32_t frame_value,
 765              	    spi_slave_frame_tx_handler_t slave_tx_frame_handler
 766              	)
 767              	{
 768 0054 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 769              	
 1307              		ebreak
 1308              	# 0 "" 2
 1309              	 #NO_APP
 1310 0058 67800000 		ret
 1311              	.L251:
 1312 005c 03250400 		lw	a0,0(s0)
 1313 0060 93060000 		li	a3,0
 1314 0064 13061000 		li	a2,1
 1315 0068 93050000 		li	a1,0
 1316 006c 97000000 		call	HW_set_8bit_reg_field
 1316      E7800000 
 1317 0074 03250400 		lw	a0,0(s0)
 1318 0078 9305F00F 		li	a1,255
 1319 007c 13054500 		addi	a0,a0,4
 1320 0080 97000000 		call	HW_set_8bit_reg
 1320      E7800000 
 1321 0088 03250400 		lw	a0,0(s0)
 1322 008c 93060000 		li	a3,0
 1323 0090 13060002 		li	a2,32
 1324 0094 93055000 		li	a1,5
 1325 0098 13058501 		addi	a0,a0,24
 1326 009c 97000000 		call	HW_set_8bit_reg_field
 1326      E7800000 
 1327 00a4 03250400 		lw	a0,0(s0)
 1328 00a8 93060000 		li	a3,0
 1329 00ac 13060001 		li	a2,16
 1330 00b0 93054000 		li	a1,4
 1331 00b4 13058501 		addi	a0,a0,24
 1332 00b8 97000000 		call	HW_set_8bit_reg_field
 1332      E7800000 
 1333 00c0 03278404 		lw	a4,72(s0)
 1334 00c4 93072000 		li	a5,2
 1335 00c8 6300F702 		beq	a4,a5,.L250
 1336 00cc 03250400 		lw	a0,0(s0)
 1337 00d0 93060000 		li	a3,0
 1338 00d4 13060004 		li	a2,64
 1339 00d8 93056000 		li	a1,6
 1340 00dc 13058501 		addi	a0,a0,24
 1341 00e0 97000000 		call	HW_set_8bit_reg_field
 1341      E7800000 
 1342              	.L250:
 1343 00e8 03250400 		lw	a0,0(s0)
 1344 00ec 93053000 		li	a1,3
 1345 00f0 23240400 		sw	zero,8(s0)
 1346 00f4 1305C501 		addi	a0,a0,28
 1347 00f8 23260400 		sw	zero,12(s0)
 1348 00fc 23280400 		sw	zero,16(s0)
 1349 0100 97000000 		call	HW_set_8bit_reg
 1349      E7800000 
 1350 0108 03250400 		lw	a0,0(s0)
 1351 010c 93850400 		mv	a1,s1
 1352 0110 232E2403 		sw	s2,60(s0)
 1353 0114 232C9402 		sw	s1,56(s0)
 1354 0118 13058502 		addi	a0,a0,40
 1355 011c 97000000 		call	HW_set_32bit_reg
 1355      E7800000 
 1356 0124 03250400 		lw	a0,0(s0)
 1357 0128 93061000 		li	a3,1
 1358 012c 13068000 		li	a2,8
 1359 0130 93053000 		li	a1,3
 1360 0134 97000000 		call	HW_set_8bit_reg_field
 1360      E7800000 
 1361 013c 93072000 		li	a5,2
 1362 0140 03250400 		lw	a0,0(s0)
 1363 0144 2324F404 		sw	a5,72(s0)
 1364 0148 03248100 		lw	s0,8(sp)
 1365 014c 8320C100 		lw	ra,12(sp)
 1366 0150 83244100 		lw	s1,4(sp)
 1367 0154 03290100 		lw	s2,0(sp)
 1368 0158 93061000 		li	a3,1
 1369 015c 13061000 		li	a2,1
 1370 0160 93050000 		li	a1,0
 1371 0164 13010101 		addi	sp,sp,16
 1372 0168 17030000 		tail	HW_set_8bit_reg_field
 1372      67000300 
 1374              		.section	.text.SPI_set_slave_block_buffers,"ax",@progbits
 1375              		.align	2
 1376              		.globl	SPI_set_slave_block_buffers
 1378              	SPI_set_slave_block_buffers:
 1379 0000 630C0506 		beq	a0,zero,.L267
 1380 0004 130101FE 		addi	sp,sp,-32
 1381 0008 232C8100 		sw	s0,24(sp)
 1382 000c 13040500 		mv	s0,a0
 1383 0010 03250500 		lw	a0,0(a0)
 1384 0014 232A9100 		sw	s1,20(sp)
 1385 0018 23282101 		sw	s2,16(sp)
 1386 001c 93840500 		mv	s1,a1
 1387 0020 13090600 		mv	s2,a2
 1388 0024 93051000 		li	a1,1
 1389 0028 13062000 		li	a2,2
 1390 002c 23263101 		sw	s3,12(sp)
 1391 0030 23244101 		sw	s4,8(sp)
 1392 0034 23225101 		sw	s5,4(sp)
 1393 0038 232E1100 		sw	ra,28(sp)
 1394 003c 938A0700 		mv	s5,a5
 1395 0040 130A0700 		mv	s4,a4
 1396 0044 93890600 		mv	s3,a3
 1397 0048 97000000 		call	HW_get_8bit_reg_field
 1397      E7800000 
 1398 0050 63080502 		beq	a0,zero,.L263
 1399 0054 8320C101 		lw	ra,28(sp)
 1400 0058 03248101 		lw	s0,24(sp)
 1401 005c 83244101 		lw	s1,20(sp)
 1402 0060 03290101 		lw	s2,16(sp)
 1403 0064 8329C100 		lw	s3,12(sp)
 1404 0068 032A8100 		lw	s4,8(sp)
 1405 006c 832A4100 		lw	s5,4(sp)
 1406 0070 13010102 		addi	sp,sp,32
 1407 0074 67800000 		jr	ra
 1408              	.L267:
 1409              	 #APP
 1410              	# 841 "../drivers/CoreSPI/core_spi.c" 1
 770              	    if( NULL_INSTANCE != this_spi )
 771              	    {
 772              	        /* This function is only intended to be used with an SPI slave. */
 773              	        if( DISABLE == HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
 774              	        {
 775              	            /* Disable the Core SPI while we configure */
 776              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 777              	
 778              	            /* Clear all interrupts */
 779              	            HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
 780              	
 781              	            /* Disable SSEND and CMD interrupts as we are not doing block transfers */
 782              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTSSEND, DISABLE );
 783              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTCMD,   DISABLE );
 784              	
 785              	            if( SPI_SLAVE_XFER_FRAME != this_spi->slave_xfer_mode )
 786              	            {
 787              	                /*
 788              	                 * Either just coming from init or were previously in block mode
 789              	                 * so no rx frame handler is set at this point in time...
 790              	                 *
 791              	                 * Don't allow RXDATA interrupts.
 792              	                 */
 793              	                HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTRXDATA, DISABLE );
 794              	            }
 795              	
 796              	            /* Disable slave block tx buffer as it is mutually exclusive with frame
 797              	             * level handling. */
 798              	            this_spi->slave_tx_buffer = NULL_BUFF;
 799              	            this_spi->slave_tx_size = 0U;
 800              	            this_spi->slave_tx_idx = 0U;
 801              	
 802              	            /* Flush the receive and transmit FIFOs*/
 803              	            HAL_set_8bit_reg(this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK);
 804              	
 805              	            /* Assign the slave frame update handler - NULL_SLAVE_TX_UPDATE_HANDLER for none */
 806              	            this_spi->slave_tx_frame_handler = slave_tx_frame_handler;
 807              	
 808              	            /* Keep a copy of the slave Tx frame value. */
 809              	            this_spi->slave_tx_frame = frame_value;
 810              	
 811              	            /* Load one frame into Tx data register. */
 812              	            HAL_set_32bit_reg( this_spi->base_addr, TXLAST, this_spi->slave_tx_frame );
 813              	
 814              	            /* Enable Tx Done interrupt in order to reload the slave Tx frame after each
 815              	             * time it has been sent. */
 816              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_INTTXDONE, ENABLE );
 817              	
 818              	            /* Make sure correct mode is selected */
 819              	            this_spi->slave_xfer_mode = SPI_SLAVE_XFER_FRAME;
 820              	
 821              	            /* Ready to go so enable CoreSPI */
 822              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 823              	        }
 824              	    }
 825              	}
 826              	
 827              	/***************************************************************************//**
 828              	 * SPI_set_slave_block_buffers()
 829              	 * See "core_spi.h" for details of how to use this function.
 830              	 */
 831              	void SPI_set_slave_block_buffers
 832              	(
 833              	    spi_instance_t * this_spi,
 834              	    const uint8_t * tx_buffer,
 835              	    uint32_t tx_buff_size,
 836              	    uint8_t * rx_buffer,
 837              	    uint32_t rx_buff_size,
 838              	    spi_block_rx_handler_t block_rx_handler
 839              	)
 840              	{
 841 0078 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 842              	
 1411              		ebreak
 1412              	# 0 "" 2
 1413              	 #NO_APP
 1414 007c 67800000 		ret
 1415              	.L263:
 1416 0080 03250400 		lw	a0,0(s0)
 1417 0084 93060000 		li	a3,0
 1418 0088 13061000 		li	a2,1
 1419 008c 93050000 		li	a1,0
 1420 0090 97000000 		call	HW_set_8bit_reg_field
 1420      E7800000 
 1421 0098 03250400 		lw	a0,0(s0)
 1422 009c 93071000 		li	a5,1
 1423 00a0 2324F404 		sw	a5,72(s0)
 1424 00a4 1305C501 		addi	a0,a0,28
 1425 00a8 2322F402 		sw	a5,36(s0)
 1426 00ac 232A0402 		sw	zero,52(s0)
 1427 00b0 232E0402 		sw	zero,60(s0)
 1428 00b4 23205405 		sw	s5,64(s0)
 1429 00b8 23243403 		sw	s3,40(s0)
 1430 00bc 23264403 		sw	s4,44(s0)
 1431 00c0 23280402 		sw	zero,48(s0)
 1432 00c4 23249400 		sw	s1,8(s0)
 1433 00c8 23262401 		sw	s2,12(s0)
 1434 00cc 23280400 		sw	zero,16(s0)
 1435 00d0 93053000 		li	a1,3
 1436 00d4 97000000 		call	HW_set_8bit_reg
 1436      E7800000 
 1437 00dc 03250400 		lw	a0,0(s0)
 1438 00e0 9305F00F 		li	a1,255
 1439 00e4 13054500 		addi	a0,a0,4
 1440 00e8 97000000 		call	HW_set_8bit_reg
 1440      E7800000 
 1441 00f0 6F008003 		j	.L259
 1442              	.L260:
 1443 00f4 03270401 		lw	a4,16(s0)
 1444 00f8 8327C400 		lw	a5,12(s0)
 1445 00fc 03250400 		lw	a0,0(s0)
 1446 0100 6374F704 		bgeu	a4,a5,.L261
 1447 0104 83278400 		lw	a5,8(s0)
 1448 0108 1305C500 		addi	a0,a0,12
 1449 010c B387E700 		add	a5,a5,a4
 1450 0110 83C50700 		lbu	a1,0(a5)
 1451 0114 97000000 		call	HW_set_32bit_reg
 1451      E7800000 
 1452 011c 83270401 		lw	a5,16(s0)
 1453 0120 93871700 		addi	a5,a5,1
 1454 0124 2328F400 		sw	a5,16(s0)
 1455              	.L259:
 1456 0128 03250400 		lw	a0,0(s0)
 1457 012c 13068000 		li	a2,8
 1458 0130 93053000 		li	a1,3
 1459 0134 13050502 		addi	a0,a0,32
 1460 0138 97000000 		call	HW_get_8bit_reg_field
 1460      E7800000 
 1461 0140 E30A05FA 		beq	a0,zero,.L260
 1462 0144 03250400 		lw	a0,0(s0)
 1463              	.L261:
 1464 0148 93060000 		li	a3,0
 1465 014c 13060008 		li	a2,128
 1466 0150 93057000 		li	a1,7
 1467 0154 13058501 		addi	a0,a0,24
 1468 0158 97000000 		call	HW_set_8bit_reg_field
 1468      E7800000 
 1469 0160 03250400 		lw	a0,0(s0)
 1470 0164 93061000 		li	a3,1
 1471 0168 13060001 		li	a2,16
 1472 016c 93054000 		li	a1,4
 1473 0170 97000000 		call	HW_set_8bit_reg_field
 1473      E7800000 
 1474 0178 03250400 		lw	a0,0(s0)
 1475 017c 93061000 		li	a3,1
 1476 0180 13060002 		li	a2,32
 1477 0184 93055000 		li	a1,5
 1478 0188 97000000 		call	HW_set_8bit_reg_field
 1478      E7800000 
 1479 0190 03250400 		lw	a0,0(s0)
 1480 0194 93061000 		li	a3,1
 1481 0198 13060004 		li	a2,64
 1482 019c 93056000 		li	a1,6
 1483 01a0 13058501 		addi	a0,a0,24
 1484 01a4 97000000 		call	HW_set_8bit_reg_field
 1484      E7800000 
 1485 01ac 03250400 		lw	a0,0(s0)
 1486 01b0 93061000 		li	a3,1
 1487 01b4 13060002 		li	a2,32
 1488 01b8 93055000 		li	a1,5
 1489 01bc 13058501 		addi	a0,a0,24
 1490 01c0 97000000 		call	HW_set_8bit_reg_field
 1490      E7800000 
 1491 01c8 03250400 		lw	a0,0(s0)
 1492 01cc 93060000 		li	a3,0
 1493 01d0 13060001 		li	a2,16
 1494 01d4 93054000 		li	a1,4
 1495 01d8 13058501 		addi	a0,a0,24
 1496 01dc 97000000 		call	HW_set_8bit_reg_field
 1496      E7800000 
 1497 01e4 03250400 		lw	a0,0(s0)
 1498 01e8 03248101 		lw	s0,24(sp)
 1499 01ec 8320C101 		lw	ra,28(sp)
 1500 01f0 83244101 		lw	s1,20(sp)
 1501 01f4 03290101 		lw	s2,16(sp)
 1502 01f8 8329C100 		lw	s3,12(sp)
 1503 01fc 032A8100 		lw	s4,8(sp)
 1504 0200 832A4100 		lw	s5,4(sp)
 1505 0204 93061000 		li	a3,1
 1506 0208 13061000 		li	a2,1
 1507 020c 93050000 		li	a1,0
 1508 0210 13010102 		addi	sp,sp,32
 1509 0214 17030000 		tail	HW_set_8bit_reg_field
 1509      67000300 
 1511              		.section	.text.SPI_set_cmd_handler,"ax",@progbits
 1512              		.align	2
 1513              		.globl	SPI_set_cmd_handler
 1515              	SPI_set_cmd_handler:
 1516 0000 6302050C 		beq	a0,zero,.L280
 1517 0004 638C050A 		beq	a1,zero,.L281
 1518              	.L270:
 1519 0008 63160600 		bne	a2,zero,.L271
 1520              	 #APP
 1521              	# 925 "../drivers/CoreSPI/core_spi.c" 1
 843              	    if( NULL_INSTANCE != this_spi )
 844              	    {
 845              	        /* This function is only intended to be used with an SPI slave. */
 846              	        if( DISABLE == HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
 847              	        {
 848              	            /* Disable the Core SPI while we configure */
 849              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 850              	
 851              	            /* Make sure correct mode is selected */
 852              	            this_spi->slave_xfer_mode = SPI_SLAVE_XFER_BLOCK;
 853              	            /*
 854              	             * No command handler should be setup at this stage so fake this
 855              	             * to ensure 0 padding works.
 856              	             */
 857              	            this_spi->cmd_done = 1u;
 858              	
 859              	            /* Disable frame handlers as they are mutually exclusive with block Rx handler. */
 860              	            this_spi->frame_rx_handler = NULL_FRAME_HANDLER;
 861              	            this_spi->slave_tx_frame_handler = NULL_SLAVE_TX_UPDATE_HANDLER;
 862              	
 863              	            /* Keep a copy of the pointer to the block Rx handler function. */
 864              	            this_spi->block_rx_handler = block_rx_handler;
 865              	
 866              	            /* Assign slave receive buffer */
 867              	            this_spi->slave_rx_buffer = rx_buffer;
 868              	            this_spi->slave_rx_size = rx_buff_size;
 869              	            this_spi->slave_rx_idx = 0U;
 870              	
 871              	            /* Assign slave transmit buffer*/
 872              	            this_spi->slave_tx_buffer = tx_buffer;
 873              	            this_spi->slave_tx_size = tx_buff_size;
 874              	            this_spi->slave_tx_idx = 0U;
 875              	
 876              	            /* Flush the receive and transmit FIFOs */
 877              	            HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
 878              	
 879              	            /* Clear all interrupts */
 880              	            HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
 881              	
 882              	            /* Preload the transmit FIFO. */
 883              	            while( !(HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_TXFULL)) &&
 884              	                     ( this_spi->slave_tx_idx < this_spi->slave_tx_size ) )
 885              	            {
 886              	                HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)this_spi->slave_tx_buffer
 887              	                ++this_spi->slave_tx_idx;
 888              	            }
 889              	            /*
 890              	             * Disable TXDATA interrupt as we will look after transmission in rx handling
 891              	             * because we know that once we have read a frame it is safe to send another one.
 892              	             */
 893              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTTXDATA,  DISABLE );
 894              	
 895              	            /* Enable Rx, FIFO error  and SSEND interrupts */
 896              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_INTRXOVFLOW, ENABLE );
 897              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_INTTXURUN,   ENABLE );
 898              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTRXDATA,   ENABLE );
 899              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTSSEND,    ENABLE );
 900              	
 901              	            /* Disable command handler until it is set explicitly */
 902              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL2_INTCMD,      DISABLE );
 903              	
 904              	            /* Now enable the CoreSPI */
 905              	            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 906              	        }
 907              	    }
 908              	}
 909              	
 910              	/***************************************************************************//**
 911              	 * SPI_set_cmd_handler()
 912              	 * See "core_spi.h" for details of how to use this function.
 913              	 */
 914              	void SPI_set_cmd_handler
 915              	(
 916              	    spi_instance_t * this_spi,
 917              	    spi_block_rx_handler_t cmd_handler,
 918              	    uint32_t cmd_size
 919              	)
 920              	{
 921              	    uint32_t ctrl2 = 0u;
 922              	
 923              	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 924              	    HAL_ASSERT( NULL_SLAVE_CMD_HANDLER != cmd_handler );
 925 000c 73001000 	    HAL_ASSERT( 0u < cmd_size );
 926              	
 1522              		ebreak
 1523              	# 0 "" 2
 1524              	 #NO_APP
 1525 0010 67800000 		ret
 1526              	.L271:
 1527 0014 6302050A 		beq	a0,zero,.L268
 1528 0018 6380050A 		beq	a1,zero,.L268
 1529 001c 130101FF 		addi	sp,sp,-16
 1530 0020 23248100 		sw	s0,8(sp)
 1531 0024 13040500 		mv	s0,a0
 1532 0028 03250500 		lw	a0,0(a0)
 1533 002c 23229100 		sw	s1,4(sp)
 1534 0030 23202101 		sw	s2,0(sp)
 1535 0034 93060000 		li	a3,0
 1536 0038 93040600 		mv	s1,a2
 1537 003c 13890500 		mv	s2,a1
 1538 0040 13061000 		li	a2,1
 1539 0044 93050000 		li	a1,0
 1540 0048 23261100 		sw	ra,12(sp)
 1541 004c 97000000 		call	HW_set_8bit_reg_field
 1541      E7800000 
 1542 0054 03250400 		lw	a0,0(s0)
 1543 0058 23202403 		sw	s2,32(s0)
 1544 005c 23220402 		sw	zero,36(s0)
 1545 0060 13058501 		addi	a0,a0,24
 1546 0064 97000000 		call	HW_get_8bit_reg
 1546      E7800000 
 1547 006c 83270400 		lw	a5,0(s0)
 1548 0070 137585FF 		andi	a0,a0,-8
 1549 0074 13F67400 		andi	a2,s1,7
 1550 0078 3366A600 		or	a2,a2,a0
 1551 007c 93650605 		ori	a1,a2,80
 1552 0080 13858701 		addi	a0,a5,24
 1553 0084 97000000 		call	HW_set_8bit_reg
 1553      E7800000 
 1554 008c 03250400 		lw	a0,0(s0)
 1555 0090 03248100 		lw	s0,8(sp)
 1556 0094 8320C100 		lw	ra,12(sp)
 1557 0098 83244100 		lw	s1,4(sp)
 1558 009c 03290100 		lw	s2,0(sp)
 1559 00a0 93061000 		li	a3,1
 1560 00a4 13061000 		li	a2,1
 1561 00a8 93050000 		li	a1,0
 1562 00ac 13010101 		addi	sp,sp,16
 1563 00b0 17030000 		tail	HW_set_8bit_reg_field
 1563      67000300 
 1564              	.L268:
 1565 00b8 67800000 		ret
 1566              	.L281:
 1567              	 #APP
 1568              	# 924 "../drivers/CoreSPI/core_spi.c" 1
 1569              		ebreak
 1570              	# 0 "" 2
 1571              	 #NO_APP
 1572 00c0 6FF09FF4 		j	.L270
 1573              	.L280:
 1574              	 #APP
 1575              	# 923 "../drivers/CoreSPI/core_spi.c" 1
 1576              		ebreak
 1577              	# 0 "" 2
 1578              	 #NO_APP
 1579 00c8 E39005F4 		bne	a1,zero,.L270
 1580 00cc 6FF01FFF 		j	.L281
 1582              		.section	.text.SPI_set_cmd_response,"ax",@progbits
 1583              		.align	2
 1584              		.globl	SPI_set_cmd_response
 1586              	SPI_set_cmd_response:
 1587 0000 630E0502 		beq	a0,zero,.L291
 1588 0004 63880502 		beq	a1,zero,.L292
 1589              	.L284:
 1590 0008 63160600 		bne	a2,zero,.L285
 1591              	 #APP
 1592              	# 970 "../drivers/CoreSPI/core_spi.c" 1
 927              	    if( ( NULL_INSTANCE != this_spi ) && ( 0u < cmd_size ) &&
 928              	        ( NULL_SLAVE_CMD_HANDLER != cmd_handler ) )
 929              	    {
 930              	        /* Disable the Core SPI while we configure */
 931              	        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 932              	        /*
 933              	         * Note we don't flush the FIFOs as this has been done already when
 934              	         * block mode was configured.
 935              	         *
 936              	         * Clear this flag so zero padding is disabled until command response
 937              	         * has been taken care of.
 938              	         */
 939              	        this_spi->cmd_done = 0u;
 940              	
 941              	        /* Assign user handler for Command received interrupt */
 942              	        this_spi->cmd_handler = cmd_handler;
 943              	
 944              	        /* Configure the command size and Enable Command received interrupt */
 945              	        ctrl2  = HAL_get_8bit_reg( this_spi->base_addr, CTRL2 );
 946              	
 947              	        /* First clear the count field then insert count and int enables */
 948              	        ctrl2 &= ~(uint32_t)CTRL2_CMDSIZE_MASK;
 949              	        ctrl2 |= (uint32_t)((cmd_size & CTRL2_CMDSIZE_MASK) | CTRL2_INTCMD_MASK | CTRL2_INTRXDATA_M
 950              	        HAL_set_8bit_reg( this_spi->base_addr, CTRL2, ctrl2 );
 951              	
 952              	        /* Now enable the CoreSPI */
 953              	        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 954              	    }
 955              	}
 956              	
 957              	/***************************************************************************//**
 958              	 * SPI_set_cmd_response()
 959              	 * See "core_spi.h" for details of how to use this function.
 960              	 */
 961              	void SPI_set_cmd_response
 962              	(
 963              	    spi_instance_t * this_spi,
 964              	    const uint8_t * resp_tx_buffer,
 965              	    uint32_t resp_buff_size
 966              	)
 967              	{
 968              	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 969              	    HAL_ASSERT( NULL_BUFF != resp_tx_buffer );
 970 000c 73001000 	    HAL_ASSERT( 0u < resp_buff_size );
 971              	
 1593              		ebreak
 1594              	# 0 "" 2
 1595              	 #NO_APP
 1596 0010 67800000 		ret
 1597              	.L285:
 1598 0014 630E0500 		beq	a0,zero,.L282
 1599 0018 638C0500 		beq	a1,zero,.L282
 1600 001c 232AB500 		sw	a1,20(a0)
 1601 0020 232CC500 		sw	a2,24(a0)
 1602 0024 232E0500 		sw	zero,28(a0)
 1603 0028 17030000 		tail	fill_slave_tx_fifo
 1603      67000300 
 1604              	.L282:
 1605 0030 67800000 		ret
 1606              	.L292:
 1607              	 #APP
 1608              	# 969 "../drivers/CoreSPI/core_spi.c" 1
 1609              		ebreak
 1610              	# 0 "" 2
 1611              	 #NO_APP
 1612 0038 6FF01FFD 		j	.L284
 1613              	.L291:
 1614              	 #APP
 1615              	# 968 "../drivers/CoreSPI/core_spi.c" 1
 1616              		ebreak
 1617              	# 0 "" 2
 1618              	 #NO_APP
 1619 0040 E39405FC 		bne	a1,zero,.L284
 1620 0044 6FF01FFF 		j	.L292
 1622              		.section	.text.SPI_enable,"ax",@progbits
 1623              		.align	2
 1624              		.globl	SPI_enable
 1626              	SPI_enable:
 1627 0000 630E0500 		beq	a0,zero,.L296
 1628 0004 03250500 		lw	a0,0(a0)
 1629 0008 93061000 		li	a3,1
 1630 000c 13061000 		li	a2,1
 1631 0010 93050000 		li	a1,0
 1632 0014 17030000 		tail	HW_set_8bit_reg_field
 1632      67000300 
 1633              	.L296:
 1634              	 #APP
 1635              	# 993 "../drivers/CoreSPI/core_spi.c" 1
 972              	    if( ( NULL_INSTANCE != this_spi ) && ( 0u < resp_buff_size ) &&
 973              	        ( NULL_BUFF != resp_tx_buffer ) )
 974              	    {
 975              	        this_spi->resp_tx_buffer = resp_tx_buffer;
 976              	        this_spi->resp_buff_size = resp_buff_size;
 977              	        this_spi->resp_buff_tx_idx = 0u;
 978              	
 979              	        fill_slave_tx_fifo(this_spi);
 980              	    }
 981              	}
 982              	
 983              	
 984              	/***************************************************************************//**
 985              	 * SPI_enable()
 986              	 * See "core_spi.h" for details of how to use this function.
 987              	 */
 988              	void SPI_enable
 989              	(
 990              	    spi_instance_t * this_spi
 991              	)
 992              	{
 993 001c 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 994              	
 1636              		ebreak
 1637              	# 0 "" 2
 1638              	 #NO_APP
 1639 0020 67800000 		ret
 1641              		.section	.text.SPI_disable,"ax",@progbits
 1642              		.align	2
 1643              		.globl	SPI_disable
 1645              	SPI_disable:
 1646 0000 630E0500 		beq	a0,zero,.L300
 1647 0004 03250500 		lw	a0,0(a0)
 1648 0008 93060000 		li	a3,0
 1649 000c 13061000 		li	a2,1
 1650 0010 93050000 		li	a1,0
 1651 0014 17030000 		tail	HW_set_8bit_reg_field
 1651      67000300 
 1652              	.L300:
 1653              	 #APP
 1654              	# 1012 "../drivers/CoreSPI/core_spi.c" 1
 995              	    if( NULL_INSTANCE != this_spi )
 996              	    {
 997              	        /* Disable the Core SPI while we configure */
 998              	        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
 999              	    }
 1000              	}
 1001              	
 1002              	
 1003              	/***************************************************************************//**
 1004              	 * SPI_disable()
 1005              	 * See "core_spi.h" for details of how to use this function.
 1006              	 */
 1007              	void SPI_disable
 1008              	(
 1009              	    spi_instance_t * this_spi
 1010              	)
 1011              	{
 1012 001c 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 1013              	
 1655              		ebreak
 1656              	# 0 "" 2
 1657              	 #NO_APP
 1658 0020 67800000 		ret
 1660              		.section	.text.SPI_isr,"ax",@progbits
 1661              		.align	2
 1662              		.globl	SPI_isr
 1664              	SPI_isr:
 1665 0000 6306050E 		beq	a0,zero,.L367
 1666 0004 130101FF 		addi	sp,sp,-16
 1667 0008 23248100 		sw	s0,8(sp)
 1668 000c 13040500 		mv	s0,a0
 1669 0010 03250500 		lw	a0,0(a0)
 1670 0014 13060004 		li	a2,64
 1671 0018 93056000 		li	a1,6
 1672 001c 13050501 		addi	a0,a0,16
 1673 0020 23261100 		sw	ra,12(sp)
 1674 0024 23229100 		sw	s1,4(sp)
 1675 0028 97000000 		call	HW_get_8bit_reg_field
 1675      E7800000 
 1676 0030 93071000 		li	a5,1
 1677 0034 630AF50E 		beq	a0,a5,.L368
 1678 0038 03250400 		lw	a0,0(s0)
 1679 003c 13061000 		li	a2,1
 1680 0040 93050000 		li	a1,0
 1681 0044 13050501 		addi	a0,a0,16
 1682 0048 97000000 		call	HW_get_8bit_reg_field
 1682      E7800000 
 1683 0050 93071000 		li	a5,1
 1684 0054 6308F530 		beq	a0,a5,.L369
 1685              	.L325:
 1686 0058 03250400 		lw	a0,0(s0)
 1687 005c 13064000 		li	a2,4
 1688 0060 93052000 		li	a1,2
 1689 0064 13050501 		addi	a0,a0,16
 1690 0068 97000000 		call	HW_get_8bit_reg_field
 1690      E7800000 
 1691 0070 93071000 		li	a5,1
 1692 0074 6304F542 		beq	a0,a5,.L370
 1693              	.L329:
 1694 0078 03250400 		lw	a0,0(s0)
 1695 007c 13068000 		li	a2,8
 1696 0080 93053000 		li	a1,3
 1697 0084 13050501 		addi	a0,a0,16
 1698 0088 97000000 		call	HW_get_8bit_reg_field
 1698      E7800000 
 1699 0090 93071000 		li	a5,1
 1700 0094 630AF532 		beq	a0,a5,.L371
 1701              	.L330:
 1702 0098 03250400 		lw	a0,0(s0)
 1703 009c 13060001 		li	a2,16
 1704 00a0 93054000 		li	a1,4
 1705 00a4 13050501 		addi	a0,a0,16
 1706 00a8 97000000 		call	HW_get_8bit_reg_field
 1706      E7800000 
 1707 00b0 93071000 		li	a5,1
 1708 00b4 6302F536 		beq	a0,a5,.L372
 1709              	.L331:
 1710 00b8 03250400 		lw	a0,0(s0)
 1711 00bc 13060002 		li	a2,32
 1712 00c0 93055000 		li	a1,5
 1713 00c4 13050501 		addi	a0,a0,16
 1714 00c8 97000000 		call	HW_get_8bit_reg_field
 1714      E7800000 
 1715 00d0 93071000 		li	a5,1
 1716 00d4 6300F502 		beq	a0,a5,.L373
 1717              	.L301:
 1718 00d8 8320C100 		lw	ra,12(sp)
 1719 00dc 03248100 		lw	s0,8(sp)
 1720 00e0 83244100 		lw	s1,4(sp)
 1721 00e4 13010101 		addi	sp,sp,16
 1722 00e8 67800000 		jr	ra
 1723              	.L367:
 1724              	 #APP
 1725              	# 1037 "../drivers/CoreSPI/core_spi.c" 1
 1014              	    if( NULL_INSTANCE != this_spi )
 1015              	    {
 1016              	        /* Disable the Core SPI while we configure */
 1017              	        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
 1018              	    }
 1019              	}
 1020              	
 1021              	
 1022              	/***************************************************************************//**
 1023              	 * SPI interrupt service routine.
 1024              	 */
 1025              	void SPI_isr
 1026              	(
 1027              	    spi_instance_t * this_spi
 1028              	)
 1029              	{
 1030              	    uint32_t rx_frame;
 1031              	    int32_t  guard;
 1032              	
 1033              	/*
 1034              	 * The assert and the NULL check here can be commented out to reduce the interrupt
 1035              	 * latency once you are sure the interrupt vector code is correct.
 1036              	 */
 1037 00ec 73001000 	    HAL_ASSERT( NULL_INSTANCE != this_spi );
 1038              	    if( NULL_INSTANCE != this_spi )
 1726              		ebreak
 1727              	# 0 "" 2
 1728              	 #NO_APP
 1729 00f0 67800000 		ret
 1730              	.L373:
 1731 00f4 83278404 		lw	a5,72(s0)
 1732 00f8 6382A742 		beq	a5,a0,.L374
 1733              	.L333:
 1734 00fc 03250400 		lw	a0,0(s0)
 1735 0100 03248100 		lw	s0,8(sp)
 1736 0104 8320C100 		lw	ra,12(sp)
 1737 0108 83244100 		lw	s1,4(sp)
 1738 010c 93061000 		li	a3,1
 1739 0110 13060002 		li	a2,32
 1740 0114 93055000 		li	a1,5
 1741 0118 13054500 		addi	a0,a0,4
 1742 011c 13010101 		addi	sp,sp,16
 1743 0120 17030000 		tail	HW_set_8bit_reg_field
 1743      67000300 
 1744              	.L368:
 1745 0128 03278404 		lw	a4,72(s0)
 1746 012c 83270400 		lw	a5,0(s0)
 1747 0130 630AA70C 		beq	a4,a0,.L304
 1748 0134 93062000 		li	a3,2
 1749 0138 630ED704 		beq	a4,a3,.L323
 1750 013c 93051000 		li	a1,1
 1751 0140 1385C701 		addi	a0,a5,28
 1752 0144 97000000 		call	HW_set_8bit_reg
 1752      E7800000 
 1753              	.L365:
 1754 014c 03250400 		lw	a0,0(s0)
 1755              	.L312:
 1756 0150 93061000 		li	a3,1
 1757 0154 13060004 		li	a2,64
 1758 0158 93056000 		li	a1,6
 1759 015c 13054500 		addi	a0,a0,4
 1760 0160 97000000 		call	HW_set_8bit_reg_field
 1760      E7800000 
 1761 0168 03250400 		lw	a0,0(s0)
 1762 016c 13061000 		li	a2,1
 1763 0170 93050000 		li	a1,0
 1764 0174 13050501 		addi	a0,a0,16
 1765 0178 97000000 		call	HW_get_8bit_reg_field
 1765      E7800000 
 1766 0180 93071000 		li	a5,1
 1767 0184 E31AF5EC 		bne	a0,a5,.L325
 1768 0188 6F00C01D 		j	.L369
 1769              	.L322:
 1770 018c E7800700 		jalr	a5
 1771 0190 83270400 		lw	a5,0(s0)
 1772              	.L323:
 1773 0194 13064000 		li	a2,4
 1774 0198 93052000 		li	a1,2
 1775 019c 13850702 		addi	a0,a5,32
 1776 01a0 97000000 		call	HW_get_8bit_reg_field
 1776      E7800000 
 1777 01a8 E31205FA 		bne	a0,zero,.L365
 1778 01ac 03250400 		lw	a0,0(s0)
 1779 01b0 13058500 		addi	a0,a0,8
 1780 01b4 97000000 		call	HW_get_32bit_reg
 1780      E7800000 
 1781 01bc 83274403 		lw	a5,52(s0)
 1782 01c0 E39607FC 		bne	a5,zero,.L322
 1783 01c4 83270400 		lw	a5,0(s0)
 1784 01c8 6FF0DFFC 		j	.L323
 1785              	.L307:
 1786 01cc 03250400 		lw	a0,0(s0)
 1787 01d0 13058500 		addi	a0,a0,8
 1788 01d4 97000000 		call	HW_get_32bit_reg
 1788      E7800000 
 1789 01dc 03270403 		lw	a4,48(s0)
 1790 01e0 8327C402 		lw	a5,44(s0)
 1791 01e4 637AF700 		bgeu	a4,a5,.L306
 1792 01e8 83278402 		lw	a5,40(s0)
 1793 01ec 3387E700 		add	a4,a5,a4
 1794 01f0 2300A700 		sb	a0,0(a4)
 1795 01f4 03270403 		lw	a4,48(s0)
 1796              	.L306:
 1797 01f8 83270400 		lw	a5,0(s0)
 1798 01fc 13071700 		addi	a4,a4,1
 1799 0200 2328E402 		sw	a4,48(s0)
 1800              	.L304:
 1801 0204 13064000 		li	a2,4
 1802 0208 93052000 		li	a1,2
 1803 020c 13850702 		addi	a0,a5,32
 1804 0210 97000000 		call	HW_get_8bit_reg_field
 1804      E7800000 
 1805 0218 E30A05FA 		beq	a0,zero,.L307
 1806 021c 03270401 		lw	a4,16(s0)
 1807 0220 8327C400 		lw	a5,12(s0)
 1808 0224 636EF702 		bltu	a4,a5,.L308
 1809 0228 6F00003B 		j	.L366
 1810              	.L310:
 1811 022c 03270401 		lw	a4,16(s0)
 1812 0230 83278400 		lw	a5,8(s0)
 1813 0234 03250400 		lw	a0,0(s0)
 1814 0238 B387E700 		add	a5,a5,a4
 1815 023c 83C50700 		lbu	a1,0(a5)
 1816 0240 1305C500 		addi	a0,a0,12
 1817 0244 97000000 		call	HW_set_32bit_reg
 1817      E7800000 
 1818 024c 83270401 		lw	a5,16(s0)
 1819 0250 0327C400 		lw	a4,12(s0)
 1820 0254 93871700 		addi	a5,a5,1
 1821 0258 2328F400 		sw	a5,16(s0)
 1822 025c 63FEE736 		bgeu	a5,a4,.L366
 1823              	.L308:
 1824 0260 03250400 		lw	a0,0(s0)
 1825 0264 13068000 		li	a2,8
 1826 0268 93053000 		li	a1,3
 1827 026c 13050502 		addi	a0,a0,32
 1828 0270 97000000 		call	HW_get_8bit_reg_field
 1828      E7800000 
 1829 0278 E30A05FA 		beq	a0,zero,.L310
 1830 027c 83270400 		lw	a5,0(s0)
 1831 0280 83260401 		lw	a3,16(s0)
 1832 0284 0327C400 		lw	a4,12(s0)
 1833 0288 13850700 		mv	a0,a5
 1834 028c E3E2E6EC 		bltu	a3,a4,.L312
 1835              	.L311:
 1836 0290 8326C401 		lw	a3,28(s0)
 1837 0294 03278401 		lw	a4,24(s0)
 1838 0298 13850700 		mv	a0,a5
 1839 029c 63E0E604 		bltu	a3,a4,.L339
 1840 02a0 6F000034 		j	.L375
 1841              	.L315:
 1842 02a4 0327C401 		lw	a4,28(s0)
 1843 02a8 83274401 		lw	a5,20(s0)
 1844 02ac 03250400 		lw	a0,0(s0)
 1845 02b0 B387E700 		add	a5,a5,a4
 1846 02b4 83C50700 		lbu	a1,0(a5)
 1847 02b8 1305C500 		addi	a0,a0,12
 1848 02bc 97000000 		call	HW_set_32bit_reg
 1848      E7800000 
 1849 02c4 8327C401 		lw	a5,28(s0)
 1850 02c8 03278401 		lw	a4,24(s0)
 1851 02cc 93871700 		addi	a5,a5,1
 1852 02d0 232EF400 		sw	a5,28(s0)
 1853 02d4 63F0E702 		bgeu	a5,a4,.L316
 1854 02d8 03250400 		lw	a0,0(s0)
 1855              	.L339:
 1856 02dc 13068000 		li	a2,8
 1857 02e0 93053000 		li	a1,3
 1858 02e4 13050502 		addi	a0,a0,32
 1859 02e8 97000000 		call	HW_get_8bit_reg_field
 1859      E7800000 
 1860 02f0 E30A05FA 		beq	a0,zero,.L315
 1861              	.L316:
 1862 02f4 83274402 		lw	a5,36(s0)
 1863 02f8 03250400 		lw	a0,0(s0)
 1864 02fc E38A07E4 		beq	a5,zero,.L312
 1865 0300 03270401 		lw	a4,16(s0)
 1866 0304 8327C400 		lw	a5,12(s0)
 1867 0308 E364F7E4 		bltu	a4,a5,.L312
 1868 030c 0327C401 		lw	a4,28(s0)
 1869 0310 83278401 		lw	a5,24(s0)
 1870 0314 E36EF7E2 		bltu	a4,a5,.L312
 1871              	.L338:
 1872 0318 83544404 		lhu	s1,68(s0)
 1873 031c 93D42400 		srli	s1,s1,2
 1874 0320 93841400 		addi	s1,s1,1
 1875 0324 6F000002 		j	.L317
 1876              	.L318:
 1877 0328 03250400 		lw	a0,0(s0)
 1878 032c E38204E2 		beq	s1,zero,.L312
 1879 0330 1305C500 		addi	a0,a0,12
 1880 0334 97000000 		call	HW_set_32bit_reg
 1880      E7800000 
 1881 033c 03250400 		lw	a0,0(s0)
 1882 0340 9384F4FF 		addi	s1,s1,-1
 1883              	.L317:
 1884 0344 93053000 		li	a1,3
 1885 0348 13068000 		li	a2,8
 1886 034c 13050502 		addi	a0,a0,32
 1887 0350 97000000 		call	HW_get_8bit_reg_field
 1887      E7800000 
 1888 0358 93050000 		li	a1,0
 1889 035c E30605FC 		beq	a0,zero,.L318
 1890 0360 6FF0DFDE 		j	.L365
 1891              	.L369:
 1892 0364 83278404 		lw	a5,72(s0)
 1893 0368 13072000 		li	a4,2
 1894 036c 6382E718 		beq	a5,a4,.L376
 1895 0370 03270400 		lw	a4,0(s0)
 1896 0374 638CA700 		beq	a5,a0,.L328
 1897 0378 1305C701 		addi	a0,a4,28
 1898 037c 93052000 		li	a1,2
 1899 0380 97000000 		call	HW_set_8bit_reg
 1899      E7800000 
 1900 0388 03270400 		lw	a4,0(s0)
 1901              	.L328:
 1902 038c 13054700 		addi	a0,a4,4
 1903 0390 93061000 		li	a3,1
 1904 0394 13061000 		li	a2,1
 1905 0398 93050000 		li	a1,0
 1906 039c 97000000 		call	HW_set_8bit_reg_field
 1906      E7800000 
 1907 03a4 03250400 		lw	a0,0(s0)
 1908 03a8 13064000 		li	a2,4
 1909 03ac 93052000 		li	a1,2
 1910 03b0 13050501 		addi	a0,a0,16
 1911 03b4 97000000 		call	HW_get_8bit_reg_field
 1911      E7800000 
 1912 03bc 93071000 		li	a5,1
 1913 03c0 E31CF5CA 		bne	a0,a5,.L329
 1914 03c4 6F00800D 		j	.L370
 1915              	.L371:
 1916 03c8 03250400 		lw	a0,0(s0)
 1917 03cc 93052000 		li	a1,2
 1918 03d0 1305C501 		addi	a0,a0,28
 1919 03d4 97000000 		call	HW_set_8bit_reg
 1919      E7800000 
 1920 03dc 03250400 		lw	a0,0(s0)
 1921 03e0 93061000 		li	a3,1
 1922 03e4 13068000 		li	a2,8
 1923 03e8 93053000 		li	a1,3
 1924 03ec 13054500 		addi	a0,a0,4
 1925 03f0 97000000 		call	HW_set_8bit_reg_field
 1925      E7800000 
 1926 03f8 03250400 		lw	a0,0(s0)
 1927 03fc 13060001 		li	a2,16
 1928 0400 93054000 		li	a1,4
 1929 0404 13050501 		addi	a0,a0,16
 1930 0408 97000000 		call	HW_get_8bit_reg_field
 1930      E7800000 
 1931 0410 93071000 		li	a5,1
 1932 0414 E312F5CA 		bne	a0,a5,.L331
 1933              	.L372:
 1934 0418 13050400 		mv	a0,s0
 1935 041c 97000000 		call	read_slave_rx_fifo
 1935      E7800000 
 1936 0424 83270402 		lw	a5,32(s0)
 1937 0428 63880700 		beq	a5,zero,.L332
 1938 042c 83250403 		lw	a1,48(s0)
 1939 0430 03258402 		lw	a0,40(s0)
 1940 0434 E7800700 		jalr	a5
 1941              	.L332:
 1942 0438 03250400 		lw	a0,0(s0)
 1943 043c 93071000 		li	a5,1
 1944 0440 2322F402 		sw	a5,36(s0)
 1945 0444 93060000 		li	a3,0
 1946 0448 13060001 		li	a2,16
 1947 044c 93054000 		li	a1,4
 1948 0450 13058501 		addi	a0,a0,24
 1949 0454 97000000 		call	HW_set_8bit_reg_field
 1949      E7800000 
 1950 045c 03250400 		lw	a0,0(s0)
 1951 0460 93061000 		li	a3,1
 1952 0464 13060001 		li	a2,16
 1953 0468 93054000 		li	a1,4
 1954 046c 13054500 		addi	a0,a0,4
 1955 0470 97000000 		call	HW_set_8bit_reg_field
 1955      E7800000 
 1956 0478 03250400 		lw	a0,0(s0)
 1957 047c 13060002 		li	a2,32
 1958 0480 93055000 		li	a1,5
 1959 0484 13050501 		addi	a0,a0,16
 1960 0488 97000000 		call	HW_get_8bit_reg_field
 1960      E7800000 
 1961 0490 93071000 		li	a5,1
 1962 0494 E312F5C4 		bne	a0,a5,.L301
 1963 0498 6FF0DFC5 		j	.L373
 1964              	.L370:
 1965 049c 03250400 		lw	a0,0(s0)
 1966 04a0 93051000 		li	a1,1
 1967 04a4 1305C501 		addi	a0,a0,28
 1968 04a8 97000000 		call	HW_set_8bit_reg
 1968      E7800000 
 1969 04b0 03250400 		lw	a0,0(s0)
 1970 04b4 93061000 		li	a3,1
 1971 04b8 13064000 		li	a2,4
 1972 04bc 93052000 		li	a1,2
 1973 04c0 13054500 		addi	a0,a0,4
 1974 04c4 97000000 		call	HW_set_8bit_reg_field
 1974      E7800000 
 1975 04cc 03250400 		lw	a0,0(s0)
 1976 04d0 13068000 		li	a2,8
 1977 04d4 93053000 		li	a1,3
 1978 04d8 13050501 		addi	a0,a0,16
 1979 04dc 97000000 		call	HW_get_8bit_reg_field
 1979      E7800000 
 1980 04e4 93071000 		li	a5,1
 1981 04e8 E318F5BA 		bne	a0,a5,.L330
 1982 04ec 6FF0DFED 		j	.L371
 1983              	.L376:
 1984 04f0 8327C403 		lw	a5,60(s0)
 1985 04f4 63860700 		beq	a5,zero,.L327
 1986 04f8 13050400 		mv	a0,s0
 1987 04fc E7800700 		jalr	a5
 1988              	.L327:
 1989 0500 03250400 		lw	a0,0(s0)
 1990 0504 83258403 		lw	a1,56(s0)
 1991 0508 13058502 		addi	a0,a0,40
 1992 050c 97000000 		call	HW_set_32bit_reg
 1992      E7800000 
 1993 0514 03270400 		lw	a4,0(s0)
 1994 0518 6FF05FE7 		j	.L328
 1995              	.L374:
 1996 051c 13050400 		mv	a0,s0
 1997 0520 97000000 		call	read_slave_rx_fifo
 1997      E7800000 
 1998 0528 83270402 		lw	a5,32(s0)
 1999 052c 83240403 		lw	s1,48(s0)
 2000 0530 63860704 		beq	a5,zero,.L334
 2001 0534 03250400 		lw	a0,0(s0)
 2002 0538 93061000 		li	a3,1
 2003 053c 13060001 		li	a2,16
 2004 0540 93054000 		li	a1,4
 2005 0544 13054500 		addi	a0,a0,4
 2006 0548 23220402 		sw	zero,36(s0)
 2007 054c 232A0400 		sw	zero,20(s0)
 2008 0550 232C0400 		sw	zero,24(s0)
 2009 0554 232E0400 		sw	zero,28(s0)
 2010 0558 97000000 		call	HW_set_8bit_reg_field
 2010      E7800000 
 2011 0560 03250400 		lw	a0,0(s0)
 2012 0564 93061000 		li	a3,1
 2013 0568 13060001 		li	a2,16
 2014 056c 93054000 		li	a1,4
 2015 0570 13058501 		addi	a0,a0,24
 2016 0574 97000000 		call	HW_set_8bit_reg_field
 2016      E7800000 
 2017              	.L334:
 2018 057c 03250400 		lw	a0,0(s0)
 2019 0580 93053000 		li	a1,3
 2020 0584 23280400 		sw	zero,16(s0)
 2021 0588 1305C501 		addi	a0,a0,28
 2022 058c 97000000 		call	HW_set_8bit_reg
 2022      E7800000 
 2023 0594 13050400 		mv	a0,s0
 2024 0598 97000000 		call	fill_slave_tx_fifo
 2024      E7800000 
 2025 05a0 83270404 		lw	a5,64(s0)
 2026 05a4 23280402 		sw	zero,48(s0)
 2027 05a8 63880700 		beq	a5,zero,.L335
 2028 05ac 03258402 		lw	a0,40(s0)
 2029 05b0 93850400 		mv	a1,s1
 2030 05b4 E7800700 		jalr	a5
 2031              	.L335:
 2032 05b8 03250400 		lw	a0,0(s0)
 2033 05bc 93061000 		li	a3,1
 2034 05c0 13060004 		li	a2,64
 2035 05c4 93056000 		li	a1,6
 2036 05c8 13054500 		addi	a0,a0,4
 2037 05cc 97000000 		call	HW_set_8bit_reg_field
 2037      E7800000 
 2038 05d4 6FF09FB2 		j	.L333
 2039              	.L366:
 2040 05d8 83270400 		lw	a5,0(s0)
 2041 05dc 6FF05FCB 		j	.L311
 2042              	.L375:
 2043 05e0 83274402 		lw	a5,36(s0)
 2044 05e4 E39A07D2 		bne	a5,zero,.L338
 2045 05e8 6FF09FB6 		j	.L312
 2047              		.ident	"GCC: (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 8.3.0"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 core_spi.c
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:10     .text.recover_from_rx_overflow.isra.0:0000000000000000 recover_from_rx_overflow.isra.0
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:40     .text.fill_slave_tx_fifo:0000000000000000 fill_slave_tx_fifo
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:114    .text.read_slave_rx_fifo:0000000000000000 read_slave_rx_fifo
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:189    .text.SPI_init:0000000000000000 SPI_init
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:283    .text.SPI_configure_slave_mode:0000000000000000 SPI_configure_slave_mode
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:325    .text.SPI_configure_master_mode:0000000000000000 SPI_configure_master_mode
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:367    .text.SPI_set_slave_select:0000000000000000 SPI_set_slave_select
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:435    .text.SPI_clear_slave_select:0000000000000000 SPI_clear_slave_select
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:504    .text.SPI_transfer_frame:0000000000000000 SPI_transfer_frame
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:568    .text.SPI_transfer_block:0000000000000000 SPI_transfer_block
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:875    .text.SPI_transfer_block_store_all_resp:0000000000000000 SPI_transfer_block_store_all_resp
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1189   .text.SPI_set_frame_rx_handler:0000000000000000 SPI_set_frame_rx_handler
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1283   .text.SPI_set_slave_tx_frame:0000000000000000 SPI_set_slave_tx_frame
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1378   .text.SPI_set_slave_block_buffers:0000000000000000 SPI_set_slave_block_buffers
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1515   .text.SPI_set_cmd_handler:0000000000000000 SPI_set_cmd_handler
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1586   .text.SPI_set_cmd_response:0000000000000000 SPI_set_cmd_response
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1626   .text.SPI_enable:0000000000000000 SPI_enable
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1645   .text.SPI_disable:0000000000000000 SPI_disable
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1664   .text.SPI_isr:0000000000000000 SPI_isr
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:62     .text.fill_slave_tx_fifo:0000000000000054 .L5
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:77     .text.fill_slave_tx_fifo:000000000000008c .L8
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:49     .text.fill_slave_tx_fifo:0000000000000020 .L7
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:72     .text.fill_slave_tx_fifo:000000000000007c .L4
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:87     .text.fill_slave_tx_fifo:00000000000000b4 .L10
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:163    .text.read_slave_rx_fifo:00000000000000bc .L17
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:173    .text.read_slave_rx_fifo:00000000000000e4 .L34
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:143    .text.read_slave_rx_fifo:0000000000000074 .L16
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:180    .text.read_slave_rx_fifo:0000000000000100 .L24
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:130    .text.read_slave_rx_fifo:0000000000000040 .L26
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:159    .text.read_slave_rx_fifo:00000000000000b0 .L19
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:148    .text.read_slave_rx_fifo:0000000000000084 .L20
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:137    .text.read_slave_rx_fifo:000000000000005c .L35
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:226    .text.SPI_init:000000000000005c .L52
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:206    .text.SPI_init:000000000000002c .L38
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:210    .text.SPI_init:0000000000000038 .L51
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:216    .text.SPI_init:000000000000003c .L40
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:219    .text.SPI_init:0000000000000044 .L36
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:233    .text.SPI_init:0000000000000064 .L53
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:199    .text.SPI_init:0000000000000024 .L37
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:275    .text.SPI_init:0000000000000120 .L54
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:244    .text.SPI_init:0000000000000090 .L42
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:313    .text.SPI_configure_slave_mode:0000000000000088 .L60
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:355    .text.SPI_configure_master_mode:0000000000000088 .L66
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:395    .text.SPI_set_slave_select:0000000000000058 .L82
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:378    .text.SPI_set_slave_select:0000000000000014 .L83
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:404    .text.SPI_set_slave_select:0000000000000068 .L84
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:371    .text.SPI_set_slave_select:000000000000000c .L69
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:426    .text.SPI_set_slave_select:00000000000000c4 .L85
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:412    .text.SPI_set_slave_select:0000000000000088 .L72
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:463    .text.SPI_clear_slave_select:0000000000000058 .L101
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:446    .text.SPI_clear_slave_select:0000000000000014 .L102
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:472    .text.SPI_clear_slave_select:0000000000000068 .L103
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:439    .text.SPI_clear_slave_select:000000000000000c .L88
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:495    .text.SPI_clear_slave_select:00000000000000c8 .L104
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:480    .text.SPI_clear_slave_select:0000000000000088 .L91
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:524    .text.SPI_transfer_frame:0000000000000050 .L113
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:536    .text.SPI_transfer_frame:000000000000006c .L109
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:545    .text.SPI_transfer_frame:0000000000000094 .L108
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:604    .text.SPI_transfer_block:000000000000008c .L163
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:592    .text.SPI_transfer_block:0000000000000060 .L114
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:611    .text.SPI_transfer_block:0000000000000094 .L164
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:858    .text.SPI_transfer_block:0000000000000450 .L165
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:866    .text.SPI_transfer_block:0000000000000470 .L166
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:672    .text.SPI_transfer_block:0000000000000180 .L121
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:649    .text.SPI_transfer_block:000000000000012c .L125
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:657    .text.SPI_transfer_block:000000000000014c .L124
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:637    .text.SPI_transfer_block:0000000000000100 .L167
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:640    .text.SPI_transfer_block:000000000000010c .L123
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:862    .text.SPI_transfer_block:0000000000000460 .L126
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:723    .text.SPI_transfer_block:000000000000024c .L128
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:697    .text.SPI_transfer_block:00000000000001e0 .L129
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:736    .text.SPI_transfer_block:000000000000027c .L168
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:679    .text.SPI_transfer_block:000000000000019c .L162
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:752    .text.SPI_transfer_block:00000000000002bc .L134
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:729    .text.SPI_transfer_block:0000000000000260 .L135
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:740    .text.SPI_transfer_block:000000000000028c .L169
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:713    .text.SPI_transfer_block:0000000000000224 .L170
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:689    .text.SPI_transfer_block:00000000000001c4 .L131
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:795    .text.SPI_transfer_block:0000000000000364 .L142
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:807    .text.SPI_transfer_block:0000000000000390 .L171
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:754    .text.SPI_transfer_block:00000000000002c0 .L138
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:831    .text.SPI_transfer_block:00000000000003f0 .L172
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:819    .text.SPI_transfer_block:00000000000003c0 .L173
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:780    .text.SPI_transfer_block:0000000000000328 .L174
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:759    .text.SPI_transfer_block:00000000000002d0 .L139
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:800    .text.SPI_transfer_block:0000000000000374 .L143
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:843    .text.SPI_transfer_block:0000000000000418 .L147
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:848    .text.SPI_transfer_block:0000000000000428 .L175
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:838    .text.SPI_transfer_block:0000000000000404 .L148
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:833    .text.SPI_transfer_block:00000000000003f4 .L146
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:624    .text.SPI_transfer_block:00000000000000cc .L118
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:667    .text.SPI_transfer_block:0000000000000170 .L127
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:659    .text.SPI_transfer_block:0000000000000150 .L120
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:914    .text.SPI_transfer_block_store_all_resp:0000000000000098 .L225
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:901    .text.SPI_transfer_block_store_all_resp:0000000000000068 .L176
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:921    .text.SPI_transfer_block_store_all_resp:00000000000000a0 .L226
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1172   .text.SPI_transfer_block_store_all_resp:000000000000046c .L227
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1180   .text.SPI_transfer_block_store_all_resp:000000000000048c .L228
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:982    .text.SPI_transfer_block_store_all_resp:000000000000018c .L183
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:959    .text.SPI_transfer_block_store_all_resp:0000000000000138 .L187
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:967    .text.SPI_transfer_block_store_all_resp:0000000000000158 .L186
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:947    .text.SPI_transfer_block_store_all_resp:000000000000010c .L229
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:950    .text.SPI_transfer_block_store_all_resp:0000000000000118 .L185
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1176   .text.SPI_transfer_block_store_all_resp:000000000000047c .L188
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1037   .text.SPI_transfer_block_store_all_resp:0000000000000268 .L190
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1007   .text.SPI_transfer_block_store_all_resp:00000000000001ec .L191
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1050   .text.SPI_transfer_block_store_all_resp:0000000000000298 .L230
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:989    .text.SPI_transfer_block_store_all_resp:00000000000001a8 .L224
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1066   .text.SPI_transfer_block_store_all_resp:00000000000002d8 .L196
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1043   .text.SPI_transfer_block_store_all_resp:000000000000027c .L197
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1054   .text.SPI_transfer_block_store_all_resp:00000000000002a8 .L231
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1025   .text.SPI_transfer_block_store_all_resp:0000000000000238 .L232
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:999    .text.SPI_transfer_block_store_all_resp:00000000000001d0 .L193
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1109   .text.SPI_transfer_block_store_all_resp:0000000000000380 .L204
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1121   .text.SPI_transfer_block_store_all_resp:00000000000003ac .L233
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1068   .text.SPI_transfer_block_store_all_resp:00000000000002dc .L200
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1145   .text.SPI_transfer_block_store_all_resp:000000000000040c .L234
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1133   .text.SPI_transfer_block_store_all_resp:00000000000003dc .L235
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1094   .text.SPI_transfer_block_store_all_resp:0000000000000344 .L236
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1073   .text.SPI_transfer_block_store_all_resp:00000000000002ec .L201
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1114   .text.SPI_transfer_block_store_all_resp:0000000000000390 .L205
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1157   .text.SPI_transfer_block_store_all_resp:0000000000000434 .L209
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1162   .text.SPI_transfer_block_store_all_resp:0000000000000444 .L237
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1152   .text.SPI_transfer_block_store_all_resp:0000000000000420 .L210
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1147   .text.SPI_transfer_block_store_all_resp:0000000000000410 .L208
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:934    .text.SPI_transfer_block_store_all_resp:00000000000000d8 .L180
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:977    .text.SPI_transfer_block_store_all_resp:000000000000017c .L189
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:969    .text.SPI_transfer_block_store_all_resp:000000000000015c .L182
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1207   .text.SPI_set_frame_rx_handler:0000000000000048 .L246
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1214   .text.SPI_set_frame_rx_handler:0000000000000050 .L242
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1246   .text.SPI_set_frame_rx_handler:00000000000000e0 .L241
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1304   .text.SPI_set_slave_tx_frame:0000000000000054 .L255
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1311   .text.SPI_set_slave_tx_frame:000000000000005c .L251
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1342   .text.SPI_set_slave_tx_frame:00000000000000e8 .L250
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1408   .text.SPI_set_slave_block_buffers:0000000000000078 .L267
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1415   .text.SPI_set_slave_block_buffers:0000000000000080 .L263
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1455   .text.SPI_set_slave_block_buffers:0000000000000128 .L259
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1463   .text.SPI_set_slave_block_buffers:0000000000000148 .L261
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1442   .text.SPI_set_slave_block_buffers:00000000000000f4 .L260
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1573   .text.SPI_set_cmd_handler:00000000000000c4 .L280
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1566   .text.SPI_set_cmd_handler:00000000000000bc .L281
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1526   .text.SPI_set_cmd_handler:0000000000000014 .L271
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1564   .text.SPI_set_cmd_handler:00000000000000b8 .L268
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1518   .text.SPI_set_cmd_handler:0000000000000008 .L270
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1613   .text.SPI_set_cmd_response:000000000000003c .L291
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1606   .text.SPI_set_cmd_response:0000000000000034 .L292
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1597   .text.SPI_set_cmd_response:0000000000000014 .L285
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1604   .text.SPI_set_cmd_response:0000000000000030 .L282
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1589   .text.SPI_set_cmd_response:0000000000000008 .L284
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1633   .text.SPI_enable:000000000000001c .L296
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1652   .text.SPI_disable:000000000000001c .L300
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1723   .text.SPI_isr:00000000000000ec .L367
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1744   .text.SPI_isr:0000000000000128 .L368
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1891   .text.SPI_isr:0000000000000364 .L369
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1964   .text.SPI_isr:000000000000049c .L370
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1915   .text.SPI_isr:00000000000003c8 .L371
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1933   .text.SPI_isr:0000000000000418 .L372
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1730   .text.SPI_isr:00000000000000f4 .L373
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1995   .text.SPI_isr:000000000000051c .L374
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1800   .text.SPI_isr:0000000000000204 .L304
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1772   .text.SPI_isr:0000000000000194 .L323
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1685   .text.SPI_isr:0000000000000058 .L325
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1753   .text.SPI_isr:000000000000014c .L365
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1769   .text.SPI_isr:000000000000018c .L322
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1796   .text.SPI_isr:00000000000001f8 .L306
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1785   .text.SPI_isr:00000000000001cc .L307
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1823   .text.SPI_isr:0000000000000260 .L308
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:2039   .text.SPI_isr:00000000000005d8 .L366
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1810   .text.SPI_isr:000000000000022c .L310
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1755   .text.SPI_isr:0000000000000150 .L312
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1855   .text.SPI_isr:00000000000002dc .L339
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:2042   .text.SPI_isr:00000000000005e0 .L375
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1861   .text.SPI_isr:00000000000002f4 .L316
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1841   .text.SPI_isr:00000000000002a4 .L315
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1883   .text.SPI_isr:0000000000000344 .L317
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1876   .text.SPI_isr:0000000000000328 .L318
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1983   .text.SPI_isr:00000000000004f0 .L376
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1901   .text.SPI_isr:000000000000038c .L328
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1693   .text.SPI_isr:0000000000000078 .L329
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1709   .text.SPI_isr:00000000000000b8 .L331
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1941   .text.SPI_isr:0000000000000438 .L332
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1717   .text.SPI_isr:00000000000000d8 .L301
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1701   .text.SPI_isr:0000000000000098 .L330
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1988   .text.SPI_isr:0000000000000500 .L327
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:2017   .text.SPI_isr:000000000000057c .L334
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:2031   .text.SPI_isr:00000000000005b8 .L335
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1733   .text.SPI_isr:00000000000000fc .L333
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1835   .text.SPI_isr:0000000000000290 .L311
C:\Users\i68629\AppData\Local\Temp\ccHr6FUr.s:1871   .text.SPI_isr:0000000000000318 .L338

UNDEFINED SYMBOLS
HW_set_8bit_reg_field
HW_set_8bit_reg
HW_set_32bit_reg
HW_get_8bit_reg_field
HW_get_32bit_reg
memset
HW_get_8bit_reg
