
miv-rv32im-bootloader.elf:     file format elf32-littleriscv
miv-rv32im-bootloader.elf
architecture: riscv:rv32, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x80100000

Program Header:
    LOAD off    0x00001000 vaddr 0x80100000 paddr 0x80100000 align 2**12
         filesz 0x00003d10 memsz 0x00003d10 flags r-x
    LOAD off    0x00005000 vaddr 0x70000000 paddr 0x80103d10 align 2**12
         filesz 0x00000010 memsz 0x00000040 flags rw-
    LOAD off    0x00005040 vaddr 0x70000040 paddr 0x80103d20 align 2**12
         filesz 0x00000000 memsz 0x00002070 flags rw-
    LOAD off    0x000050b0 vaddr 0x700020b0 paddr 0x80103d20 align 2**12
         filesz 0x00000000 memsz 0x00001000 flags rw-

Sections:
Idx Name              Size      VMA       LMA       File off  Algn  Flags
  0 .entry            000009a0  80100000  80100000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .text             00003370  801009a0  801009a0  000019a0  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .sdata            00000000  70000000  70000000  00005010  2**4  CONTENTS
  3 .data             00000010  70000000  80103d10  00005000  2**4  CONTENTS, ALLOC, LOAD, DATA
  4 .sbss             00000030  70000010  80103d20  00005010  2**4  ALLOC
  5 .bss              00002070  70000040  80103d20  00005040  2**4  ALLOC
  6 .heap             00000000  700020b0  700020b0  00005010  2**4  CONTENTS
  7 .stack            00001000  700020b0  80103d20  000050b0  2**4  ALLOC
  8 .debug_info       00005884  00000000  00000000  00005010  2**0  CONTENTS, READONLY, DEBUGGING
  9 .debug_abbrev     000012e1  00000000  00000000  0000a894  2**0  CONTENTS, READONLY, DEBUGGING
 10 .debug_aranges    00000468  00000000  00000000  0000bb78  2**3  CONTENTS, READONLY, DEBUGGING
 11 .debug_ranges     000003b0  00000000  00000000  0000bfe0  2**3  CONTENTS, READONLY, DEBUGGING
 12 .debug_macro      00003e79  00000000  00000000  0000c390  2**0  CONTENTS, READONLY, DEBUGGING
 13 .debug_line       000068b6  00000000  00000000  00010209  2**0  CONTENTS, READONLY, DEBUGGING
 14 .debug_str        0000d6ca  00000000  00000000  00016abf  2**0  CONTENTS, READONLY, DEBUGGING
 15 .comment          00000051  00000000  00000000  00024189  2**0  CONTENTS, READONLY
 16 .riscv.attributes 00000021  00000000  00000000  000241da  2**0  CONTENTS, READONLY
 17 .debug_frame      0000107c  00000000  00000000  000241fc  2**2  CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
80100000 l    d  .entry	00000000 .entry
801009a0 l    d  .text	00000000 .text
70000000 l    d  .sdata	00000000 .sdata
70000000 l    d  .data	00000000 .data
70000010 l    d  .sbss	00000000 .sbss
70000040 l    d  .bss	00000000 .bss
700020b0 l    d  .heap	00000000 .heap
700020b0 l    d  .stack	00000000 .stack
00000000 l    d  .debug_info	00000000 .debug_info
00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
00000000 l    d  .debug_aranges	00000000 .debug_aranges
00000000 l    d  .debug_ranges	00000000 .debug_ranges
00000000 l    d  .debug_macro	00000000 .debug_macro
00000000 l    d  .debug_line	00000000 .debug_line
00000000 l    d  .debug_str	00000000 .debug_str
00000000 l    d  .comment	00000000 .comment
00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
00000000 l    d  .debug_frame	00000000 .debug_frame
00000000 l    df *ABS*	00000000 ./miv_rv32_hal/miv_rv32_entry.o
801010cc l       .text	00000000 handle_reset
80100004 l       .entry	00000000 trap_entry
80100090 l       .entry	00000000 generic_trap_handler
80100010 l       .entry	00000000 sw_trap_entry
80100120 l       .entry	00000000 vector_sw_trap_handler
80100020 l       .entry	00000000 tmr_trap_entry
801001a8 l       .entry	00000000 vector_tmr_trap_handler
80100030 l       .entry	00000000 ext_trap_entry
80100230 l       .entry	00000000 vector_ext_trap_handler
80100044 l       .entry	00000000 MGEUI_trap_entry
801002b8 l       .entry	00000000 vector_MGEUI_trap_handler
80100048 l       .entry	00000000 MGECI_trap_entry
80100340 l       .entry	00000000 vector_MGECI_trap_handler
8010005c l       .entry	00000000 MSYS_MIE22_trap_entry
80100890 l       .entry	00000000 vector_SUBSYSR_IRQHandler
80100060 l       .entry	00000000 MSYS_MIE23_trap_entry
801006f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
80100064 l       .entry	00000000 MSYS_MIE24_trap_entry
801003c8 l       .entry	00000000 vector_MSYS_EI0_trap_handler
80100068 l       .entry	00000000 MSYS_MIE25_trap_entry
80100450 l       .entry	00000000 vector_MSYS_EI1_trap_handler
8010006c l       .entry	00000000 MSYS_MIE26_trap_entry
801004d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
80100070 l       .entry	00000000 MSYS_MIE27_trap_entry
80100560 l       .entry	00000000 vector_MSYS_EI3_trap_handler
80100074 l       .entry	00000000 MSYS_MIE28_trap_entry
801005e8 l       .entry	00000000 vector_MSYS_EI4_trap_handler
80100078 l       .entry	00000000 MSYS_MIE29_trap_entry
80100670 l       .entry	00000000 vector_MSYS_EI5_trap_handler
8010007c l       .entry	00000000 MSYS_MIE30_trap_entry
80100780 l       .entry	00000000 vector_MSYS_EI6_trap_handler
80100080 l       .entry	00000000 MSYS_MIE31_trap_entry
80100808 l       .entry	00000000 vector_MSYS_EI7_trap_handler
80100918 l       .entry	00000000 generic_restore
8010111c l       .text	00000000 ima_cores_setup
80101168 l       .text	00000000 vector_address_not_matching
80101128 l       .text	00000000 generic_reset_handling
801011f4 l       .text	00000000 block_copy
8010116c l       .text	00000000 initializations
801011d4 l       .text	00000000 zeroize_block
8010121c l       .text	00000000 block_copy_error
801011e4 l       .text	00000000 zeroize_loop
80101204 l       .text	00000000 block_copy_loop
80101220 l       .text	00000000 block_copy_exit
00000000 l    df *ABS*	00000000 mt25ql01gbbb.c
8010105c l     F .text	00000070 wait_ready_erase
80100ff4 l     F .text	00000068 wait_ready
00000000 l    df *ABS*	00000000 miv_rv32_hal.c
80101224 l     F .text	00000094 MRV_read_mtime
801012b8 l     F .text	00000030 MRV_clear_soft_irq
70000010 l     O .sbss	00000008 g_systick_increment
70000018 l     O .sbss	00000008 g_systick_cmp_value
70000020 l     O .sbss	00000004 d_tick.2196
00000000 l    df *ABS*	00000000 miv_rv32_init.c
00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
00000000 l    df *ABS*	00000000 core_uart_apb.c
00000000 l    df *ABS*	00000000 core_spi.c
801027c0 l     F .text	00000090 recover_from_rx_overflow
00000000 l    df *ABS*	00000000 core_gpio.c
00000000 l    df *ABS*	00000000 main.c
80102c80 l     F .text	00000030 MRV_disable_interrupts
80102ce8 l     F .text	000003b8 read_page_from_host_through_uart
80103870 l     F .text	00000044 Bootloader_JumpToApplication
7000008c g     O .bss	00000008 g_gpio
00001000 g       *ABS*	00000000 STACK_SIZE
70000800 g       .sdata	00000000 __global_pointer$
80101bc8 g     F .text	00000154 UART_get_rx
80102cb0 g     F .text	00000038 delay1
80103d10 g       *ABS*	00000000 __data_load
8010168c  w    F .text	0000001c SysTick_Handler
80101908 g       .text	00000000 HW_get_8bit_reg_field
70000010 g       .sbss	00000000 __sbss_start
8010144c g     F .text	00000088 handle_local_ei_interrupts
80101840 g       .text	00000000 HW_set_32bit_reg
80100db0 g     F .text	00000244 FLASH_program
70000000 g       .sdata	00000000 __sdata_start
80101788  w    F .text	0000001c MSYS_EI4_IRQHandler
70000094 g     O .bss	00000008 g_uart
801018e0 g       .text	00000000 HW_set_8bit_reg_field
801016fc  w    F .text	0000001c SUBSYS_IRQHandler
801014d4 g     F .text	0000015c handle_trap
00010000 g       *ABS*	00000000 RAM_SIZE
801017d8  w    F .text	0000001c MSYS_EI6_IRQHandler
801021f0 g     F .text	000005d0 SPI_transfer_block
70000040 g     O .bss	0000004c g_flash_core_spi
80101810  w    F .text	0000001c SUBSYSR_IRQHandler
80100b30 g     F .text	000000a4 FLASH_global_unprotect
801016c4  w    F .text	0000001c MGECI_IRQHandler
700020b0 g       .heap	00000000 _heap_end
801038d0 g     O .text	00000040 local_irq_handler_table
801017f4  w    F .text	0000001c MSYS_EI7_IRQHandler
80101ff4 g     F .text	000000fc SPI_set_slave_select
700020b0 g       .bss	00000000 __bss_end
80101630 g     F .text	00000028 _init
801030a0 g     F .text	0000008c number_size
801018d0 g       .text	00000000 HW_set_8bit_reg
801018d8 g       .text	00000000 HW_get_8bit_reg
80100a70 g     F .text	000000c0 FLASH_read
80101734  w    F .text	0000001c MSYS_EI1_IRQHandler
70000040 g       .sbss	00000000 __sbss_end
80101850 g       .text	00000000 HW_set_32bit_reg_field
801035e0 g     F .text	0000014c read_program_from_flash_and_copy_to_ddr
80100bd4 g     F .text	000000e0 FLASH_erase_64k_block
80100cb4 g     F .text	000000fc write_cmd_data
700030b0 g       .stack	00000000 __stack_top
8010312c g     F .text	00000090 copy_to_flash
80101d1c g     F .text	000000c8 UART_polled_tx_string
00000000 g       *ABS*	00000000 HEAP_SIZE
70000000 g     O .data	0000000c flash_address
80101af0 g     F .text	000000d8 UART_send
80100000 g       .entry	00000000 _start
801009a0 g     F .text	00000044 FLASH_init
801012e8 g     F .text	00000138 handle_m_timer_interrupt
80103d10 g       *ABS*	00000000 __sdata_load
70000010 g       .data	00000000 __data_end
80103ac8 g     O .text	00000134 g_instructions_msg
80101878 g       .text	00000000 HW_get_32bit_reg_field
801031bc g     F .text	00000424 load_spi_flash_with_images_thruough_uart_intf
7000009c g     O .bss	00001000 g_read_buf
80102850 g     F .text	00000174 GPIO_init
80101f38 g     F .text	000000bc SPI_configure_master_mode
70000024 g     O .sbss	00000001 no_of_files
7000109c g     O .bss	00000004 g_10ms_count
80103910 g     O .text	000001b5 g_greeting_msg
70000000 g       *ABS*	00000000 RAM_START_ADDRESS
70000040 g       .bss	00000000 __bss_start
801038b4 g     F .text	0000001c memset
8010372c g     F .text	00000144 main
801017a4  w    F .text	0000001c MSYS_EI5_IRQHandler
801016e0  w    F .text	0000001c MGEUI_IRQHandler
70000028 g     O .sbss	00000004 g_src_image_target_address
80101890 g       .text	00000000 HW_get_16bit_reg
70000000 g       .sdata	00000000 __sdata_end
700020b0 g       .heap	00000000 __heap_end
80101658 g     F .text	0000001c _fini
801009e4 g     F .text	0000008c FLASH_read_device_id
7000002c g     O .sbss	00000004 g_file_size
80101898 g       .text	00000000 HW_set_16bit_reg_field
80101750  w    F .text	0000001c MSYS_EI2_IRQHandler
700020b0 g       .stack	00000000 __stack_bottom
80101674  w    F .text	00000018 Software_IRQHandler
700020b0 g       .heap	00000000 __heap_start
700010a0 g     O .bss	00001000 g_write_buffer
700020b0 g       .bss	00000000 _end
801017c0  w    F .text	00000018 Reserved_IRQHandler
80101de4 g     F .text	00000154 SPI_init
80101918 g     F .text	000001d8 UART_init
80101848 g       .text	00000000 HW_get_32bit_reg
8010182c g     F .text	00000014 _exit
80101888 g       .text	00000000 HW_set_16bit_reg
70000030 g     O .sbss	00000004 g_flash_address
8010176c  w    F .text	0000001c MSYS_EI3_IRQHandler
801016a8  w    F .text	0000001c External_IRQHandler
70000000 g       .data	00000000 __data_start
801020f0 g     F .text	00000100 SPI_clear_slave_select
80101420 g     F .text	0000002c handle_m_soft_interrupt
801018c0 g       .text	00000000 HW_get_16bit_reg_field
801029c4 g     F .text	000002bc GPIO_set_output
80101718  w    F .text	0000001c MSYS_EI0_IRQHandler
700020a0 g     O .bss	00000004 g_state



Disassembly of section .entry:

80100000 <_start>:
_start():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:113

  .section      .entry, "ax"
  .globl _start

_start:
  j handle_reset
80100000:	0cc0106f          	j	801010cc <handle_reset>

80100004 <trap_entry>:
trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:124
   at the jump and you can at least look at mcause, mepc and get some hints
   about the crash. */
trap_entry:
.option push
.option norvc
j generic_trap_handler
80100004:	08c0006f          	j	80100090 <generic_trap_handler>
	...

80100010 <sw_trap_entry>:
sw_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:130
.option pop
  .word 0
  .word 0

sw_trap_entry:
  j vector_sw_trap_handler
80100010:	1100006f          	j	80100120 <vector_sw_trap_handler>
	...

80100020 <tmr_trap_entry>:
tmr_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:139
  .word 0
  .word 0
  .word 0

tmr_trap_entry:
  j vector_tmr_trap_handler
80100020:	1880006f          	j	801001a8 <vector_tmr_trap_handler>
	...

80100030 <ext_trap_entry>:
ext_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:148
  .word 0
  .word 0
  .word 0

ext_trap_entry:
  j vector_ext_trap_handler
80100030:	2000006f          	j	80100230 <vector_ext_trap_handler>
	...

80100044 <MGEUI_trap_entry>:
MGEUI_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:159
  .word 0
  .word 0

#ifndef MIV_LEGACY_RV32
MGEUI_trap_entry:
  j vector_MGEUI_trap_handler
80100044:	2740006f          	j	801002b8 <vector_MGEUI_trap_handler>

80100048 <MGECI_trap_entry>:
MGECI_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:165
#ifdef __riscv_compressed
  .2byte 0
#endif

MGECI_trap_entry:
  j vector_MGECI_trap_handler
80100048:	2f80006f          	j	80100340 <vector_MGECI_trap_handler>
	...

8010005c <MSYS_MIE22_trap_entry>:
MSYS_MIE22_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:177
  .word 0

#ifndef MIV_RV32_V3_0
MSYS_MIE22_trap_entry:
#ifndef MIV_RV32_V3_0 
  j vector_SUBSYSR_IRQHandler
8010005c:	0350006f          	j	80100890 <vector_SUBSYSR_IRQHandler>

80100060 <MSYS_MIE23_trap_entry>:
MSYS_MIE23_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:184
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE23_trap_entry:
  j vector_SUBSYS_IRQHandler
80100060:	6980006f          	j	801006f8 <vector_SUBSYS_IRQHandler>

80100064 <MSYS_MIE24_trap_entry>:
MSYS_MIE24_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:191
  .2byte 0
#endif
#endif /*MIV_RV32_V3_0*/

MSYS_MIE24_trap_entry:
  j vector_MSYS_EI0_trap_handler
80100064:	3640006f          	j	801003c8 <vector_MSYS_EI0_trap_handler>

80100068 <MSYS_MIE25_trap_entry>:
MSYS_MIE25_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:197
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE25_trap_entry:
  j vector_MSYS_EI1_trap_handler
80100068:	3e80006f          	j	80100450 <vector_MSYS_EI1_trap_handler>

8010006c <MSYS_MIE26_trap_entry>:
MSYS_MIE26_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:203
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE26_trap_entry:
  j vector_MSYS_EI2_trap_handler
8010006c:	46c0006f          	j	801004d8 <vector_MSYS_EI2_trap_handler>

80100070 <MSYS_MIE27_trap_entry>:
MSYS_MIE27_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:209
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE27_trap_entry:
  j vector_MSYS_EI3_trap_handler
80100070:	4f00006f          	j	80100560 <vector_MSYS_EI3_trap_handler>

80100074 <MSYS_MIE28_trap_entry>:
MSYS_MIE28_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:215
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE28_trap_entry:
  j vector_MSYS_EI4_trap_handler
80100074:	5740006f          	j	801005e8 <vector_MSYS_EI4_trap_handler>

80100078 <MSYS_MIE29_trap_entry>:
MSYS_MIE29_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:221
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE29_trap_entry:
  j vector_MSYS_EI5_trap_handler
80100078:	5f80006f          	j	80100670 <vector_MSYS_EI5_trap_handler>

8010007c <MSYS_MIE30_trap_entry>:
MSYS_MIE30_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:228
  .2byte 0
#endif

MSYS_MIE30_trap_entry:
#ifndef MIV_RV32_V3_0
  j vector_MSYS_EI6_trap_handler
8010007c:	7040006f          	j	80100780 <vector_MSYS_EI6_trap_handler>

80100080 <MSYS_MIE31_trap_entry>:
MSYS_MIE31_trap_entry():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:238
  .2byte 0
#endif

#ifndef MIV_RV32_V3_0
MSYS_MIE31_trap_entry:
  j vector_MSYS_EI7_trap_handler
80100080:	7880006f          	j	80100808 <vector_MSYS_EI7_trap_handler>
80100084:	00000013          	nop
80100088:	00000013          	nop
8010008c:	00000013          	nop

80100090 <generic_trap_handler>:
generic_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:247
#endif /* MIV_RV32_V3_0 */
#endif /* MIV_LEGACY_RV32 */

.align 4
generic_trap_handler:
  STORE_CONTEXT
80100090:	f8010113          	addi	sp,sp,-128
80100094:	00112023          	sw	ra,0(sp)
80100098:	00212223          	sw	sp,4(sp)
8010009c:	00312423          	sw	gp,8(sp)
801000a0:	00412623          	sw	tp,12(sp)
801000a4:	00512823          	sw	t0,16(sp)
801000a8:	00612a23          	sw	t1,20(sp)
801000ac:	00712c23          	sw	t2,24(sp)
801000b0:	00812e23          	sw	s0,28(sp)
801000b4:	02912023          	sw	s1,32(sp)
801000b8:	02a12223          	sw	a0,36(sp)
801000bc:	02b12423          	sw	a1,40(sp)
801000c0:	02c12623          	sw	a2,44(sp)
801000c4:	02d12823          	sw	a3,48(sp)
801000c8:	02e12a23          	sw	a4,52(sp)
801000cc:	02f12c23          	sw	a5,56(sp)
801000d0:	03012e23          	sw	a6,60(sp)
801000d4:	05112023          	sw	a7,64(sp)
801000d8:	05212223          	sw	s2,68(sp)
801000dc:	05312423          	sw	s3,72(sp)
801000e0:	05412623          	sw	s4,76(sp)
801000e4:	05512823          	sw	s5,80(sp)
801000e8:	05612a23          	sw	s6,84(sp)
801000ec:	05712c23          	sw	s7,88(sp)
801000f0:	05812e23          	sw	s8,92(sp)
801000f4:	07912023          	sw	s9,96(sp)
801000f8:	07a12223          	sw	s10,100(sp)
801000fc:	07b12423          	sw	s11,104(sp)
80100100:	07c12623          	sw	t3,108(sp)
80100104:	07d12823          	sw	t4,112(sp)
80100108:	07e12a23          	sw	t5,116(sp)
8010010c:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:248
  csrr a0, mcause
80100110:	34202573          	csrr	a0,mcause
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:249
  csrr a1, mepc
80100114:	341025f3          	csrr	a1,mepc
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:250
  jal handle_trap
80100118:	3bc010ef          	jal	ra,801014d4 <handle_trap>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:251
  j generic_restore
8010011c:	7fc0006f          	j	80100918 <generic_restore>

80100120 <vector_sw_trap_handler>:
vector_sw_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:254

vector_sw_trap_handler:
  STORE_CONTEXT
80100120:	f8010113          	addi	sp,sp,-128
80100124:	00112023          	sw	ra,0(sp)
80100128:	00212223          	sw	sp,4(sp)
8010012c:	00312423          	sw	gp,8(sp)
80100130:	00412623          	sw	tp,12(sp)
80100134:	00512823          	sw	t0,16(sp)
80100138:	00612a23          	sw	t1,20(sp)
8010013c:	00712c23          	sw	t2,24(sp)
80100140:	00812e23          	sw	s0,28(sp)
80100144:	02912023          	sw	s1,32(sp)
80100148:	02a12223          	sw	a0,36(sp)
8010014c:	02b12423          	sw	a1,40(sp)
80100150:	02c12623          	sw	a2,44(sp)
80100154:	02d12823          	sw	a3,48(sp)
80100158:	02e12a23          	sw	a4,52(sp)
8010015c:	02f12c23          	sw	a5,56(sp)
80100160:	03012e23          	sw	a6,60(sp)
80100164:	05112023          	sw	a7,64(sp)
80100168:	05212223          	sw	s2,68(sp)
8010016c:	05312423          	sw	s3,72(sp)
80100170:	05412623          	sw	s4,76(sp)
80100174:	05512823          	sw	s5,80(sp)
80100178:	05612a23          	sw	s6,84(sp)
8010017c:	05712c23          	sw	s7,88(sp)
80100180:	05812e23          	sw	s8,92(sp)
80100184:	07912023          	sw	s9,96(sp)
80100188:	07a12223          	sw	s10,100(sp)
8010018c:	07b12423          	sw	s11,104(sp)
80100190:	07c12623          	sw	t3,108(sp)
80100194:	07d12823          	sw	t4,112(sp)
80100198:	07e12a23          	sw	t5,116(sp)
8010019c:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:255
  jal handle_m_soft_interrupt
801001a0:	280010ef          	jal	ra,80101420 <handle_m_soft_interrupt>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:256
  j generic_restore
801001a4:	7740006f          	j	80100918 <generic_restore>

801001a8 <vector_tmr_trap_handler>:
vector_tmr_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:259

vector_tmr_trap_handler:
  STORE_CONTEXT
801001a8:	f8010113          	addi	sp,sp,-128
801001ac:	00112023          	sw	ra,0(sp)
801001b0:	00212223          	sw	sp,4(sp)
801001b4:	00312423          	sw	gp,8(sp)
801001b8:	00412623          	sw	tp,12(sp)
801001bc:	00512823          	sw	t0,16(sp)
801001c0:	00612a23          	sw	t1,20(sp)
801001c4:	00712c23          	sw	t2,24(sp)
801001c8:	00812e23          	sw	s0,28(sp)
801001cc:	02912023          	sw	s1,32(sp)
801001d0:	02a12223          	sw	a0,36(sp)
801001d4:	02b12423          	sw	a1,40(sp)
801001d8:	02c12623          	sw	a2,44(sp)
801001dc:	02d12823          	sw	a3,48(sp)
801001e0:	02e12a23          	sw	a4,52(sp)
801001e4:	02f12c23          	sw	a5,56(sp)
801001e8:	03012e23          	sw	a6,60(sp)
801001ec:	05112023          	sw	a7,64(sp)
801001f0:	05212223          	sw	s2,68(sp)
801001f4:	05312423          	sw	s3,72(sp)
801001f8:	05412623          	sw	s4,76(sp)
801001fc:	05512823          	sw	s5,80(sp)
80100200:	05612a23          	sw	s6,84(sp)
80100204:	05712c23          	sw	s7,88(sp)
80100208:	05812e23          	sw	s8,92(sp)
8010020c:	07912023          	sw	s9,96(sp)
80100210:	07a12223          	sw	s10,100(sp)
80100214:	07b12423          	sw	s11,104(sp)
80100218:	07c12623          	sw	t3,108(sp)
8010021c:	07d12823          	sw	t4,112(sp)
80100220:	07e12a23          	sw	t5,116(sp)
80100224:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:260
  jal handle_m_timer_interrupt
80100228:	0c0010ef          	jal	ra,801012e8 <handle_m_timer_interrupt>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:261
  j generic_restore
8010022c:	6ec0006f          	j	80100918 <generic_restore>

80100230 <vector_ext_trap_handler>:
vector_ext_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:264

vector_ext_trap_handler:
  STORE_CONTEXT
80100230:	f8010113          	addi	sp,sp,-128
80100234:	00112023          	sw	ra,0(sp)
80100238:	00212223          	sw	sp,4(sp)
8010023c:	00312423          	sw	gp,8(sp)
80100240:	00412623          	sw	tp,12(sp)
80100244:	00512823          	sw	t0,16(sp)
80100248:	00612a23          	sw	t1,20(sp)
8010024c:	00712c23          	sw	t2,24(sp)
80100250:	00812e23          	sw	s0,28(sp)
80100254:	02912023          	sw	s1,32(sp)
80100258:	02a12223          	sw	a0,36(sp)
8010025c:	02b12423          	sw	a1,40(sp)
80100260:	02c12623          	sw	a2,44(sp)
80100264:	02d12823          	sw	a3,48(sp)
80100268:	02e12a23          	sw	a4,52(sp)
8010026c:	02f12c23          	sw	a5,56(sp)
80100270:	03012e23          	sw	a6,60(sp)
80100274:	05112023          	sw	a7,64(sp)
80100278:	05212223          	sw	s2,68(sp)
8010027c:	05312423          	sw	s3,72(sp)
80100280:	05412623          	sw	s4,76(sp)
80100284:	05512823          	sw	s5,80(sp)
80100288:	05612a23          	sw	s6,84(sp)
8010028c:	05712c23          	sw	s7,88(sp)
80100290:	05812e23          	sw	s8,92(sp)
80100294:	07912023          	sw	s9,96(sp)
80100298:	07a12223          	sw	s10,100(sp)
8010029c:	07b12423          	sw	s11,104(sp)
801002a0:	07c12623          	sw	t3,108(sp)
801002a4:	07d12823          	sw	t4,112(sp)
801002a8:	07e12a23          	sw	t5,116(sp)
801002ac:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:268
#ifdef MIV_LEGACY_RV32
  jal handle_m_ext_interrupt
#else
  jal External_IRQHandler
801002b0:	3f8010ef          	jal	ra,801016a8 <External_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:270
#endif /* MIV_LEGACY_RV32 */
  j generic_restore
801002b4:	6640006f          	j	80100918 <generic_restore>

801002b8 <vector_MGEUI_trap_handler>:
vector_MGEUI_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:274

#ifndef MIV_LEGACY_RV32
vector_MGEUI_trap_handler:
  STORE_CONTEXT
801002b8:	f8010113          	addi	sp,sp,-128
801002bc:	00112023          	sw	ra,0(sp)
801002c0:	00212223          	sw	sp,4(sp)
801002c4:	00312423          	sw	gp,8(sp)
801002c8:	00412623          	sw	tp,12(sp)
801002cc:	00512823          	sw	t0,16(sp)
801002d0:	00612a23          	sw	t1,20(sp)
801002d4:	00712c23          	sw	t2,24(sp)
801002d8:	00812e23          	sw	s0,28(sp)
801002dc:	02912023          	sw	s1,32(sp)
801002e0:	02a12223          	sw	a0,36(sp)
801002e4:	02b12423          	sw	a1,40(sp)
801002e8:	02c12623          	sw	a2,44(sp)
801002ec:	02d12823          	sw	a3,48(sp)
801002f0:	02e12a23          	sw	a4,52(sp)
801002f4:	02f12c23          	sw	a5,56(sp)
801002f8:	03012e23          	sw	a6,60(sp)
801002fc:	05112023          	sw	a7,64(sp)
80100300:	05212223          	sw	s2,68(sp)
80100304:	05312423          	sw	s3,72(sp)
80100308:	05412623          	sw	s4,76(sp)
8010030c:	05512823          	sw	s5,80(sp)
80100310:	05612a23          	sw	s6,84(sp)
80100314:	05712c23          	sw	s7,88(sp)
80100318:	05812e23          	sw	s8,92(sp)
8010031c:	07912023          	sw	s9,96(sp)
80100320:	07a12223          	sw	s10,100(sp)
80100324:	07b12423          	sw	s11,104(sp)
80100328:	07c12623          	sw	t3,108(sp)
8010032c:	07d12823          	sw	t4,112(sp)
80100330:	07e12a23          	sw	t5,116(sp)
80100334:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:275
  jal MGEUI_IRQHandler
80100338:	3a8010ef          	jal	ra,801016e0 <MGEUI_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:276
  j generic_restore
8010033c:	5dc0006f          	j	80100918 <generic_restore>

80100340 <vector_MGECI_trap_handler>:
vector_MGECI_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:279

vector_MGECI_trap_handler:
  STORE_CONTEXT
80100340:	f8010113          	addi	sp,sp,-128
80100344:	00112023          	sw	ra,0(sp)
80100348:	00212223          	sw	sp,4(sp)
8010034c:	00312423          	sw	gp,8(sp)
80100350:	00412623          	sw	tp,12(sp)
80100354:	00512823          	sw	t0,16(sp)
80100358:	00612a23          	sw	t1,20(sp)
8010035c:	00712c23          	sw	t2,24(sp)
80100360:	00812e23          	sw	s0,28(sp)
80100364:	02912023          	sw	s1,32(sp)
80100368:	02a12223          	sw	a0,36(sp)
8010036c:	02b12423          	sw	a1,40(sp)
80100370:	02c12623          	sw	a2,44(sp)
80100374:	02d12823          	sw	a3,48(sp)
80100378:	02e12a23          	sw	a4,52(sp)
8010037c:	02f12c23          	sw	a5,56(sp)
80100380:	03012e23          	sw	a6,60(sp)
80100384:	05112023          	sw	a7,64(sp)
80100388:	05212223          	sw	s2,68(sp)
8010038c:	05312423          	sw	s3,72(sp)
80100390:	05412623          	sw	s4,76(sp)
80100394:	05512823          	sw	s5,80(sp)
80100398:	05612a23          	sw	s6,84(sp)
8010039c:	05712c23          	sw	s7,88(sp)
801003a0:	05812e23          	sw	s8,92(sp)
801003a4:	07912023          	sw	s9,96(sp)
801003a8:	07a12223          	sw	s10,100(sp)
801003ac:	07b12423          	sw	s11,104(sp)
801003b0:	07c12623          	sw	t3,108(sp)
801003b4:	07d12823          	sw	t4,112(sp)
801003b8:	07e12a23          	sw	t5,116(sp)
801003bc:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:280
  jal MGECI_IRQHandler
801003c0:	304010ef          	jal	ra,801016c4 <MGECI_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:281
  j generic_restore
801003c4:	5540006f          	j	80100918 <generic_restore>

801003c8 <vector_MSYS_EI0_trap_handler>:
vector_MSYS_EI0_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:284

vector_MSYS_EI0_trap_handler:
  STORE_CONTEXT
801003c8:	f8010113          	addi	sp,sp,-128
801003cc:	00112023          	sw	ra,0(sp)
801003d0:	00212223          	sw	sp,4(sp)
801003d4:	00312423          	sw	gp,8(sp)
801003d8:	00412623          	sw	tp,12(sp)
801003dc:	00512823          	sw	t0,16(sp)
801003e0:	00612a23          	sw	t1,20(sp)
801003e4:	00712c23          	sw	t2,24(sp)
801003e8:	00812e23          	sw	s0,28(sp)
801003ec:	02912023          	sw	s1,32(sp)
801003f0:	02a12223          	sw	a0,36(sp)
801003f4:	02b12423          	sw	a1,40(sp)
801003f8:	02c12623          	sw	a2,44(sp)
801003fc:	02d12823          	sw	a3,48(sp)
80100400:	02e12a23          	sw	a4,52(sp)
80100404:	02f12c23          	sw	a5,56(sp)
80100408:	03012e23          	sw	a6,60(sp)
8010040c:	05112023          	sw	a7,64(sp)
80100410:	05212223          	sw	s2,68(sp)
80100414:	05312423          	sw	s3,72(sp)
80100418:	05412623          	sw	s4,76(sp)
8010041c:	05512823          	sw	s5,80(sp)
80100420:	05612a23          	sw	s6,84(sp)
80100424:	05712c23          	sw	s7,88(sp)
80100428:	05812e23          	sw	s8,92(sp)
8010042c:	07912023          	sw	s9,96(sp)
80100430:	07a12223          	sw	s10,100(sp)
80100434:	07b12423          	sw	s11,104(sp)
80100438:	07c12623          	sw	t3,108(sp)
8010043c:	07d12823          	sw	t4,112(sp)
80100440:	07e12a23          	sw	t5,116(sp)
80100444:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:285
  jal MSYS_EI0_IRQHandler
80100448:	2d0010ef          	jal	ra,80101718 <MSYS_EI0_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:286
  j generic_restore
8010044c:	4cc0006f          	j	80100918 <generic_restore>

80100450 <vector_MSYS_EI1_trap_handler>:
vector_MSYS_EI1_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:289

vector_MSYS_EI1_trap_handler:
  STORE_CONTEXT
80100450:	f8010113          	addi	sp,sp,-128
80100454:	00112023          	sw	ra,0(sp)
80100458:	00212223          	sw	sp,4(sp)
8010045c:	00312423          	sw	gp,8(sp)
80100460:	00412623          	sw	tp,12(sp)
80100464:	00512823          	sw	t0,16(sp)
80100468:	00612a23          	sw	t1,20(sp)
8010046c:	00712c23          	sw	t2,24(sp)
80100470:	00812e23          	sw	s0,28(sp)
80100474:	02912023          	sw	s1,32(sp)
80100478:	02a12223          	sw	a0,36(sp)
8010047c:	02b12423          	sw	a1,40(sp)
80100480:	02c12623          	sw	a2,44(sp)
80100484:	02d12823          	sw	a3,48(sp)
80100488:	02e12a23          	sw	a4,52(sp)
8010048c:	02f12c23          	sw	a5,56(sp)
80100490:	03012e23          	sw	a6,60(sp)
80100494:	05112023          	sw	a7,64(sp)
80100498:	05212223          	sw	s2,68(sp)
8010049c:	05312423          	sw	s3,72(sp)
801004a0:	05412623          	sw	s4,76(sp)
801004a4:	05512823          	sw	s5,80(sp)
801004a8:	05612a23          	sw	s6,84(sp)
801004ac:	05712c23          	sw	s7,88(sp)
801004b0:	05812e23          	sw	s8,92(sp)
801004b4:	07912023          	sw	s9,96(sp)
801004b8:	07a12223          	sw	s10,100(sp)
801004bc:	07b12423          	sw	s11,104(sp)
801004c0:	07c12623          	sw	t3,108(sp)
801004c4:	07d12823          	sw	t4,112(sp)
801004c8:	07e12a23          	sw	t5,116(sp)
801004cc:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:290
  jal MSYS_EI1_IRQHandler
801004d0:	264010ef          	jal	ra,80101734 <MSYS_EI1_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:291
  j generic_restore
801004d4:	4440006f          	j	80100918 <generic_restore>

801004d8 <vector_MSYS_EI2_trap_handler>:
vector_MSYS_EI2_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:294

vector_MSYS_EI2_trap_handler:
  STORE_CONTEXT
801004d8:	f8010113          	addi	sp,sp,-128
801004dc:	00112023          	sw	ra,0(sp)
801004e0:	00212223          	sw	sp,4(sp)
801004e4:	00312423          	sw	gp,8(sp)
801004e8:	00412623          	sw	tp,12(sp)
801004ec:	00512823          	sw	t0,16(sp)
801004f0:	00612a23          	sw	t1,20(sp)
801004f4:	00712c23          	sw	t2,24(sp)
801004f8:	00812e23          	sw	s0,28(sp)
801004fc:	02912023          	sw	s1,32(sp)
80100500:	02a12223          	sw	a0,36(sp)
80100504:	02b12423          	sw	a1,40(sp)
80100508:	02c12623          	sw	a2,44(sp)
8010050c:	02d12823          	sw	a3,48(sp)
80100510:	02e12a23          	sw	a4,52(sp)
80100514:	02f12c23          	sw	a5,56(sp)
80100518:	03012e23          	sw	a6,60(sp)
8010051c:	05112023          	sw	a7,64(sp)
80100520:	05212223          	sw	s2,68(sp)
80100524:	05312423          	sw	s3,72(sp)
80100528:	05412623          	sw	s4,76(sp)
8010052c:	05512823          	sw	s5,80(sp)
80100530:	05612a23          	sw	s6,84(sp)
80100534:	05712c23          	sw	s7,88(sp)
80100538:	05812e23          	sw	s8,92(sp)
8010053c:	07912023          	sw	s9,96(sp)
80100540:	07a12223          	sw	s10,100(sp)
80100544:	07b12423          	sw	s11,104(sp)
80100548:	07c12623          	sw	t3,108(sp)
8010054c:	07d12823          	sw	t4,112(sp)
80100550:	07e12a23          	sw	t5,116(sp)
80100554:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:295
  jal MSYS_EI2_IRQHandler
80100558:	1f8010ef          	jal	ra,80101750 <MSYS_EI2_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:296
  j generic_restore
8010055c:	3bc0006f          	j	80100918 <generic_restore>

80100560 <vector_MSYS_EI3_trap_handler>:
vector_MSYS_EI3_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:299

vector_MSYS_EI3_trap_handler:
  STORE_CONTEXT
80100560:	f8010113          	addi	sp,sp,-128
80100564:	00112023          	sw	ra,0(sp)
80100568:	00212223          	sw	sp,4(sp)
8010056c:	00312423          	sw	gp,8(sp)
80100570:	00412623          	sw	tp,12(sp)
80100574:	00512823          	sw	t0,16(sp)
80100578:	00612a23          	sw	t1,20(sp)
8010057c:	00712c23          	sw	t2,24(sp)
80100580:	00812e23          	sw	s0,28(sp)
80100584:	02912023          	sw	s1,32(sp)
80100588:	02a12223          	sw	a0,36(sp)
8010058c:	02b12423          	sw	a1,40(sp)
80100590:	02c12623          	sw	a2,44(sp)
80100594:	02d12823          	sw	a3,48(sp)
80100598:	02e12a23          	sw	a4,52(sp)
8010059c:	02f12c23          	sw	a5,56(sp)
801005a0:	03012e23          	sw	a6,60(sp)
801005a4:	05112023          	sw	a7,64(sp)
801005a8:	05212223          	sw	s2,68(sp)
801005ac:	05312423          	sw	s3,72(sp)
801005b0:	05412623          	sw	s4,76(sp)
801005b4:	05512823          	sw	s5,80(sp)
801005b8:	05612a23          	sw	s6,84(sp)
801005bc:	05712c23          	sw	s7,88(sp)
801005c0:	05812e23          	sw	s8,92(sp)
801005c4:	07912023          	sw	s9,96(sp)
801005c8:	07a12223          	sw	s10,100(sp)
801005cc:	07b12423          	sw	s11,104(sp)
801005d0:	07c12623          	sw	t3,108(sp)
801005d4:	07d12823          	sw	t4,112(sp)
801005d8:	07e12a23          	sw	t5,116(sp)
801005dc:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:300
  jal MSYS_EI3_IRQHandler
801005e0:	18c010ef          	jal	ra,8010176c <MSYS_EI3_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:301
  j generic_restore
801005e4:	3340006f          	j	80100918 <generic_restore>

801005e8 <vector_MSYS_EI4_trap_handler>:
vector_MSYS_EI4_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:304

vector_MSYS_EI4_trap_handler:
  STORE_CONTEXT
801005e8:	f8010113          	addi	sp,sp,-128
801005ec:	00112023          	sw	ra,0(sp)
801005f0:	00212223          	sw	sp,4(sp)
801005f4:	00312423          	sw	gp,8(sp)
801005f8:	00412623          	sw	tp,12(sp)
801005fc:	00512823          	sw	t0,16(sp)
80100600:	00612a23          	sw	t1,20(sp)
80100604:	00712c23          	sw	t2,24(sp)
80100608:	00812e23          	sw	s0,28(sp)
8010060c:	02912023          	sw	s1,32(sp)
80100610:	02a12223          	sw	a0,36(sp)
80100614:	02b12423          	sw	a1,40(sp)
80100618:	02c12623          	sw	a2,44(sp)
8010061c:	02d12823          	sw	a3,48(sp)
80100620:	02e12a23          	sw	a4,52(sp)
80100624:	02f12c23          	sw	a5,56(sp)
80100628:	03012e23          	sw	a6,60(sp)
8010062c:	05112023          	sw	a7,64(sp)
80100630:	05212223          	sw	s2,68(sp)
80100634:	05312423          	sw	s3,72(sp)
80100638:	05412623          	sw	s4,76(sp)
8010063c:	05512823          	sw	s5,80(sp)
80100640:	05612a23          	sw	s6,84(sp)
80100644:	05712c23          	sw	s7,88(sp)
80100648:	05812e23          	sw	s8,92(sp)
8010064c:	07912023          	sw	s9,96(sp)
80100650:	07a12223          	sw	s10,100(sp)
80100654:	07b12423          	sw	s11,104(sp)
80100658:	07c12623          	sw	t3,108(sp)
8010065c:	07d12823          	sw	t4,112(sp)
80100660:	07e12a23          	sw	t5,116(sp)
80100664:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:305
  jal MSYS_EI4_IRQHandler
80100668:	120010ef          	jal	ra,80101788 <MSYS_EI4_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:306
  j generic_restore
8010066c:	2ac0006f          	j	80100918 <generic_restore>

80100670 <vector_MSYS_EI5_trap_handler>:
vector_MSYS_EI5_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:309

vector_MSYS_EI5_trap_handler:
  STORE_CONTEXT
80100670:	f8010113          	addi	sp,sp,-128
80100674:	00112023          	sw	ra,0(sp)
80100678:	00212223          	sw	sp,4(sp)
8010067c:	00312423          	sw	gp,8(sp)
80100680:	00412623          	sw	tp,12(sp)
80100684:	00512823          	sw	t0,16(sp)
80100688:	00612a23          	sw	t1,20(sp)
8010068c:	00712c23          	sw	t2,24(sp)
80100690:	00812e23          	sw	s0,28(sp)
80100694:	02912023          	sw	s1,32(sp)
80100698:	02a12223          	sw	a0,36(sp)
8010069c:	02b12423          	sw	a1,40(sp)
801006a0:	02c12623          	sw	a2,44(sp)
801006a4:	02d12823          	sw	a3,48(sp)
801006a8:	02e12a23          	sw	a4,52(sp)
801006ac:	02f12c23          	sw	a5,56(sp)
801006b0:	03012e23          	sw	a6,60(sp)
801006b4:	05112023          	sw	a7,64(sp)
801006b8:	05212223          	sw	s2,68(sp)
801006bc:	05312423          	sw	s3,72(sp)
801006c0:	05412623          	sw	s4,76(sp)
801006c4:	05512823          	sw	s5,80(sp)
801006c8:	05612a23          	sw	s6,84(sp)
801006cc:	05712c23          	sw	s7,88(sp)
801006d0:	05812e23          	sw	s8,92(sp)
801006d4:	07912023          	sw	s9,96(sp)
801006d8:	07a12223          	sw	s10,100(sp)
801006dc:	07b12423          	sw	s11,104(sp)
801006e0:	07c12623          	sw	t3,108(sp)
801006e4:	07d12823          	sw	t4,112(sp)
801006e8:	07e12a23          	sw	t5,116(sp)
801006ec:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:310
  jal MSYS_EI5_IRQHandler
801006f0:	0b4010ef          	jal	ra,801017a4 <MSYS_EI5_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:311
  j generic_restore
801006f4:	2240006f          	j	80100918 <generic_restore>

801006f8 <vector_SUBSYS_IRQHandler>:
vector_SUBSYS_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:314

vector_SUBSYS_IRQHandler:
  STORE_CONTEXT
801006f8:	f8010113          	addi	sp,sp,-128
801006fc:	00112023          	sw	ra,0(sp)
80100700:	00212223          	sw	sp,4(sp)
80100704:	00312423          	sw	gp,8(sp)
80100708:	00412623          	sw	tp,12(sp)
8010070c:	00512823          	sw	t0,16(sp)
80100710:	00612a23          	sw	t1,20(sp)
80100714:	00712c23          	sw	t2,24(sp)
80100718:	00812e23          	sw	s0,28(sp)
8010071c:	02912023          	sw	s1,32(sp)
80100720:	02a12223          	sw	a0,36(sp)
80100724:	02b12423          	sw	a1,40(sp)
80100728:	02c12623          	sw	a2,44(sp)
8010072c:	02d12823          	sw	a3,48(sp)
80100730:	02e12a23          	sw	a4,52(sp)
80100734:	02f12c23          	sw	a5,56(sp)
80100738:	03012e23          	sw	a6,60(sp)
8010073c:	05112023          	sw	a7,64(sp)
80100740:	05212223          	sw	s2,68(sp)
80100744:	05312423          	sw	s3,72(sp)
80100748:	05412623          	sw	s4,76(sp)
8010074c:	05512823          	sw	s5,80(sp)
80100750:	05612a23          	sw	s6,84(sp)
80100754:	05712c23          	sw	s7,88(sp)
80100758:	05812e23          	sw	s8,92(sp)
8010075c:	07912023          	sw	s9,96(sp)
80100760:	07a12223          	sw	s10,100(sp)
80100764:	07b12423          	sw	s11,104(sp)
80100768:	07c12623          	sw	t3,108(sp)
8010076c:	07d12823          	sw	t4,112(sp)
80100770:	07e12a23          	sw	t5,116(sp)
80100774:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:315
  jal SUBSYS_IRQHandler
80100778:	785000ef          	jal	ra,801016fc <SUBSYS_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:316
  j generic_restore
8010077c:	19c0006f          	j	80100918 <generic_restore>

80100780 <vector_MSYS_EI6_trap_handler>:
vector_MSYS_EI6_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:320

#ifndef MIV_RV32_V3_0
vector_MSYS_EI6_trap_handler:
  STORE_CONTEXT
80100780:	f8010113          	addi	sp,sp,-128
80100784:	00112023          	sw	ra,0(sp)
80100788:	00212223          	sw	sp,4(sp)
8010078c:	00312423          	sw	gp,8(sp)
80100790:	00412623          	sw	tp,12(sp)
80100794:	00512823          	sw	t0,16(sp)
80100798:	00612a23          	sw	t1,20(sp)
8010079c:	00712c23          	sw	t2,24(sp)
801007a0:	00812e23          	sw	s0,28(sp)
801007a4:	02912023          	sw	s1,32(sp)
801007a8:	02a12223          	sw	a0,36(sp)
801007ac:	02b12423          	sw	a1,40(sp)
801007b0:	02c12623          	sw	a2,44(sp)
801007b4:	02d12823          	sw	a3,48(sp)
801007b8:	02e12a23          	sw	a4,52(sp)
801007bc:	02f12c23          	sw	a5,56(sp)
801007c0:	03012e23          	sw	a6,60(sp)
801007c4:	05112023          	sw	a7,64(sp)
801007c8:	05212223          	sw	s2,68(sp)
801007cc:	05312423          	sw	s3,72(sp)
801007d0:	05412623          	sw	s4,76(sp)
801007d4:	05512823          	sw	s5,80(sp)
801007d8:	05612a23          	sw	s6,84(sp)
801007dc:	05712c23          	sw	s7,88(sp)
801007e0:	05812e23          	sw	s8,92(sp)
801007e4:	07912023          	sw	s9,96(sp)
801007e8:	07a12223          	sw	s10,100(sp)
801007ec:	07b12423          	sw	s11,104(sp)
801007f0:	07c12623          	sw	t3,108(sp)
801007f4:	07d12823          	sw	t4,112(sp)
801007f8:	07e12a23          	sw	t5,116(sp)
801007fc:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:321
  jal MSYS_EI6_IRQHandler
80100800:	7d9000ef          	jal	ra,801017d8 <MSYS_EI6_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:322
  j generic_restore
80100804:	1140006f          	j	80100918 <generic_restore>

80100808 <vector_MSYS_EI7_trap_handler>:
vector_MSYS_EI7_trap_handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:325

vector_MSYS_EI7_trap_handler:
  STORE_CONTEXT
80100808:	f8010113          	addi	sp,sp,-128
8010080c:	00112023          	sw	ra,0(sp)
80100810:	00212223          	sw	sp,4(sp)
80100814:	00312423          	sw	gp,8(sp)
80100818:	00412623          	sw	tp,12(sp)
8010081c:	00512823          	sw	t0,16(sp)
80100820:	00612a23          	sw	t1,20(sp)
80100824:	00712c23          	sw	t2,24(sp)
80100828:	00812e23          	sw	s0,28(sp)
8010082c:	02912023          	sw	s1,32(sp)
80100830:	02a12223          	sw	a0,36(sp)
80100834:	02b12423          	sw	a1,40(sp)
80100838:	02c12623          	sw	a2,44(sp)
8010083c:	02d12823          	sw	a3,48(sp)
80100840:	02e12a23          	sw	a4,52(sp)
80100844:	02f12c23          	sw	a5,56(sp)
80100848:	03012e23          	sw	a6,60(sp)
8010084c:	05112023          	sw	a7,64(sp)
80100850:	05212223          	sw	s2,68(sp)
80100854:	05312423          	sw	s3,72(sp)
80100858:	05412623          	sw	s4,76(sp)
8010085c:	05512823          	sw	s5,80(sp)
80100860:	05612a23          	sw	s6,84(sp)
80100864:	05712c23          	sw	s7,88(sp)
80100868:	05812e23          	sw	s8,92(sp)
8010086c:	07912023          	sw	s9,96(sp)
80100870:	07a12223          	sw	s10,100(sp)
80100874:	07b12423          	sw	s11,104(sp)
80100878:	07c12623          	sw	t3,108(sp)
8010087c:	07d12823          	sw	t4,112(sp)
80100880:	07e12a23          	sw	t5,116(sp)
80100884:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:326
  jal MSYS_EI7_IRQHandler
80100888:	76d000ef          	jal	ra,801017f4 <MSYS_EI7_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:327
  j generic_restore
8010088c:	08c0006f          	j	80100918 <generic_restore>

80100890 <vector_SUBSYSR_IRQHandler>:
vector_SUBSYSR_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:331


vector_SUBSYSR_IRQHandler:
  STORE_CONTEXT
80100890:	f8010113          	addi	sp,sp,-128
80100894:	00112023          	sw	ra,0(sp)
80100898:	00212223          	sw	sp,4(sp)
8010089c:	00312423          	sw	gp,8(sp)
801008a0:	00412623          	sw	tp,12(sp)
801008a4:	00512823          	sw	t0,16(sp)
801008a8:	00612a23          	sw	t1,20(sp)
801008ac:	00712c23          	sw	t2,24(sp)
801008b0:	00812e23          	sw	s0,28(sp)
801008b4:	02912023          	sw	s1,32(sp)
801008b8:	02a12223          	sw	a0,36(sp)
801008bc:	02b12423          	sw	a1,40(sp)
801008c0:	02c12623          	sw	a2,44(sp)
801008c4:	02d12823          	sw	a3,48(sp)
801008c8:	02e12a23          	sw	a4,52(sp)
801008cc:	02f12c23          	sw	a5,56(sp)
801008d0:	03012e23          	sw	a6,60(sp)
801008d4:	05112023          	sw	a7,64(sp)
801008d8:	05212223          	sw	s2,68(sp)
801008dc:	05312423          	sw	s3,72(sp)
801008e0:	05412623          	sw	s4,76(sp)
801008e4:	05512823          	sw	s5,80(sp)
801008e8:	05612a23          	sw	s6,84(sp)
801008ec:	05712c23          	sw	s7,88(sp)
801008f0:	05812e23          	sw	s8,92(sp)
801008f4:	07912023          	sw	s9,96(sp)
801008f8:	07a12223          	sw	s10,100(sp)
801008fc:	07b12423          	sw	s11,104(sp)
80100900:	07c12623          	sw	t3,108(sp)
80100904:	07d12823          	sw	t4,112(sp)
80100908:	07e12a23          	sw	t5,116(sp)
8010090c:	07f12c23          	sw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:332
  jal SUBSYSR_IRQHandler
80100910:	701000ef          	jal	ra,80101810 <SUBSYSR_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:333
  j generic_restore
80100914:	0040006f          	j	80100918 <generic_restore>

80100918 <generic_restore>:
generic_restore():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:339

#endif /*MIV_RV32_V3_0*/
#endif /* MIV_LEGACY_RV32 */

generic_restore:
  LREG x1, 0 * REGBYTES(sp)
80100918:	00012083          	lw	ra,0(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:340
  LREG x2, 1 * REGBYTES(sp)
8010091c:	00412103          	lw	sp,4(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:341
  LREG x3, 2 * REGBYTES(sp)
80100920:	00812183          	lw	gp,8(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:342
  LREG x4, 3 * REGBYTES(sp)
80100924:	00c12203          	lw	tp,12(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:343
  LREG x5, 4 * REGBYTES(sp)
80100928:	01012283          	lw	t0,16(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:344
  LREG x6, 5 * REGBYTES(sp)
8010092c:	01412303          	lw	t1,20(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:345
  LREG x7, 6 * REGBYTES(sp)
80100930:	01812383          	lw	t2,24(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:346
  LREG x8, 7 * REGBYTES(sp)
80100934:	01c12403          	lw	s0,28(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:347
  LREG x9, 8 * REGBYTES(sp)
80100938:	02012483          	lw	s1,32(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:348
  LREG x10, 9 * REGBYTES(sp)
8010093c:	02412503          	lw	a0,36(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:349
  LREG x11, 10 * REGBYTES(sp)
80100940:	02812583          	lw	a1,40(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:350
  LREG x12, 11 * REGBYTES(sp)
80100944:	02c12603          	lw	a2,44(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:351
  LREG x13, 12 * REGBYTES(sp)
80100948:	03012683          	lw	a3,48(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:352
  LREG x14, 13 * REGBYTES(sp)
8010094c:	03412703          	lw	a4,52(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:353
  LREG x15, 14 * REGBYTES(sp)
80100950:	03812783          	lw	a5,56(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:354
  LREG x16, 15 * REGBYTES(sp)
80100954:	03c12803          	lw	a6,60(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:355
  LREG x17, 16 * REGBYTES(sp)
80100958:	04012883          	lw	a7,64(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:356
  LREG x18, 17 * REGBYTES(sp)
8010095c:	04412903          	lw	s2,68(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:357
  LREG x19, 18 * REGBYTES(sp)
80100960:	04812983          	lw	s3,72(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:358
  LREG x20, 19 * REGBYTES(sp)
80100964:	04c12a03          	lw	s4,76(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:359
  LREG x21, 20 * REGBYTES(sp)
80100968:	05012a83          	lw	s5,80(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:360
  LREG x22, 21 * REGBYTES(sp)
8010096c:	05412b03          	lw	s6,84(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:361
  LREG x23, 22 * REGBYTES(sp)
80100970:	05812b83          	lw	s7,88(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:362
  LREG x24, 23 * REGBYTES(sp)
80100974:	05c12c03          	lw	s8,92(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:363
  LREG x25, 24 * REGBYTES(sp)
80100978:	06012c83          	lw	s9,96(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:364
  LREG x26, 25 * REGBYTES(sp)
8010097c:	06412d03          	lw	s10,100(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:365
  LREG x27, 26 * REGBYTES(sp)
80100980:	06812d83          	lw	s11,104(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:366
  LREG x28, 27 * REGBYTES(sp)
80100984:	06c12e03          	lw	t3,108(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:367
  LREG x29, 28 * REGBYTES(sp)
80100988:	07012e83          	lw	t4,112(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:368
  LREG x30, 29 * REGBYTES(sp)
8010098c:	07412f03          	lw	t5,116(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:369
  LREG x31, 30 * REGBYTES(sp)
80100990:	07812f83          	lw	t6,120(sp)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:408
  flw	f30, 61*REGBYTES(sp)
  flw	f31, 62*REGBYTES(sp)
  #endif /* __riscv_flen */
  #endif /* MIV_FP_CONTEXT_SAVE */

  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
80100994:	08010113          	addi	sp,sp,128
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:409
  mret
80100998:	30200073          	mret
8010099c:	0000                	unimp
	...

Disassembly of section .text:

801009a0 <FLASH_init>:
FLASH_init():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:58

/*******************************************************************************
 *
 */
void FLASH_init( void )
{
801009a0:	ff010113          	addi	sp,sp,-16
801009a4:	00112623          	sw	ra,12(sp)
801009a8:	00812423          	sw	s0,8(sp)
801009ac:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:62
    /*--------------------------------------------------------------------------
     * Configure SPI.
     */
    SPI_init( SPI_INSTANCE, CORESPI_BASE_ADDR, 32 );
801009b0:	02000613          	li	a2,32
801009b4:	760005b7          	lui	a1,0x76000
801009b8:	700007b7          	lui	a5,0x70000
801009bc:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
801009c0:	424010ef          	jal	ra,80101de4 <SPI_init>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:63
    SPI_configure_master_mode( SPI_INSTANCE );
801009c4:	700007b7          	lui	a5,0x70000
801009c8:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
801009cc:	56c010ef          	jal	ra,80101f38 <SPI_configure_master_mode>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:65

}
801009d0:	00000013          	nop
801009d4:	00c12083          	lw	ra,12(sp)
801009d8:	00812403          	lw	s0,8(sp)
801009dc:	01010113          	addi	sp,sp,16
801009e0:	00008067          	ret

801009e4 <FLASH_read_device_id>:
FLASH_read_device_id():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:75
void FLASH_read_device_id
(
    uint8_t * manufacturer_id,
    uint8_t * device_id
)
{
801009e4:	fd010113          	addi	sp,sp,-48
801009e8:	02112623          	sw	ra,44(sp)
801009ec:	02812423          	sw	s0,40(sp)
801009f0:	03010413          	addi	s0,sp,48
801009f4:	fca42e23          	sw	a0,-36(s0)
801009f8:	fcb42c23          	sw	a1,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:76
    uint8_t read_device_id_cmd = DEVICE_ID_READ;
801009fc:	f9f00793          	li	a5,-97
80100a00:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:79
    uint8_t read_buffer[3];
    
    SPI_set_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100a04:	00000593          	li	a1,0
80100a08:	700007b7          	lui	a5,0x70000
80100a0c:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100a10:	5e4010ef          	jal	ra,80101ff4 <SPI_set_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:80
    SPI_transfer_block(SPI_INSTANCE, &read_device_id_cmd, 1, read_buffer, sizeof(read_buffer));
80100a14:	fec40693          	addi	a3,s0,-20
80100a18:	fef40793          	addi	a5,s0,-17
80100a1c:	00300713          	li	a4,3
80100a20:	00100613          	li	a2,1
80100a24:	00078593          	mv	a1,a5
80100a28:	700007b7          	lui	a5,0x70000
80100a2c:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100a30:	7c0010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:81
    SPI_clear_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100a34:	00000593          	li	a1,0
80100a38:	700007b7          	lui	a5,0x70000
80100a3c:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100a40:	6b0010ef          	jal	ra,801020f0 <SPI_clear_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:83

    *manufacturer_id = read_buffer[0];
80100a44:	fec44703          	lbu	a4,-20(s0)
80100a48:	fdc42783          	lw	a5,-36(s0)
80100a4c:	00e78023          	sb	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:84
    *device_id = read_buffer[1];
80100a50:	fed44703          	lbu	a4,-19(s0)
80100a54:	fd842783          	lw	a5,-40(s0)
80100a58:	00e78023          	sb	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:86

}
80100a5c:	00000013          	nop
80100a60:	02c12083          	lw	ra,44(sp)
80100a64:	02812403          	lw	s0,40(sp)
80100a68:	03010113          	addi	sp,sp,48
80100a6c:	00008067          	ret

80100a70 <FLASH_read>:
FLASH_read():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:97
(
    uint32_t address,
    uint8_t * rx_buffer,
    size_t size_in_bytes
)
{
80100a70:	fd010113          	addi	sp,sp,-48
80100a74:	02112623          	sw	ra,44(sp)
80100a78:	02812423          	sw	s0,40(sp)
80100a7c:	03010413          	addi	s0,sp,48
80100a80:	fca42e23          	sw	a0,-36(s0)
80100a84:	fcb42c23          	sw	a1,-40(s0)
80100a88:	fcc42a23          	sw	a2,-44(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:100
    uint8_t cmd_buffer[6];
    
    cmd_buffer[0] = READ_CMD;
80100a8c:	00300793          	li	a5,3
80100a90:	fef40423          	sb	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:101
    cmd_buffer[1] = (uint8_t)((address >> 16) & 0xFF);
80100a94:	fdc42783          	lw	a5,-36(s0)
80100a98:	0107d793          	srli	a5,a5,0x10
80100a9c:	0ff7f793          	andi	a5,a5,255
80100aa0:	fef404a3          	sb	a5,-23(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:102
    cmd_buffer[2] = (uint8_t)((address >> 8) & 0xFF);;
80100aa4:	fdc42783          	lw	a5,-36(s0)
80100aa8:	0087d793          	srli	a5,a5,0x8
80100aac:	0ff7f793          	andi	a5,a5,255
80100ab0:	fef40523          	sb	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:103
    cmd_buffer[3] = (uint8_t)(address & 0xFF);
80100ab4:	fdc42783          	lw	a5,-36(s0)
80100ab8:	0ff7f793          	andi	a5,a5,255
80100abc:	fef405a3          	sb	a5,-21(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:104
    cmd_buffer[4] = DONT_CARE;
80100ac0:	fe040623          	sb	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:105
    cmd_buffer[5] = DONT_CARE;
80100ac4:	fe0406a3          	sb	zero,-19(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:107
    
    SPI_set_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100ac8:	00000593          	li	a1,0
80100acc:	700007b7          	lui	a5,0x70000
80100ad0:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100ad4:	520010ef          	jal	ra,80101ff4 <SPI_set_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:108
    wait_ready_erase();
80100ad8:	584000ef          	jal	ra,8010105c <wait_ready_erase>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:109
    wait_ready();
80100adc:	518000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:110
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 4, rx_buffer, size_in_bytes);
80100ae0:	fd442783          	lw	a5,-44(s0)
80100ae4:	01079713          	slli	a4,a5,0x10
80100ae8:	01075713          	srli	a4,a4,0x10
80100aec:	fe840793          	addi	a5,s0,-24
80100af0:	fd842683          	lw	a3,-40(s0)
80100af4:	00400613          	li	a2,4
80100af8:	00078593          	mv	a1,a5
80100afc:	700007b7          	lui	a5,0x70000
80100b00:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100b04:	6ec010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:111
    wait_ready();
80100b08:	4ec000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:112
    SPI_clear_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100b0c:	00000593          	li	a1,0
80100b10:	700007b7          	lui	a5,0x70000
80100b14:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100b18:	5d8010ef          	jal	ra,801020f0 <SPI_clear_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:114
    
}
80100b1c:	00000013          	nop
80100b20:	02c12083          	lw	ra,44(sp)
80100b24:	02812403          	lw	s0,40(sp)
80100b28:	03010113          	addi	sp,sp,48
80100b2c:	00008067          	ret

80100b30 <FLASH_global_unprotect>:
FLASH_global_unprotect():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:120

/*******************************************************************************
 *
 */
void FLASH_global_unprotect( void )
{
80100b30:	fe010113          	addi	sp,sp,-32
80100b34:	00112e23          	sw	ra,28(sp)
80100b38:	00812c23          	sw	s0,24(sp)
80100b3c:	02010413          	addi	s0,sp,32
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:123
    uint8_t cmd_buffer[2];
    /* Send Write Enable command */
    cmd_buffer[0] = WRITE_ENABLE_CMD;
80100b40:	00600793          	li	a5,6
80100b44:	fef40623          	sb	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:125

    SPI_set_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100b48:	00000593          	li	a1,0
80100b4c:	700007b7          	lui	a5,0x70000
80100b50:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100b54:	4a0010ef          	jal	ra,80101ff4 <SPI_set_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:126
    wait_ready();
80100b58:	49c000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:127
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 1, 0, 0);
80100b5c:	fec40793          	addi	a5,s0,-20
80100b60:	00000713          	li	a4,0
80100b64:	00000693          	li	a3,0
80100b68:	00100613          	li	a2,1
80100b6c:	00078593          	mv	a1,a5
80100b70:	700007b7          	lui	a5,0x70000
80100b74:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100b78:	678010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:130
    
    /* Send Chip Erase command */
    cmd_buffer[0] = WRITE_STATUS1_OPCODE;
80100b7c:	00100793          	li	a5,1
80100b80:	fef40623          	sb	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:131
    cmd_buffer[1] = 0;
80100b84:	fe0406a3          	sb	zero,-19(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:133
    
    wait_ready();
80100b88:	46c000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:134
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 2, 0, 0);
80100b8c:	fec40793          	addi	a5,s0,-20
80100b90:	00000713          	li	a4,0
80100b94:	00000693          	li	a3,0
80100b98:	00200613          	li	a2,2
80100b9c:	00078593          	mv	a1,a5
80100ba0:	700007b7          	lui	a5,0x70000
80100ba4:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100ba8:	648010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:135
    wait_ready();
80100bac:	448000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:136
    SPI_clear_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100bb0:	00000593          	li	a1,0
80100bb4:	700007b7          	lui	a5,0x70000
80100bb8:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100bbc:	534010ef          	jal	ra,801020f0 <SPI_clear_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:137
}
80100bc0:	00000013          	nop
80100bc4:	01c12083          	lw	ra,28(sp)
80100bc8:	01812403          	lw	s0,24(sp)
80100bcc:	02010113          	addi	sp,sp,32
80100bd0:	00008067          	ret

80100bd4 <FLASH_erase_64k_block>:
FLASH_erase_64k_block():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:201
 */
void FLASH_erase_64k_block
(
    uint32_t address
)
{
80100bd4:	fd010113          	addi	sp,sp,-48
80100bd8:	02112623          	sw	ra,44(sp)
80100bdc:	02812423          	sw	s0,40(sp)
80100be0:	03010413          	addi	s0,sp,48
80100be4:	fca42e23          	sw	a0,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:204
    uint8_t cmd_buffer[4];

    address &= BLOCK_ALIGN_MASK_64K;
80100be8:	fdc42703          	lw	a4,-36(s0)
80100bec:	ffff07b7          	lui	a5,0xffff0
80100bf0:	00f777b3          	and	a5,a4,a5
80100bf4:	fcf42e23          	sw	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:207

    /* Send Write Enable command */
    cmd_buffer[0] = WRITE_ENABLE_CMD;
80100bf8:	00600793          	li	a5,6
80100bfc:	fef40623          	sb	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:209

    SPI_set_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100c00:	00000593          	li	a1,0
80100c04:	700007b7          	lui	a5,0x70000
80100c08:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100c0c:	3e8010ef          	jal	ra,80101ff4 <SPI_set_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:210
    wait_ready();
80100c10:	3e4000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:211
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 1, 0, 0);
80100c14:	fec40793          	addi	a5,s0,-20
80100c18:	00000713          	li	a4,0
80100c1c:	00000693          	li	a3,0
80100c20:	00100613          	li	a2,1
80100c24:	00078593          	mv	a1,a5
80100c28:	700007b7          	lui	a5,0x70000
80100c2c:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100c30:	5c0010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:214

    /* Send Chip Erase command */
    cmd_buffer[0] = ERASE_64K_BLOCK_OPCODE;
80100c34:	fd800793          	li	a5,-40
80100c38:	fef40623          	sb	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:215
    cmd_buffer[1] = (address >> 16) & 0xFF;
80100c3c:	fdc42783          	lw	a5,-36(s0)
80100c40:	0107d793          	srli	a5,a5,0x10
80100c44:	0ff7f793          	andi	a5,a5,255
80100c48:	fef406a3          	sb	a5,-19(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:216
    cmd_buffer[2] = (address >> 8 ) & 0xFF;
80100c4c:	fdc42783          	lw	a5,-36(s0)
80100c50:	0087d793          	srli	a5,a5,0x8
80100c54:	0ff7f793          	andi	a5,a5,255
80100c58:	fef40723          	sb	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:217
    cmd_buffer[3] = address & 0xFF;
80100c5c:	fdc42783          	lw	a5,-36(s0)
80100c60:	0ff7f793          	andi	a5,a5,255
80100c64:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:219

    wait_ready();
80100c68:	38c000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:220
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, sizeof(cmd_buffer), 0, 0);
80100c6c:	fec40793          	addi	a5,s0,-20
80100c70:	00000713          	li	a4,0
80100c74:	00000693          	li	a3,0
80100c78:	00400613          	li	a2,4
80100c7c:	00078593          	mv	a1,a5
80100c80:	700007b7          	lui	a5,0x70000
80100c84:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100c88:	568010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:221
    wait_ready();
80100c8c:	368000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:222
    SPI_clear_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100c90:	00000593          	li	a1,0
80100c94:	700007b7          	lui	a5,0x70000
80100c98:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100c9c:	454010ef          	jal	ra,801020f0 <SPI_clear_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:223
}
80100ca0:	00000013          	nop
80100ca4:	02c12083          	lw	ra,44(sp)
80100ca8:	02812403          	lw	s0,40(sp)
80100cac:	03010113          	addi	sp,sp,48
80100cb0:	00008067          	ret

80100cb4 <write_cmd_data>:
write_cmd_data():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:236
    const uint8_t * cmd_buffer,
    uint16_t cmd_byte_size,
    uint8_t * data_buffer,
    uint16_t data_byte_size
)
{
80100cb4:	dd010113          	addi	sp,sp,-560
80100cb8:	22112623          	sw	ra,556(sp)
80100cbc:	22812423          	sw	s0,552(sp)
80100cc0:	23010413          	addi	s0,sp,560
80100cc4:	dca42e23          	sw	a0,-548(s0)
80100cc8:	dcb42c23          	sw	a1,-552(s0)
80100ccc:	00060793          	mv	a5,a2
80100cd0:	dcd42823          	sw	a3,-560(s0)
80100cd4:	dcf41b23          	sh	a5,-554(s0)
80100cd8:	00070793          	mv	a5,a4
80100cdc:	dcf41a23          	sh	a5,-556(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:239
    uint8_t tx_buffer[516];
    uint16_t transfer_size;
    uint16_t idx = 0;
80100ce0:	fe041723          	sh	zero,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:241
    
    transfer_size = cmd_byte_size + data_byte_size;
80100ce4:	dd645703          	lhu	a4,-554(s0)
80100ce8:	dd445783          	lhu	a5,-556(s0)
80100cec:	00f707b3          	add	a5,a4,a5
80100cf0:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:243
    
    for(idx = 0; idx < cmd_byte_size; ++idx)
80100cf4:	fe041723          	sh	zero,-18(s0)
80100cf8:	0300006f          	j	80100d28 <write_cmd_data+0x74>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:245 (discriminator 3)
    {
        tx_buffer[idx] = cmd_buffer[idx];
80100cfc:	fee45783          	lhu	a5,-18(s0)
80100d00:	dd842703          	lw	a4,-552(s0)
80100d04:	00f70733          	add	a4,a4,a5
80100d08:	fee45783          	lhu	a5,-18(s0)
80100d0c:	00074703          	lbu	a4,0(a4)
80100d10:	ff040693          	addi	a3,s0,-16
80100d14:	00f687b3          	add	a5,a3,a5
80100d18:	dee78c23          	sb	a4,-520(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:243 (discriminator 3)
    for(idx = 0; idx < cmd_byte_size; ++idx)
80100d1c:	fee45783          	lhu	a5,-18(s0)
80100d20:	00178793          	addi	a5,a5,1
80100d24:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:243 (discriminator 1)
80100d28:	fee45703          	lhu	a4,-18(s0)
80100d2c:	dd645783          	lhu	a5,-554(s0)
80100d30:	fcf766e3          	bltu	a4,a5,80100cfc <write_cmd_data+0x48>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:248
    }

    for(idx = 0; idx < data_byte_size; ++idx)
80100d34:	fe041723          	sh	zero,-18(s0)
80100d38:	0380006f          	j	80100d70 <write_cmd_data+0xbc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:250 (discriminator 3)
    {
        tx_buffer[cmd_byte_size + idx] = data_buffer[idx];
80100d3c:	fee45783          	lhu	a5,-18(s0)
80100d40:	dd042703          	lw	a4,-560(s0)
80100d44:	00f70733          	add	a4,a4,a5
80100d48:	dd645683          	lhu	a3,-554(s0)
80100d4c:	fee45783          	lhu	a5,-18(s0)
80100d50:	00f687b3          	add	a5,a3,a5
80100d54:	00074703          	lbu	a4,0(a4)
80100d58:	ff040693          	addi	a3,s0,-16
80100d5c:	00f687b3          	add	a5,a3,a5
80100d60:	dee78c23          	sb	a4,-520(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:248 (discriminator 3)
    for(idx = 0; idx < data_byte_size; ++idx)
80100d64:	fee45783          	lhu	a5,-18(s0)
80100d68:	00178793          	addi	a5,a5,1
80100d6c:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:248 (discriminator 1)
80100d70:	fee45703          	lhu	a4,-18(s0)
80100d74:	dd445783          	lhu	a5,-556(s0)
80100d78:	fcf762e3          	bltu	a4,a5,80100d3c <write_cmd_data+0x88>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:253
    }

    SPI_transfer_block(SPI_INSTANCE, tx_buffer, transfer_size, 0, 0);    
80100d7c:	fec45603          	lhu	a2,-20(s0)
80100d80:	de840793          	addi	a5,s0,-536
80100d84:	00000713          	li	a4,0
80100d88:	00000693          	li	a3,0
80100d8c:	00078593          	mv	a1,a5
80100d90:	700007b7          	lui	a5,0x70000
80100d94:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100d98:	458010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:255
    
}
80100d9c:	00000013          	nop
80100da0:	22c12083          	lw	ra,556(sp)
80100da4:	22812403          	lw	s0,552(sp)
80100da8:	23010113          	addi	sp,sp,560
80100dac:	00008067          	ret

80100db0 <FLASH_program>:
FLASH_program():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:266
(
    uint32_t address,
    uint8_t * write_buffer,
    size_t size_in_bytes
)
{
80100db0:	fc010113          	addi	sp,sp,-64
80100db4:	02112e23          	sw	ra,60(sp)
80100db8:	02812c23          	sw	s0,56(sp)
80100dbc:	04010413          	addi	s0,sp,64
80100dc0:	fca42623          	sw	a0,-52(s0)
80100dc4:	fcb42423          	sw	a1,-56(s0)
80100dc8:	fcc42223          	sw	a2,-60(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:273
    
    uint32_t in_buffer_idx;
    uint32_t nb_bytes_to_write;
    uint32_t target_addr;

    SPI_set_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100dcc:	00000593          	li	a1,0
80100dd0:	700007b7          	lui	a5,0x70000
80100dd4:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100dd8:	21c010ef          	jal	ra,80101ff4 <SPI_set_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:276
    
    /* Send Write Enable command */
    cmd_buffer[0] = WRITE_ENABLE_CMD;
80100ddc:	00600793          	li	a5,6
80100de0:	fcf40e23          	sb	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:277
    wait_ready();
80100de4:	210000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:278
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 1, 0, 0);     
80100de8:	fdc40793          	addi	a5,s0,-36
80100dec:	00000713          	li	a4,0
80100df0:	00000693          	li	a3,0
80100df4:	00100613          	li	a2,1
80100df8:	00078593          	mv	a1,a5
80100dfc:	700007b7          	lui	a5,0x70000
80100e00:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100e04:	3ec010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:281
    
    /* Unprotect sector */
    cmd_buffer[0] = UNPROTECT_SECTOR_OPCODE;
80100e08:	03900793          	li	a5,57
80100e0c:	fcf40e23          	sb	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:282
    cmd_buffer[1] = (address >> 16) & 0xFF;
80100e10:	fcc42783          	lw	a5,-52(s0)
80100e14:	0107d793          	srli	a5,a5,0x10
80100e18:	0ff7f793          	andi	a5,a5,255
80100e1c:	fcf40ea3          	sb	a5,-35(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:283
    cmd_buffer[2] = (address >> 8 ) & 0xFF;
80100e20:	fcc42783          	lw	a5,-52(s0)
80100e24:	0087d793          	srli	a5,a5,0x8
80100e28:	0ff7f793          	andi	a5,a5,255
80100e2c:	fcf40f23          	sb	a5,-34(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:284
    cmd_buffer[3] = address & 0xFF;
80100e30:	fcc42783          	lw	a5,-52(s0)
80100e34:	0ff7f793          	andi	a5,a5,255
80100e38:	fcf40fa3          	sb	a5,-33(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:285
    wait_ready();
80100e3c:	1b8000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:286
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, sizeof(cmd_buffer), 0, 0 );
80100e40:	fdc40793          	addi	a5,s0,-36
80100e44:	00000713          	li	a4,0
80100e48:	00000693          	li	a3,0
80100e4c:	00400613          	li	a2,4
80100e50:	00078593          	mv	a1,a5
80100e54:	700007b7          	lui	a5,0x70000
80100e58:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100e5c:	394010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:287
    wait_ready_erase();
80100e60:	1fc000ef          	jal	ra,8010105c <wait_ready_erase>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:290

    /* Send Write Enable command */
    cmd_buffer[0] = WRITE_ENABLE_CMD;
80100e64:	00600793          	li	a5,6
80100e68:	fcf40e23          	sb	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:291
    wait_ready();
80100e6c:	188000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:292
    SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
80100e70:	fdc40793          	addi	a5,s0,-36
80100e74:	00000713          	li	a4,0
80100e78:	00000693          	li	a3,0
80100e7c:	00100613          	li	a2,1
80100e80:	00078593          	mv	a1,a5
80100e84:	700007b7          	lui	a5,0x70000
80100e88:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100e8c:	364010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:295
    
    /**/
    in_buffer_idx = 0;
80100e90:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:296
    nb_bytes_to_write = size_in_bytes;
80100e94:	fc442783          	lw	a5,-60(s0)
80100e98:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:297
    target_addr = address;
80100e9c:	fcc42783          	lw	a5,-52(s0)
80100ea0:	fef42223          	sw	a5,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:299
    
    while ( in_buffer_idx < size_in_bytes )
80100ea4:	0f40006f          	j	80100f98 <FLASH_program+0x1e8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:301
    {
        wait_ready_erase();
80100ea8:	1b4000ef          	jal	ra,8010105c <wait_ready_erase>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:303
        uint32_t size_left;
        nb_bytes_to_write = 0x100 - (target_addr & 0xFF);   /* adjust max possible size to page boundary. */
80100eac:	fe442783          	lw	a5,-28(s0)
80100eb0:	0ff7f793          	andi	a5,a5,255
80100eb4:	10000713          	li	a4,256
80100eb8:	40f707b3          	sub	a5,a4,a5
80100ebc:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:304
        size_left = size_in_bytes - in_buffer_idx;
80100ec0:	fc442703          	lw	a4,-60(s0)
80100ec4:	fec42783          	lw	a5,-20(s0)
80100ec8:	40f707b3          	sub	a5,a4,a5
80100ecc:	fef42023          	sw	a5,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:305
        if ( size_left < nb_bytes_to_write )
80100ed0:	fe042703          	lw	a4,-32(s0)
80100ed4:	fe842783          	lw	a5,-24(s0)
80100ed8:	00f77663          	bgeu	a4,a5,80100ee4 <FLASH_program+0x134>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:307
        {
            nb_bytes_to_write = size_left;
80100edc:	fe042783          	lw	a5,-32(s0)
80100ee0:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:310
        }
        
        wait_ready();
80100ee4:	110000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:313
        
        /* Send Write Enable command */
        cmd_buffer[0] = WRITE_ENABLE_CMD;
80100ee8:	00600793          	li	a5,6
80100eec:	fcf40e23          	sb	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:314
        SPI_transfer_block(SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
80100ef0:	fdc40793          	addi	a5,s0,-36
80100ef4:	00000713          	li	a4,0
80100ef8:	00000693          	li	a3,0
80100efc:	00100613          	li	a2,1
80100f00:	00078593          	mv	a1,a5
80100f04:	700007b7          	lui	a5,0x70000
80100f08:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100f0c:	2e4010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:317
            
        /* Program page */
        wait_ready();
80100f10:	0e4000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:319
    
        cmd_buffer[0] = PROGRAM_PAGE_CMD;
80100f14:	00200793          	li	a5,2
80100f18:	fcf40e23          	sb	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:320
        cmd_buffer[1] = (target_addr >> 16) & 0xFF;
80100f1c:	fe442783          	lw	a5,-28(s0)
80100f20:	0107d793          	srli	a5,a5,0x10
80100f24:	0ff7f793          	andi	a5,a5,255
80100f28:	fcf40ea3          	sb	a5,-35(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:321
        cmd_buffer[2] = (target_addr >> 8 ) & 0xFF;
80100f2c:	fe442783          	lw	a5,-28(s0)
80100f30:	0087d793          	srli	a5,a5,0x8
80100f34:	0ff7f793          	andi	a5,a5,255
80100f38:	fcf40f23          	sb	a5,-34(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:322
        cmd_buffer[3] = target_addr & 0xFF;
80100f3c:	fe442783          	lw	a5,-28(s0)
80100f40:	0ff7f793          	andi	a5,a5,255
80100f44:	fcf40fa3          	sb	a5,-33(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:324
        
        write_cmd_data
80100f48:	fc842703          	lw	a4,-56(s0)
80100f4c:	fec42783          	lw	a5,-20(s0)
80100f50:	00f706b3          	add	a3,a4,a5
80100f54:	fe842783          	lw	a5,-24(s0)
80100f58:	01079713          	slli	a4,a5,0x10
80100f5c:	01075713          	srli	a4,a4,0x10
80100f60:	fdc40793          	addi	a5,s0,-36
80100f64:	00400613          	li	a2,4
80100f68:	00078593          	mv	a1,a5
80100f6c:	700007b7          	lui	a5,0x70000
80100f70:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100f74:	d41ff0ef          	jal	ra,80100cb4 <write_cmd_data>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:333
            sizeof(cmd_buffer),
            &write_buffer[in_buffer_idx],
            nb_bytes_to_write
          );
        
        target_addr += nb_bytes_to_write;
80100f78:	fe442703          	lw	a4,-28(s0)
80100f7c:	fe842783          	lw	a5,-24(s0)
80100f80:	00f707b3          	add	a5,a4,a5
80100f84:	fef42223          	sw	a5,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:334
        in_buffer_idx += nb_bytes_to_write;
80100f88:	fec42703          	lw	a4,-20(s0)
80100f8c:	fe842783          	lw	a5,-24(s0)
80100f90:	00f707b3          	add	a5,a4,a5
80100f94:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:299
    while ( in_buffer_idx < size_in_bytes )
80100f98:	fec42703          	lw	a4,-20(s0)
80100f9c:	fc442783          	lw	a5,-60(s0)
80100fa0:	f0f764e3          	bltu	a4,a5,80100ea8 <FLASH_program+0xf8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:338
    }
    
    /* Send Write Disable command. */
    cmd_buffer[0] = WRITE_DISABLE_CMD;
80100fa4:	00400793          	li	a5,4
80100fa8:	fcf40e23          	sb	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:340

    wait_ready();
80100fac:	048000ef          	jal	ra,80100ff4 <wait_ready>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:342

    SPI_transfer_block(SPI_INSTANCE,  cmd_buffer, 1, 0, 0 );
80100fb0:	fdc40793          	addi	a5,s0,-36
80100fb4:	00000713          	li	a4,0
80100fb8:	00000693          	li	a3,0
80100fbc:	00100613          	li	a2,1
80100fc0:	00078593          	mv	a1,a5
80100fc4:	700007b7          	lui	a5,0x70000
80100fc8:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100fcc:	224010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:343
    SPI_clear_slave_select(SPI_INSTANCE, SPI_SLAVE);
80100fd0:	00000593          	li	a1,0
80100fd4:	700007b7          	lui	a5,0x70000
80100fd8:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80100fdc:	114010ef          	jal	ra,801020f0 <SPI_clear_slave_select>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:344
}
80100fe0:	00000013          	nop
80100fe4:	03c12083          	lw	ra,60(sp)
80100fe8:	03812403          	lw	s0,56(sp)
80100fec:	04010113          	addi	sp,sp,64
80100ff0:	00008067          	ret

80100ff4 <wait_ready>:
wait_ready():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:363

/*******************************************************************************
 *
 */
static void wait_ready( void )
{
80100ff4:	fe010113          	addi	sp,sp,-32
80100ff8:	00112e23          	sw	ra,28(sp)
80100ffc:	00812c23          	sw	s0,24(sp)
80101000:	02010413          	addi	s0,sp,32
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:365
    uint8_t ready_bit;
    uint8_t command = READ_STATUS;
80101004:	00500793          	li	a5,5
80101008:	fef40723          	sb	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:368 (discriminator 1)
    
    do {
        SPI_transfer_block(SPI_INSTANCE, &command, 1, &ready_bit, sizeof(ready_bit));
8010100c:	fef40693          	addi	a3,s0,-17
80101010:	fee40793          	addi	a5,s0,-18
80101014:	00100713          	li	a4,1
80101018:	00100613          	li	a2,1
8010101c:	00078593          	mv	a1,a5
80101020:	700007b7          	lui	a5,0x70000
80101024:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80101028:	1c8010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:369 (discriminator 1)
        ready_bit = ready_bit & READY_BIT_MASK;
8010102c:	fef44783          	lbu	a5,-17(s0)
80101030:	0017f793          	andi	a5,a5,1
80101034:	0ff7f793          	andi	a5,a5,255
80101038:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:370 (discriminator 1)
    } while( ready_bit == 1 );
8010103c:	fef44703          	lbu	a4,-17(s0)
80101040:	00100793          	li	a5,1
80101044:	fcf704e3          	beq	a4,a5,8010100c <wait_ready+0x18>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:371
}
80101048:	00000013          	nop
8010104c:	01c12083          	lw	ra,28(sp)
80101050:	01812403          	lw	s0,24(sp)
80101054:	02010113          	addi	sp,sp,32
80101058:	00008067          	ret

8010105c <wait_ready_erase>:
wait_ready_erase():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:374

static uint8_t wait_ready_erase( void )
{
8010105c:	fe010113          	addi	sp,sp,-32
80101060:	00112e23          	sw	ra,28(sp)
80101064:	00812c23          	sw	s0,24(sp)
80101068:	02010413          	addi	s0,sp,32
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:375
    uint32_t count = 0;
8010106c:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:377
    uint8_t ready_bit;
    uint8_t command = 0x70 ; // FLAG_READ_STATUS;
80101070:	07000793          	li	a5,112
80101074:	fef40523          	sb	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:380 (discriminator 1)
#if 1
    do {
        SPI_transfer_block(SPI_INSTANCE, &command, 1, &ready_bit, 1);
80101078:	feb40693          	addi	a3,s0,-21
8010107c:	fea40793          	addi	a5,s0,-22
80101080:	00100713          	li	a4,1
80101084:	00100613          	li	a2,1
80101088:	00078593          	mv	a1,a5
8010108c:	700007b7          	lui	a5,0x70000
80101090:	04078513          	addi	a0,a5,64 # 70000040 <__sbss_end>
80101094:	15c010ef          	jal	ra,801021f0 <SPI_transfer_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:381 (discriminator 1)
        count++;
80101098:	fec42783          	lw	a5,-20(s0)
8010109c:	00178793          	addi	a5,a5,1
801010a0:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:382 (discriminator 1)
    } while((ready_bit & 0x80) == 0);
801010a4:	feb44783          	lbu	a5,-21(s0)
801010a8:	01879793          	slli	a5,a5,0x18
801010ac:	4187d793          	srai	a5,a5,0x18
801010b0:	fc07d4e3          	bgez	a5,80101078 <wait_ready_erase+0x1c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:384
#endif
    return (ready_bit);
801010b4:	feb44783          	lbu	a5,-21(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../mt25ql01gbbb/mt25ql01gbbb.c:385
}
801010b8:	00078513          	mv	a0,a5
801010bc:	01c12083          	lw	ra,28(sp)
801010c0:	01812403          	lw	s0,24(sp)
801010c4:	02010113          	addi	sp,sp,32
801010c8:	00008067          	ret

801010cc <handle_reset>:
handle_reset():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:418
/* Ensure instructions are not relaxed, since gp is not yet set */
.option push
.option norelax

#ifndef MIV_RV32_V3_0
  csrwi mstatus, 0
801010cc:	30005073          	csrwi	mstatus,0
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:419
  csrwi mie, 0
801010d0:	30405073          	csrwi	mie,0
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:420
  la ra, _start
801010d4:	fffff097          	auipc	ra,0xfffff
801010d8:	f2c08093          	addi	ra,ra,-212 # 80100000 <_start>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:424

/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
#ifndef MIV_LEGACY_RV32
  li t0, MTIMEH_ADDR
801010dc:	0200c2b7          	lui	t0,0x200c
801010e0:	ffc28293          	addi	t0,t0,-4 # 200bffc <RAM_SIZE+0x1ffbffc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:425
  sw x0, 0(t0)
801010e4:	0002a023          	sw	zero,0(t0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:428
#endif

  csrr t0, misa
801010e8:	301022f3          	csrr	t0,misa
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:429
  andi t0, t0, A_EXTENSION_MASK
801010ec:	0012f293          	andi	t0,t0,1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:430
  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
801010f0:	02029663          	bnez	t0,8010111c <ima_cores_setup>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:438
/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
   address + 0x4. Check the mode bits. */
/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
   configured by the user at runtime */

  csrr t0, mtvec
801010f4:	305022f3          	csrr	t0,mtvec
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:439
  andi t0, t0, MTVEC_MODE_BIT_MASK
801010f8:	0032f293          	andi	t0,t0,3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:440
  li t1, MTVEC_VECTORED_MODE_VAL
801010fc:	00100313          	li	t1,1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:441
  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
80101100:	00629e63          	bne	t0,t1,8010111c <ima_cores_setup>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:445

  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
     Verify that the trap_handler address matches the configuration in MTVEC */
  csrr t0, mtvec
80101104:	305022f3          	csrr	t0,mtvec
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:446
  andi t0, t0, 0xFFFFFFFC
80101108:	ffc2f293          	andi	t0,t0,-4
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:447
  la t1, trap_entry
8010110c:	fffff317          	auipc	t1,0xfffff
80101110:	ef830313          	addi	t1,t1,-264 # 80100004 <trap_entry>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:448
  bne t0, t1, vector_address_not_matching
80101114:	04629a63          	bne	t0,t1,80101168 <vector_address_not_matching>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:449
  j generic_reset_handling
80101118:	0100006f          	j	80101128 <generic_reset_handling>

8010111c <ima_cores_setup>:
ima_cores_setup():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:476
  bne t0, t1, vector_address_not_matching
  j generic_reset_handling
#endif /*MIV_RV32_V3_0*/

ima_cores_setup:
  la t0, trap_entry
8010111c:	fffff297          	auipc	t0,0xfffff
80101120:	ee828293          	addi	t0,t0,-280 # 80100004 <trap_entry>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:482

#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
#endif
  csrw mtvec, t0
80101124:	30529073          	csrw	mtvec,t0

80101128 <generic_reset_handling>:
generic_reset_handling():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:487

generic_reset_handling:
/* Copy sdata section first so that the gp is set and linker relaxation can be
   used */
    la a4, __sdata_load
80101128:	00003717          	auipc	a4,0x3
8010112c:	be870713          	addi	a4,a4,-1048 # 80103d10 <__data_load>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:488
    la a5, __sdata_start
80101130:	efeff797          	auipc	a5,0xefeff
80101134:	ed078793          	addi	a5,a5,-304 # 70000000 <RAM_START_ADDRESS>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:489
    la a6, __sdata_end
80101138:	efeff817          	auipc	a6,0xefeff
8010113c:	ec880813          	addi	a6,a6,-312 # 70000000 <RAM_START_ADDRESS>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:490
    beq a4, a5, 1f     /* Exit if source and dest are same */
80101140:	00f70863          	beq	a4,a5,80101150 <generic_reset_handling+0x28>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:491
    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
80101144:	01078663          	beq	a5,a6,80101150 <generic_reset_handling+0x28>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:492
    call block_copy
80101148:	00000097          	auipc	ra,0x0
8010114c:	0ac080e7          	jalr	172(ra) # 801011f4 <block_copy>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:496

1:
  /* initialize global pointer */
  la gp, __global_pointer$
80101150:	efeff197          	auipc	gp,0xefeff
80101154:	6b018193          	addi	gp,gp,1712 # 70000800 <__global_pointer$>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:513
  csrw mstatus, t1

  lui t0, 0x0
  fscsr t0
#endif
  call initializations
80101158:	014000ef          	jal	ra,8010116c <initializations>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:515
  /* Initialize stack pointer */
  la sp, __stack_top
8010115c:	eff02117          	auipc	sp,0xeff02
80101160:	f5410113          	addi	sp,sp,-172 # 700030b0 <__stack_top>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:518

  /* Jump into C code */
  j _init
80101164:	4cc0006f          	j	80101630 <_init>

80101168 <vector_address_not_matching>:
vector_address_not_matching():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:523

/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
   as configured in the MIV_RV32 core vectored mode */
vector_address_not_matching:
  ebreak
80101168:	00100073          	ebreak

8010116c <initializations>:
initializations():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:527

initializations:
/* Initialize the .bss section */
    mv t0, ra           /* Store ra for future use */
8010116c:	00008293          	mv	t0,ra
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:528
    la  a5, __bss_start
80101170:	84018793          	addi	a5,gp,-1984 # 70000040 <__sbss_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:529
    la  a6, __bss_end
80101174:	eff01817          	auipc	a6,0xeff01
80101178:	f3c80813          	addi	a6,a6,-196 # 700020b0 <__bss_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:530
    beq a5, a6, 1f     /* Section start and end address are the same */
8010117c:	01078463          	beq	a5,a6,80101184 <initializations+0x18>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:531
    call zeroize_block
80101180:	054000ef          	jal	ra,801011d4 <zeroize_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:535

1:
/* Initialize the .sbss section */
    la  a5, __sbss_start
80101184:	81018793          	addi	a5,gp,-2032 # 70000010 <__data_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:536
    la  a6, __sbss_end
80101188:	84018813          	addi	a6,gp,-1984 # 70000040 <__sbss_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:537
    beq a5, a6, 1f     /* Section start and end address are the same */
8010118c:	03078063          	beq	a5,a6,801011ac <initializations+0x40>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:538
    call zeroize_block
80101190:	044000ef          	jal	ra,801011d4 <zeroize_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:541

/* Clear heap */
    la  a5, __heap_start
80101194:	eff01797          	auipc	a5,0xeff01
80101198:	f1c78793          	addi	a5,a5,-228 # 700020b0 <__bss_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:542
    la  a6, __heap_end
8010119c:	eff01817          	auipc	a6,0xeff01
801011a0:	f1480813          	addi	a6,a6,-236 # 700020b0 <__bss_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:543
    beq a5, a6, 1f     /* Section start and end address are the same */
801011a4:	01078463          	beq	a5,a6,801011ac <initializations+0x40>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:544
    call zeroize_block
801011a8:	02c000ef          	jal	ra,801011d4 <zeroize_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:548

1:
/* Copy data section */
    la  a4, __data_load
801011ac:	00003717          	auipc	a4,0x3
801011b0:	b6470713          	addi	a4,a4,-1180 # 80103d10 <__data_load>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:549
    la  a5, __data_start
801011b4:	efeff797          	auipc	a5,0xefeff
801011b8:	e4c78793          	addi	a5,a5,-436 # 70000000 <RAM_START_ADDRESS>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:550
    la  a6, __data_end
801011bc:	81018813          	addi	a6,gp,-2032 # 70000010 <__data_end>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:551
    beq a4, a5, 1f     /* Exit early if source and dest are same */
801011c0:	00f70663          	beq	a4,a5,801011cc <initializations+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:552
    beq a5, a6, 1f     /* Section start and end addresses are the same */
801011c4:	01078463          	beq	a5,a6,801011cc <initializations+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:553
    call block_copy
801011c8:	02c000ef          	jal	ra,801011f4 <block_copy>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:556

1:
    mv ra, t0           /* Retrieve ra */
801011cc:	00028093          	mv	ra,t0
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:557
    ret
801011d0:	00008067          	ret

801011d4 <zeroize_block>:
zeroize_block():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:560

zeroize_block:
    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
801011d4:	04f86463          	bltu	a6,a5,8010121c <block_copy_error>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:561
    or a7, a6, a5                   /* Check if start or end is unalined */
801011d8:	00f868b3          	or	a7,a6,a5
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:562
    andi a7, a7, 0x03u
801011dc:	0038f893          	andi	a7,a7,3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:563
    bgtz a7, block_copy_error       /* Unaligned addresses error*/
801011e0:	03104e63          	bgtz	a7,8010121c <block_copy_error>

801011e4 <zeroize_loop>:
zeroize_loop():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:565
zeroize_loop:
    sw x0, 0(a5)
801011e4:	0007a023          	sw	zero,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:566
    add a5, a5, __SIZEOF_POINTER__
801011e8:	00478793          	addi	a5,a5,4
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:567
    blt a5, a6, zeroize_loop
801011ec:	ff07cce3          	blt	a5,a6,801011e4 <zeroize_loop>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:568
    ret
801011f0:	00008067          	ret

801011f4 <block_copy>:
block_copy():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:571

block_copy:
    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
801011f4:	02f86463          	bltu	a6,a5,8010121c <block_copy_error>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:572
    or a7, a6, a5                   /* Check if start or end is unalined */
801011f8:	00f868b3          	or	a7,a6,a5
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:573
    andi a7, a7, 0x03u
801011fc:	0038f893          	andi	a7,a7,3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:574
    bgtz a7, block_copy_error       /* Unaligned addresses error*/
80101200:	01104e63          	bgtz	a7,8010121c <block_copy_error>

80101204 <block_copy_loop>:
block_copy_loop():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:576
block_copy_loop:
    lw a7, 0(a4)
80101204:	00072883          	lw	a7,0(a4)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:577
    sw a7, 0(a5)
80101208:	0117a023          	sw	a7,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:578
    addi a5, a5, 0x04
8010120c:	00478793          	addi	a5,a5,4
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:579
    addi a4, a4, 0x04
80101210:	00470713          	addi	a4,a4,4
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:580
    blt a5, a6, block_copy_loop
80101214:	ff07c8e3          	blt	a5,a6,80101204 <block_copy_loop>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:581
    j block_copy_exit
80101218:	0080006f          	j	80101220 <block_copy_exit>

8010121c <block_copy_error>:
block_copy_error():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:584

block_copy_error:
    j block_copy_error
8010121c:	0000006f          	j	8010121c <block_copy_error>

80101220 <block_copy_exit>:
block_copy_exit():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_entry.S:587

block_copy_exit:
    ret
80101220:	00008067          	ret

80101224 <MRV_read_mtime>:
MRV_read_mtime():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:684

/***************************************************************************//**
  The MRV_read_mtime() function returns the current MTIME register value.
 */
static inline uint64_t MRV_read_mtime(void)
{
80101224:	fe010113          	addi	sp,sp,-32
80101228:	00812e23          	sw	s0,28(sp)
8010122c:	02010413          	addi	s0,sp,32
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:685
    volatile uint32_t hi = 0u;
80101230:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:686
    volatile uint32_t lo = 0u;
80101234:	fe042423          	sw	zero,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:691 (discriminator 1)

    /* when mtime lower word is 0xFFFFFFFF, there will be rollover and
     * returned value could be wrong. */
    do {
        hi = MTIMEH;
80101238:	0200c537          	lui	a0,0x200c
8010123c:	ffc50513          	addi	a0,a0,-4 # 200bffc <RAM_SIZE+0x1ffbffc>
80101240:	00052503          	lw	a0,0(a0)
80101244:	fea42623          	sw	a0,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:692 (discriminator 1)
        lo = MTIME;
80101248:	0200c537          	lui	a0,0x200c
8010124c:	ff850513          	addi	a0,a0,-8 # 200bff8 <RAM_SIZE+0x1ffbff8>
80101250:	00052503          	lw	a0,0(a0)
80101254:	fea42423          	sw	a0,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:693 (discriminator 1)
    } while(hi != MTIMEH);
80101258:	0200c537          	lui	a0,0x200c
8010125c:	ffc50513          	addi	a0,a0,-4 # 200bffc <RAM_SIZE+0x1ffbffc>
80101260:	00052883          	lw	a7,0(a0)
80101264:	fec42503          	lw	a0,-20(s0)
80101268:	fca898e3          	bne	a7,a0,80101238 <MRV_read_mtime+0x14>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:695

    return((((uint64_t)MTIMEH) << 32u) | lo);
8010126c:	0200c537          	lui	a0,0x200c
80101270:	ffc50513          	addi	a0,a0,-4 # 200bffc <RAM_SIZE+0x1ffbffc>
80101274:	00052503          	lw	a0,0(a0)
80101278:	00050313          	mv	t1,a0
8010127c:	00000393          	li	t2,0
80101280:	00031813          	slli	a6,t1,0x0
80101284:	00000793          	li	a5,0
80101288:	fe842503          	lw	a0,-24(s0)
8010128c:	00050693          	mv	a3,a0
80101290:	00000713          	li	a4,0
80101294:	00d7e5b3          	or	a1,a5,a3
80101298:	00e86633          	or	a2,a6,a4
8010129c:	00058793          	mv	a5,a1
801012a0:	00060813          	mv	a6,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:696
}
801012a4:	00078513          	mv	a0,a5
801012a8:	00080593          	mv	a1,a6
801012ac:	01c12403          	lw	s0,28(sp)
801012b0:	02010113          	addi	sp,sp,32
801012b4:	00008067          	ret

801012b8 <MRV_clear_soft_irq>:
MRV_clear_soft_irq():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:730

  @return
  This function does not return any value.
 */
static inline void MRV_clear_soft_irq(void)
{
801012b8:	ff010113          	addi	sp,sp,-16
801012bc:	00812623          	sw	s0,12(sp)
801012c0:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:735
#ifdef MIV_LEGACY_RV32
    MSIP = 0x00u;   /* clear soft interrupt */
#else
    /* Clear soft IRQ on MIV_RV32 processor */
    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
801012c4:	000067b7          	lui	a5,0x6
801012c8:	0207a703          	lw	a4,32(a5) # 6020 <STACK_SIZE+0x5020>
801012cc:	000067b7          	lui	a5,0x6
801012d0:	ffd77713          	andi	a4,a4,-3
801012d4:	02e7a023          	sw	a4,32(a5) # 6020 <STACK_SIZE+0x5020>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.h:737
#endif
}
801012d8:	00000013          	nop
801012dc:	00c12403          	lw	s0,12(sp)
801012e0:	01010113          	addi	sp,sp,16
801012e4:	00008067          	ret

801012e8 <handle_m_timer_interrupt>:
handle_m_timer_interrupt():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:192

/*------------------------------------------------------------------------------
 * RISC-V interrupt handler for machine timer interrupts.
 */
void handle_m_timer_interrupt(void)
{
801012e8:	fd010113          	addi	sp,sp,-48
801012ec:	02112623          	sw	ra,44(sp)
801012f0:	02812423          	sw	s0,40(sp)
801012f4:	03212223          	sw	s2,36(sp)
801012f8:	03312023          	sw	s3,32(sp)
801012fc:	03010413          	addi	s0,sp,48
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:193
    clear_csr(mie, MIP_MTIP);
80101300:	08000793          	li	a5,128
80101304:	3047b7f3          	csrrc	a5,mie,a5
80101308:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:195

    uint64_t mtime_at_irq = MRV_read_mtime();
8010130c:	f19ff0ef          	jal	ra,80101224 <MRV_read_mtime>
80101310:	fea42023          	sw	a0,-32(s0)
80101314:	feb42223          	sw	a1,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:201

#ifndef NDEBUG
    static volatile uint32_t d_tick = 0u;
#endif

    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
80101318:	04c0006f          	j	80101364 <handle_m_timer_interrupt+0x7c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:202
        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
8010131c:	81c1a803          	lw	a6,-2020(gp) # 7000001c <g_systick_cmp_value+0x4>
80101320:	8181a783          	lw	a5,-2024(gp) # 70000018 <g_systick_cmp_value>
80101324:	70000737          	lui	a4,0x70000
80101328:	01072583          	lw	a1,16(a4) # 70000010 <__data_end>
8010132c:	8141a603          	lw	a2,-2028(gp) # 70000014 <__data_end+0x4>
80101330:	00b786b3          	add	a3,a5,a1
80101334:	00068513          	mv	a0,a3
80101338:	00f53533          	sltu	a0,a0,a5
8010133c:	00c80733          	add	a4,a6,a2
80101340:	00e507b3          	add	a5,a0,a4
80101344:	00078713          	mv	a4,a5
80101348:	00068793          	mv	a5,a3
8010134c:	00070813          	mv	a6,a4
80101350:	80f1ac23          	sw	a5,-2024(gp) # 70000018 <g_systick_cmp_value>
80101354:	8101ae23          	sw	a6,-2020(gp) # 7000001c <g_systick_cmp_value+0x4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:205

#ifndef NDEBUG
        d_tick += 1;
80101358:	8201a783          	lw	a5,-2016(gp) # 70000020 <d_tick.2196>
8010135c:	00178713          	addi	a4,a5,1
80101360:	82e1a023          	sw	a4,-2016(gp) # 70000020 <d_tick.2196>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:201
    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
80101364:	fe042783          	lw	a5,-32(s0)
80101368:	fe442803          	lw	a6,-28(s0)
8010136c:	00500593          	li	a1,5
80101370:	00000613          	li	a2,0
80101374:	00b786b3          	add	a3,a5,a1
80101378:	00068513          	mv	a0,a3
8010137c:	00f53533          	sltu	a0,a0,a5
80101380:	00c80733          	add	a4,a6,a2
80101384:	00e507b3          	add	a5,a0,a4
80101388:	00078713          	mv	a4,a5
8010138c:	81c1a803          	lw	a6,-2020(gp) # 7000001c <g_systick_cmp_value+0x4>
80101390:	8181a783          	lw	a5,-2024(gp) # 70000018 <g_systick_cmp_value>
80101394:	00070593          	mv	a1,a4
80101398:	00080613          	mv	a2,a6
8010139c:	f8b660e3          	bltu	a2,a1,8010131c <handle_m_timer_interrupt+0x34>
801013a0:	00070593          	mv	a1,a4
801013a4:	00080613          	mv	a2,a6
801013a8:	00c59663          	bne	a1,a2,801013b4 <handle_m_timer_interrupt+0xcc>
801013ac:	00068713          	mv	a4,a3
801013b0:	f6e7e6e3          	bltu	a5,a4,8010131c <handle_m_timer_interrupt+0x34>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:223
     * If you are running the program using the debugger and halt the CPU at a 
     * breakpoint, MTIME will continue to increment and interrupts will be 
     * missed; resulting in d_tick > 1.
     */

    WRITE_MTIMECMP(g_systick_cmp_value);
801013b4:	020047b7          	lui	a5,0x2004
801013b8:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ff4004>
801013bc:	fff00713          	li	a4,-1
801013c0:	00e7a023          	sw	a4,0(a5)
801013c4:	81c1a803          	lw	a6,-2020(gp) # 7000001c <g_systick_cmp_value+0x4>
801013c8:	8181a783          	lw	a5,-2024(gp) # 70000018 <g_systick_cmp_value>
801013cc:	02004737          	lui	a4,0x2004
801013d0:	00f72023          	sw	a5,0(a4) # 2004000 <RAM_SIZE+0x1ff4000>
801013d4:	81c1a803          	lw	a6,-2020(gp) # 7000001c <g_systick_cmp_value+0x4>
801013d8:	8181a783          	lw	a5,-2024(gp) # 70000018 <g_systick_cmp_value>
801013dc:	00085913          	srli	s2,a6,0x0
801013e0:	00000993          	li	s3,0
801013e4:	020047b7          	lui	a5,0x2004
801013e8:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ff4004>
801013ec:	00090713          	mv	a4,s2
801013f0:	00e7a023          	sw	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:225

    SysTick_Handler();
801013f4:	298000ef          	jal	ra,8010168c <SysTick_Handler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:227

    set_csr(mie, MIP_MTIP);
801013f8:	08000793          	li	a5,128
801013fc:	3047a7f3          	csrrs	a5,mie,a5
80101400:	fcf42e23          	sw	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:228
}
80101404:	00000013          	nop
80101408:	02c12083          	lw	ra,44(sp)
8010140c:	02812403          	lw	s0,40(sp)
80101410:	02412903          	lw	s2,36(sp)
80101414:	02012983          	lw	s3,32(sp)
80101418:	03010113          	addi	sp,sp,48
8010141c:	00008067          	ret

80101420 <handle_m_soft_interrupt>:
handle_m_soft_interrupt():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:231

void handle_m_soft_interrupt(void)
{
80101420:	ff010113          	addi	sp,sp,-16
80101424:	00112623          	sw	ra,12(sp)
80101428:	00812423          	sw	s0,8(sp)
8010142c:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:232
    Software_IRQHandler();
80101430:	244000ef          	jal	ra,80101674 <Software_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:233
    MRV_clear_soft_irq();
80101434:	e85ff0ef          	jal	ra,801012b8 <MRV_clear_soft_irq>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:234
}
80101438:	00000013          	nop
8010143c:	00c12083          	lw	ra,12(sp)
80101440:	00812403          	lw	s0,8(sp)
80101444:	01010113          	addi	sp,sp,16
80101448:	00008067          	ret

8010144c <handle_local_ei_interrupts>:
handle_local_ei_interrupts():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:305

/*------------------------------------------------------------------------------
 * Jump to interrupt table containing local interrupts
 */
void handle_local_ei_interrupts(uint8_t irq_no)
{
8010144c:	fc010113          	addi	sp,sp,-64
80101450:	02112e23          	sw	ra,60(sp)
80101454:	02812c23          	sw	s0,56(sp)
80101458:	04010413          	addi	s0,sp,64
8010145c:	00050793          	mv	a5,a0
80101460:	fcf407a3          	sb	a5,-49(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:306
    uint64_t mhart_id = read_csr(mhartid);
80101464:	f14027f3          	csrr	a5,mhartid
80101468:	fef42623          	sw	a5,-20(s0)
8010146c:	fec42783          	lw	a5,-20(s0)
80101470:	fef42023          	sw	a5,-32(s0)
80101474:	fe042223          	sw	zero,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:307
    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
80101478:	fcf44703          	lbu	a4,-49(s0)
8010147c:	01f00793          	li	a5,31
80101480:	00e7f463          	bgeu	a5,a4,80101488 <handle_local_ei_interrupts+0x3c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:307 (discriminator 1)
80101484:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:308
    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
80101488:	fcf44703          	lbu	a4,-49(s0)
8010148c:	00f00793          	li	a5,15
80101490:	00e7e463          	bltu	a5,a4,80101498 <handle_local_ei_interrupts+0x4c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:308 (discriminator 1)
80101494:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:310

    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
80101498:	fcf44783          	lbu	a5,-49(s0)
8010149c:	ff078793          	addi	a5,a5,-16
801014a0:	fcf40fa3          	sb	a5,-33(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:311
    (*local_irq_handler_table[ei_no])();
801014a4:	fdf44783          	lbu	a5,-33(s0)
801014a8:	80104737          	lui	a4,0x80104
801014ac:	8d070713          	addi	a4,a4,-1840 # 801038d0 <__data_load+0xfffffbc0>
801014b0:	00279793          	slli	a5,a5,0x2
801014b4:	00f707b3          	add	a5,a4,a5
801014b8:	0007a783          	lw	a5,0(a5)
801014bc:	000780e7          	jalr	a5
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:312
}
801014c0:	00000013          	nop
801014c4:	03c12083          	lw	ra,60(sp)
801014c8:	03812403          	lw	s0,56(sp)
801014cc:	04010113          	addi	sp,sp,64
801014d0:	00008067          	ret

801014d4 <handle_trap>:
handle_trap():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:320

/*------------------------------------------------------------------------------
 * Trap handler. This function is invoked in the non-vectored mode.
 */
void handle_trap(uintptr_t mcause, uintptr_t mepc)
{   
801014d4:	fa010113          	addi	sp,sp,-96
801014d8:	04112e23          	sw	ra,92(sp)
801014dc:	04812c23          	sw	s0,88(sp)
801014e0:	06010413          	addi	s0,sp,96
801014e4:	faa42623          	sw	a0,-84(s0)
801014e8:	fab42423          	sw	a1,-88(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:321
    uint64_t is_interrupt = mcause & MCAUSE_INT;
801014ec:	fac42703          	lw	a4,-84(s0)
801014f0:	00070793          	mv	a5,a4
801014f4:	00000813          	li	a6,0
801014f8:	80000737          	lui	a4,0x80000
801014fc:	00e7f733          	and	a4,a5,a4
80101500:	fee42423          	sw	a4,-24(s0)
80101504:	00087793          	andi	a5,a6,0
80101508:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:323

    if (is_interrupt)
8010150c:	fe842783          	lw	a5,-24(s0)
80101510:	fec42703          	lw	a4,-20(s0)
80101514:	00e7e7b3          	or	a5,a5,a4
80101518:	0a078063          	beqz	a5,801015b8 <handle_trap+0xe4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:326
    {
#ifndef MIV_LEGACY_RV32
        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
8010151c:	fac42703          	lw	a4,-84(s0)
80101520:	800007b7          	lui	a5,0x80000
80101524:	ff07c793          	xori	a5,a5,-16
80101528:	00f777b3          	and	a5,a4,a5
8010152c:	02078663          	beqz	a5,80101558 <handle_trap+0x84>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
80101530:	fac42703          	lw	a4,-84(s0)
80101534:	800007b7          	lui	a5,0x80000
80101538:	fe07c793          	xori	a5,a5,-32
8010153c:	00f777b3          	and	a5,a4,a5
80101540:	00079c63          	bnez	a5,80101558 <handle_trap+0x84>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:328
        {
            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
80101544:	fac42783          	lw	a5,-84(s0)
80101548:	0ff7f793          	andi	a5,a5,255
8010154c:	00078513          	mv	a0,a5
80101550:	efdff0ef          	jal	ra,8010144c <handle_local_ei_interrupts>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:405
        __asm__("ebreak");
#else
        _exit(1 + mcause);
#endif  /* NDEBUG */
    }
}
80101554:	0c80006f          	j	8010161c <handle_trap+0x148>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:330
        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
80101558:	fac42703          	lw	a4,-84(s0)
8010155c:	800007b7          	lui	a5,0x80000
80101560:	fff7c793          	not	a5,a5
80101564:	00f77733          	and	a4,a4,a5
80101568:	00b00793          	li	a5,11
8010156c:	00f71663          	bne	a4,a5,80101578 <handle_trap+0xa4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:336
            External_IRQHandler();
80101570:	138000ef          	jal	ra,801016a8 <External_IRQHandler>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:405
}
80101574:	0a80006f          	j	8010161c <handle_trap+0x148>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:341
        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
80101578:	fac42703          	lw	a4,-84(s0)
8010157c:	800007b7          	lui	a5,0x80000
80101580:	fff7c793          	not	a5,a5
80101584:	00f77733          	and	a4,a4,a5
80101588:	00300793          	li	a5,3
8010158c:	00f71663          	bne	a4,a5,80101598 <handle_trap+0xc4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:343
            handle_m_soft_interrupt();
80101590:	e91ff0ef          	jal	ra,80101420 <handle_m_soft_interrupt>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:405
}
80101594:	0880006f          	j	8010161c <handle_trap+0x148>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:345
        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
80101598:	fac42703          	lw	a4,-84(s0)
8010159c:	800007b7          	lui	a5,0x80000
801015a0:	fff7c793          	not	a5,a5
801015a4:	00f77733          	and	a4,a4,a5
801015a8:	00700793          	li	a5,7
801015ac:	06f71863          	bne	a4,a5,8010161c <handle_trap+0x148>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:347
            handle_m_timer_interrupt();
801015b0:	d39ff0ef          	jal	ra,801012e8 <handle_m_timer_interrupt>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:405
}
801015b4:	0680006f          	j	8010161c <handle_trap+0x148>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:382
         uintptr_t mip      = read_csr(mip);
801015b8:	344027f3          	csrr	a5,mip
801015bc:	fef42223          	sw	a5,-28(s0)
801015c0:	fe442783          	lw	a5,-28(s0)
801015c4:	fef42023          	sw	a5,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:385
         uintptr_t mtval = read_csr(mtval);
801015c8:	343027f3          	csrr	a5,mtval
801015cc:	fcf42e23          	sw	a5,-36(s0)
801015d0:	fdc42783          	lw	a5,-36(s0)
801015d4:	fcf42c23          	sw	a5,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:388
         uintptr_t mtvec    = read_csr(mtvec);
801015d8:	305027f3          	csrr	a5,mtvec
801015dc:	fcf42a23          	sw	a5,-44(s0)
801015e0:	fd442783          	lw	a5,-44(s0)
801015e4:	fcf42823          	sw	a5,-48(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:391
         uintptr_t mscratch = read_csr(mscratch);
801015e8:	340027f3          	csrr	a5,mscratch
801015ec:	fcf42623          	sw	a5,-52(s0)
801015f0:	fcc42783          	lw	a5,-52(s0)
801015f4:	fcf42423          	sw	a5,-56(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:394
         uintptr_t mstatus  = read_csr(mstatus);
801015f8:	300027f3          	csrr	a5,mstatus
801015fc:	fcf42223          	sw	a5,-60(s0)
80101600:	fc442783          	lw	a5,-60(s0)
80101604:	fcf42023          	sw	a5,-64(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:397
         uintptr_t mmepc  = read_csr(mepc);
80101608:	341027f3          	csrr	a5,mepc
8010160c:	faf42e23          	sw	a5,-68(s0)
80101610:	fbc42783          	lw	a5,-68(s0)
80101614:	faf42c23          	sw	a5,-72(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:400
        __asm__("ebreak");
80101618:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_hal.c:405
}
8010161c:	00000013          	nop
80101620:	05c12083          	lw	ra,92(sp)
80101624:	05812403          	lw	s0,88(sp)
80101628:	06010113          	addi	sp,sp,96
8010162c:	00008067          	ret

80101630 <_init>:
_init():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_init.c:21
#endif

extern void main(void);

void _init(void)
{
80101630:	ff010113          	addi	sp,sp,-16
80101634:	00112623          	sw	ra,12(sp)
80101638:	00812423          	sw	s0,8(sp)
8010163c:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_init.c:27
    /* This function is a placeholder for the case where some more hardware
     * specific initializations are required before jumping into the application
     * code. You can implement it here. */

    /* Jump to the application code after all initializations are completed */
    main();
80101640:	0ec020ef          	jal	ra,8010372c <main>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_init.c:28
}
80101644:	00000013          	nop
80101648:	00c12083          	lw	ra,12(sp)
8010164c:	00812403          	lw	s0,8(sp)
80101650:	01010113          	addi	sp,sp,16
80101654:	00008067          	ret

80101658 <_fini>:
_fini():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_init.c:33

/* Function called after main() finishes */
void
_fini(void)
{
80101658:	ff010113          	addi	sp,sp,-16
8010165c:	00812623          	sw	s0,12(sp)
80101660:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_init.c:34
}
80101664:	00000013          	nop
80101668:	00c12403          	lw	s0,12(sp)
8010166c:	01010113          	addi	sp,sp,16
80101670:	00008067          	ret

80101674 <Software_IRQHandler>:
Software_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:23
#ifdef __cplusplus
extern "C" {
#endif

__attribute__((weak)) void Software_IRQHandler(void)
{
80101674:	ff010113          	addi	sp,sp,-16
80101678:	00112623          	sw	ra,12(sp)
8010167c:	00812423          	sw	s0,8(sp)
80101680:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:24
    _exit(10);
80101684:	00a00513          	li	a0,10
80101688:	1a4000ef          	jal	ra,8010182c <_exit>

8010168c <SysTick_Handler>:
SysTick_Handler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:28
}

__attribute__((weak)) void SysTick_Handler(void)
{
8010168c:	ff010113          	addi	sp,sp,-16
80101690:	00812623          	sw	s0,12(sp)
80101694:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:30
    /* Default handler */
}
80101698:	00000013          	nop
8010169c:	00c12403          	lw	s0,12(sp)
801016a0:	01010113          	addi	sp,sp,16
801016a4:	00008067          	ret

801016a8 <External_IRQHandler>:
External_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:195
    return(0U); /* Default handler */
}

#else
__attribute__((weak)) void External_IRQHandler(void)
{
801016a8:	ff010113          	addi	sp,sp,-16
801016ac:	00812623          	sw	s0,12(sp)
801016b0:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:196
}
801016b4:	00000013          	nop
801016b8:	00c12403          	lw	s0,12(sp)
801016bc:	01010113          	addi	sp,sp,16
801016c0:	00008067          	ret

801016c4 <MGECI_IRQHandler>:
MGECI_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:198
__attribute__((weak)) void MGECI_IRQHandler(void)
{
801016c4:	ff010113          	addi	sp,sp,-16
801016c8:	00812623          	sw	s0,12(sp)
801016cc:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:199
}
801016d0:	00000013          	nop
801016d4:	00c12403          	lw	s0,12(sp)
801016d8:	01010113          	addi	sp,sp,16
801016dc:	00008067          	ret

801016e0 <MGEUI_IRQHandler>:
MGEUI_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:201
__attribute__((weak)) void MGEUI_IRQHandler(void)
{
801016e0:	ff010113          	addi	sp,sp,-16
801016e4:	00812623          	sw	s0,12(sp)
801016e8:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:202
}
801016ec:	00000013          	nop
801016f0:	00c12403          	lw	s0,12(sp)
801016f4:	01010113          	addi	sp,sp,16
801016f8:	00008067          	ret

801016fc <SUBSYS_IRQHandler>:
SUBSYS_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:204
__attribute__((weak)) void SUBSYS_IRQHandler(void)
{
801016fc:	ff010113          	addi	sp,sp,-16
80101700:	00812623          	sw	s0,12(sp)
80101704:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:205
}
80101708:	00000013          	nop
8010170c:	00c12403          	lw	s0,12(sp)
80101710:	01010113          	addi	sp,sp,16
80101714:	00008067          	ret

80101718 <MSYS_EI0_IRQHandler>:
MSYS_EI0_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:207
__attribute__((weak)) void MSYS_EI0_IRQHandler(void)
{
80101718:	ff010113          	addi	sp,sp,-16
8010171c:	00812623          	sw	s0,12(sp)
80101720:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:208
}
80101724:	00000013          	nop
80101728:	00c12403          	lw	s0,12(sp)
8010172c:	01010113          	addi	sp,sp,16
80101730:	00008067          	ret

80101734 <MSYS_EI1_IRQHandler>:
MSYS_EI1_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:210
__attribute__((weak)) void MSYS_EI1_IRQHandler(void)
{
80101734:	ff010113          	addi	sp,sp,-16
80101738:	00812623          	sw	s0,12(sp)
8010173c:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:211
}
80101740:	00000013          	nop
80101744:	00c12403          	lw	s0,12(sp)
80101748:	01010113          	addi	sp,sp,16
8010174c:	00008067          	ret

80101750 <MSYS_EI2_IRQHandler>:
MSYS_EI2_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:213
__attribute__((weak)) void MSYS_EI2_IRQHandler(void)
{
80101750:	ff010113          	addi	sp,sp,-16
80101754:	00812623          	sw	s0,12(sp)
80101758:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:214
}
8010175c:	00000013          	nop
80101760:	00c12403          	lw	s0,12(sp)
80101764:	01010113          	addi	sp,sp,16
80101768:	00008067          	ret

8010176c <MSYS_EI3_IRQHandler>:
MSYS_EI3_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:216
__attribute__((weak)) void MSYS_EI3_IRQHandler(void)
{
8010176c:	ff010113          	addi	sp,sp,-16
80101770:	00812623          	sw	s0,12(sp)
80101774:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:217
}
80101778:	00000013          	nop
8010177c:	00c12403          	lw	s0,12(sp)
80101780:	01010113          	addi	sp,sp,16
80101784:	00008067          	ret

80101788 <MSYS_EI4_IRQHandler>:
MSYS_EI4_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:219
__attribute__((weak)) void MSYS_EI4_IRQHandler(void)
{
80101788:	ff010113          	addi	sp,sp,-16
8010178c:	00812623          	sw	s0,12(sp)
80101790:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:220
}
80101794:	00000013          	nop
80101798:	00c12403          	lw	s0,12(sp)
8010179c:	01010113          	addi	sp,sp,16
801017a0:	00008067          	ret

801017a4 <MSYS_EI5_IRQHandler>:
MSYS_EI5_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:222
__attribute__((weak)) void MSYS_EI5_IRQHandler(void)
{
801017a4:	ff010113          	addi	sp,sp,-16
801017a8:	00812623          	sw	s0,12(sp)
801017ac:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:223
}
801017b0:	00000013          	nop
801017b4:	00c12403          	lw	s0,12(sp)
801017b8:	01010113          	addi	sp,sp,16
801017bc:	00008067          	ret

801017c0 <Reserved_IRQHandler>:
Reserved_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:225
__attribute__((weak)) void Reserved_IRQHandler(void)
{
801017c0:	ff010113          	addi	sp,sp,-16
801017c4:	00112623          	sw	ra,12(sp)
801017c8:	00812423          	sw	s0,8(sp)
801017cc:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:226
    _exit(10);
801017d0:	00a00513          	li	a0,10
801017d4:	058000ef          	jal	ra,8010182c <_exit>

801017d8 <MSYS_EI6_IRQHandler>:
MSYS_EI6_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:230
}
#ifndef MIV_RV32_V3_0 /* For MIV_RV32 v3.0 */
__attribute__((weak)) void MSYS_EI6_IRQHandler(void)
{
801017d8:	ff010113          	addi	sp,sp,-16
801017dc:	00812623          	sw	s0,12(sp)
801017e0:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:231
}
801017e4:	00000013          	nop
801017e8:	00c12403          	lw	s0,12(sp)
801017ec:	01010113          	addi	sp,sp,16
801017f0:	00008067          	ret

801017f4 <MSYS_EI7_IRQHandler>:
MSYS_EI7_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:233
__attribute__((weak)) void MSYS_EI7_IRQHandler(void)
{
801017f4:	ff010113          	addi	sp,sp,-16
801017f8:	00812623          	sw	s0,12(sp)
801017fc:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:234
}
80101800:	00000013          	nop
80101804:	00c12403          	lw	s0,12(sp)
80101808:	01010113          	addi	sp,sp,16
8010180c:	00008067          	ret

80101810 <SUBSYSR_IRQHandler>:
SUBSYSR_IRQHandler():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:236
__attribute__((weak)) void SUBSYSR_IRQHandler(void)
{
80101810:	ff010113          	addi	sp,sp,-16
80101814:	00812623          	sw	s0,12(sp)
80101818:	01010413          	addi	s0,sp,16
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_stubs.c:237
}
8010181c:	00000013          	nop
80101820:	00c12403          	lw	s0,12(sp)
80101824:	01010113          	addi	sp,sp,16
80101828:	00008067          	ret

8010182c <_exit>:
_exit():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_syscall.c:142
#ifdef GDB_TESTING
void __attribute__((optimize("O0"))) _exit(int code)
#else
void _exit(int code)
#endif
{
8010182c:	fe010113          	addi	sp,sp,-32
80101830:	00812e23          	sw	s0,28(sp)
80101834:	02010413          	addi	s0,sp,32
80101838:	fea42623          	sw	a0,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)

    write(STDERR_FILENO, message, strlen(message));
    write_hex(STDERR_FILENO, code);
#endif

    while (1){};
8010183c:	0000006f          	j	8010183c <_exit+0x10>

80101840 <HW_set_32bit_reg>:
HW_set_32bit_reg():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:39
 *
 * a0:   addr_t reg_addr
 * a1:   uint32_t value
 */
HW_set_32bit_reg:
    sw a1, 0(a0)
80101840:	00b52023          	sw	a1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:40
    ret
80101844:	00008067          	ret

80101848 <HW_get_32bit_reg>:
HW_get_32bit_reg():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:51
 * a0:   addr_t reg_addr

 * @return          32 bits value read from the peripheral register.
 */
HW_get_32bit_reg:
    lw a0, 0(a0)
80101848:	00052503          	lw	a0,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:52
    ret
8010184c:	00008067          	ret

80101850 <HW_set_32bit_reg_field>:
HW_set_32bit_reg_field():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:64
 * a1:   int_fast8_t shift
 * a2:   uint32_t mask
 * a3:   uint32_t value
 */
HW_set_32bit_reg_field:
    mv t3, a3
80101850:	00068e13          	mv	t3,a3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:65
    sll t3, t3, a1
80101854:	00be1e33          	sll	t3,t3,a1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:66
    and  t3, t3, a2
80101858:	00ce7e33          	and	t3,t3,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:67
    lw t1, 0(a0)
8010185c:	00052303          	lw	t1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:68
    mv t2, a2
80101860:	00060393          	mv	t2,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:69
    not t2, t2
80101864:	fff3c393          	not	t2,t2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:70
    and t1, t1, t2
80101868:	00737333          	and	t1,t1,t2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:71
    or t1, t1, t3
8010186c:	01c36333          	or	t1,t1,t3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:72
    sw t1, 0(a0)
80101870:	00652023          	sw	t1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:73
    ret
80101874:	00008067          	ret

80101878 <HW_get_32bit_reg_field>:
HW_get_32bit_reg_field():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:87
 *
 * @return          32 bits value containing the register field value specified
 *                  as parameter.
 */
HW_get_32bit_reg_field:
    lw a0, 0(a0)
80101878:	00052503          	lw	a0,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:88
    and a0, a0, a2
8010187c:	00c57533          	and	a0,a0,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:89
    srl a0, a0, a1
80101880:	00b55533          	srl	a0,a0,a1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:90
    ret
80101884:	00008067          	ret

80101888 <HW_set_16bit_reg>:
HW_set_16bit_reg():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:100
 *
 * a0:   addr_t reg_addr
 * a1:   uint_fast16_t value
 */
HW_set_16bit_reg:
    sh a1, 0(a0)
80101888:	00b51023          	sh	a1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:101
    ret
8010188c:	00008067          	ret

80101890 <HW_get_16bit_reg>:
HW_get_16bit_reg():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:112
 * a0:   addr_t reg_addr

 * @return          16 bits value read from the peripheral register.
 */
HW_get_16bit_reg:
    lh a0, (a0)
80101890:	00051503          	lh	a0,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:113
    ret
80101894:	00008067          	ret

80101898 <HW_set_16bit_reg_field>:
HW_set_16bit_reg_field():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:126
 * a2:   uint_fast16_t mask
 * a3:   uint_fast16_t value
 * @param value     Value to be written in the specified field.
 */
HW_set_16bit_reg_field:
    mv t3, a3
80101898:	00068e13          	mv	t3,a3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:127
    sll t3, t3, a1
8010189c:	00be1e33          	sll	t3,t3,a1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:128
    and  t3, t3, a2
801018a0:	00ce7e33          	and	t3,t3,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:129
    lh t1, 0(a0)
801018a4:	00051303          	lh	t1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:130
    mv t2, a2
801018a8:	00060393          	mv	t2,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:131
    not t2, t2
801018ac:	fff3c393          	not	t2,t2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:132
    and t1, t1, t2
801018b0:	00737333          	and	t1,t1,t2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:133
    or t1, t1, t3
801018b4:	01c36333          	or	t1,t1,t3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:134
    sh t1, 0(a0)
801018b8:	00651023          	sh	t1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:135
    ret
801018bc:	00008067          	ret

801018c0 <HW_get_16bit_reg_field>:
HW_get_16bit_reg_field():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:149
 *
 * @return          16 bits value containing the register field value specified
 *                  as parameter.
 */
HW_get_16bit_reg_field:
    lh a0, 0(a0)
801018c0:	00051503          	lh	a0,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:150
    and a0, a0, a2
801018c4:	00c57533          	and	a0,a0,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:151
    srl a0, a0, a1
801018c8:	00b55533          	srl	a0,a0,a1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:152
    ret
801018cc:	00008067          	ret

801018d0 <HW_set_8bit_reg>:
HW_set_8bit_reg():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:162
 *
 * a0:   addr_t reg_addr
 * a1:   uint_fast8_t value
 */
HW_set_8bit_reg:
    sb a1, 0(a0)
801018d0:	00b50023          	sb	a1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:163
    ret
801018d4:	00008067          	ret

801018d8 <HW_get_8bit_reg>:
HW_get_8bit_reg():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:174
 * a0:   addr_t reg_addr

 * @return          8 bits value read from the peripheral register.
 */
HW_get_8bit_reg:
    lb a0, 0(a0)
801018d8:	00050503          	lb	a0,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:175
    ret
801018dc:	00008067          	ret

801018e0 <HW_set_8bit_reg_field>:
HW_set_8bit_reg_field():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:187
 * a1:   int_fast8_t shift
 * a2:   uint_fast8_t mask
 * a3:   uint_fast8_t value
 */
HW_set_8bit_reg_field:
    mv t3, a3
801018e0:	00068e13          	mv	t3,a3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:188
    sll t3, t3, a1
801018e4:	00be1e33          	sll	t3,t3,a1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:189
    and  t3, t3, a2
801018e8:	00ce7e33          	and	t3,t3,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:190
    lb t1, 0(a0)
801018ec:	00050303          	lb	t1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:191
    mv t2, a2
801018f0:	00060393          	mv	t2,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:192
    not t2, t2
801018f4:	fff3c393          	not	t2,t2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:193
    and t1, t1, t2
801018f8:	00737333          	and	t1,t1,t2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:194
    or t1, t1, t3
801018fc:	01c36333          	or	t1,t1,t3
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:195
    sb t1, 0(a0)
80101900:	00650023          	sb	t1,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:196
    ret
80101904:	00008067          	ret

80101908 <HW_get_8bit_reg_field>:
HW_get_8bit_reg_field():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:210
 *
 * @return          8 bits value containing the register field value specified
 *                  as parameter.
 */
HW_get_8bit_reg_field:
    lb a0, 0(a0)
80101908:	00050503          	lb	a0,0(a0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:211
    and a0, a0, a2
8010190c:	00c57533          	and	a0,a0,a2
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:212
    srl a0, a0, a1
80101910:	00b55533          	srl	a0,a0,a1
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../hal/hw_reg_access.S:213
    ret
80101914:	00008067          	ret

80101918 <UART_init>:
UART_init():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:46
    UART_instance_t * this_uart,
    addr_t base_addr,
    uint16_t baud_value,
    uint8_t line_config
)
{
80101918:	fd010113          	addi	sp,sp,-48
8010191c:	02112623          	sw	ra,44(sp)
80101920:	02812423          	sw	s0,40(sp)
80101924:	03010413          	addi	s0,sp,48
80101928:	fca42e23          	sw	a0,-36(s0)
8010192c:	fcb42c23          	sw	a1,-40(s0)
80101930:	00060793          	mv	a5,a2
80101934:	00068713          	mv	a4,a3
80101938:	fcf41b23          	sh	a5,-42(s0)
8010193c:	00070793          	mv	a5,a4
80101940:	fcf40aa3          	sb	a5,-43(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:49
    uint8_t rx_full;
    
    HAL_ASSERT( this_uart != NULL_INSTANCE )
80101944:	fdc42783          	lw	a5,-36(s0)
80101948:	00079463          	bnez	a5,80101950 <UART_init+0x38>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:49 (discriminator 1)
8010194c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:50
    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
80101950:	fd544703          	lbu	a4,-43(s0)
80101954:	00700793          	li	a5,7
80101958:	00e7f463          	bgeu	a5,a4,80101960 <UART_init+0x48>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:50 (discriminator 1)
8010195c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:51
    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
80101960:	fd645703          	lhu	a4,-42(s0)
80101964:	000027b7          	lui	a5,0x2
80101968:	00f76463          	bltu	a4,a5,80101970 <UART_init+0x58>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:51 (discriminator 1)
8010196c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:53

    if( ( this_uart != NULL_INSTANCE ) &&
80101970:	fdc42783          	lw	a5,-36(s0)
80101974:	16078463          	beqz	a5,80101adc <UART_init+0x1c4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
80101978:	fd544703          	lbu	a4,-43(s0)
8010197c:	00700793          	li	a5,7
80101980:	14e7ee63          	bltu	a5,a4,80101adc <UART_init+0x1c4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:54
        ( line_config <= MAX_LINE_CONFIG ) &&
80101984:	fd645703          	lhu	a4,-42(s0)
80101988:	000027b7          	lui	a5,0x2
8010198c:	14f77863          	bgeu	a4,a5,80101adc <UART_init+0x1c4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:60
        ( baud_value <= MAX_BAUD_VALUE ) )
    {
        /*
         * Store lower 8-bits of baud value in CTRL1.
         */
        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
80101990:	fd842783          	lw	a5,-40(s0)
80101994:	00878713          	addi	a4,a5,8 # 2008 <STACK_SIZE+0x1008>
80101998:	fd645783          	lhu	a5,-42(s0)
8010199c:	0ff7f793          	andi	a5,a5,255
801019a0:	00078593          	mv	a1,a5
801019a4:	00070513          	mv	a0,a4
801019a8:	f29ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:67
    
        /*
         * Extract higher 5-bits of baud value and store in higher 5-bits 
         * of CTRL2, along with line configuration in lower 3 three bits.
         */
        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
801019ac:	fd842783          	lw	a5,-40(s0)
801019b0:	00c78693          	addi	a3,a5,12
801019b4:	fd544703          	lbu	a4,-43(s0)
801019b8:	fd645783          	lhu	a5,-42(s0)
801019bc:	4057d793          	srai	a5,a5,0x5
801019c0:	7f87f793          	andi	a5,a5,2040
801019c4:	00f767b3          	or	a5,a4,a5
801019c8:	00078593          	mv	a1,a5
801019cc:	00068513          	mv	a0,a3
801019d0:	f01ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:71
                                           (uint_fast8_t)((baud_value &
                                   BAUDVALUE_MSB) >> BAUDVALUE_SHIFT ) );
    
        this_uart->base_address = base_addr;
801019d4:	fdc42783          	lw	a5,-36(s0)
801019d8:	fd842703          	lw	a4,-40(s0)
801019dc:	00e7a023          	sw	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:77
#ifndef NDEBUG
        {
            uint8_t  config;
            uint8_t  temp;
            uint16_t baud_val;
            baud_val = HAL_get_8bit_reg( this_uart->base_address, CTRL1 );
801019e0:	fdc42783          	lw	a5,-36(s0)
801019e4:	0007a783          	lw	a5,0(a5)
801019e8:	00878793          	addi	a5,a5,8
801019ec:	00078513          	mv	a0,a5
801019f0:	ee9ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
801019f4:	00050793          	mv	a5,a0
801019f8:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:78
            config =  HAL_get_8bit_reg( this_uart->base_address, CTRL2 );
801019fc:	fdc42783          	lw	a5,-36(s0)
80101a00:	0007a783          	lw	a5,0(a5)
80101a04:	00c78793          	addi	a5,a5,12
80101a08:	00078513          	mv	a0,a5
80101a0c:	ecdff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101a10:	00050793          	mv	a5,a0
80101a14:	fef405a3          	sb	a5,-21(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:82
            /*
             * To resolve operator precedence between & and <<
             */
            temp =  ( config  &  (uint8_t)(CTRL2_BAUDVALUE_MASK ) );
80101a18:	feb44783          	lbu	a5,-21(s0)
80101a1c:	ff87f793          	andi	a5,a5,-8
80101a20:	fef40523          	sb	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:83
            baud_val |= (uint16_t)( (uint16_t)(temp) << BAUDVALUE_SHIFT );
80101a24:	fea44783          	lbu	a5,-22(s0)
80101a28:	01079793          	slli	a5,a5,0x10
80101a2c:	0107d793          	srli	a5,a5,0x10
80101a30:	00579793          	slli	a5,a5,0x5
80101a34:	01079713          	slli	a4,a5,0x10
80101a38:	01075713          	srli	a4,a4,0x10
80101a3c:	fec45783          	lhu	a5,-20(s0)
80101a40:	00f767b3          	or	a5,a4,a5
80101a44:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:84
            config &= (uint8_t)(~CTRL2_BAUDVALUE_MASK);
80101a48:	feb44783          	lbu	a5,-21(s0)
80101a4c:	0077f793          	andi	a5,a5,7
80101a50:	fef405a3          	sb	a5,-21(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:85
            HAL_ASSERT( baud_val == baud_value );
80101a54:	fec45703          	lhu	a4,-20(s0)
80101a58:	fd645783          	lhu	a5,-42(s0)
80101a5c:	00f70463          	beq	a4,a5,80101a64 <UART_init+0x14c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:85 (discriminator 1)
80101a60:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:86
            HAL_ASSERT( config == line_config );
80101a64:	feb44703          	lbu	a4,-21(s0)
80101a68:	fd544783          	lbu	a5,-43(s0)
80101a6c:	00f70463          	beq	a4,a5,80101a74 <UART_init+0x15c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:86 (discriminator 1)
80101a70:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:94
        
        /*
         * Flush the receive FIFO of data that may have been received before the
         * driver was initialized.
         */
        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
80101a74:	fdc42783          	lw	a5,-36(s0)
80101a78:	0007a783          	lw	a5,0(a5)
80101a7c:	01078793          	addi	a5,a5,16
80101a80:	00078513          	mv	a0,a5
80101a84:	e55ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101a88:	00050793          	mv	a5,a0
80101a8c:	0027f793          	andi	a5,a5,2
80101a90:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:96
                                                    STATUS_RXFULL_MASK;
        while ( rx_full )
80101a94:	0380006f          	j	80101acc <UART_init+0x1b4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:98
        {
            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
80101a98:	fdc42783          	lw	a5,-36(s0)
80101a9c:	0007a783          	lw	a5,0(a5)
80101aa0:	00478793          	addi	a5,a5,4
80101aa4:	00078513          	mv	a0,a5
80101aa8:	e31ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:99
            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
80101aac:	fdc42783          	lw	a5,-36(s0)
80101ab0:	0007a783          	lw	a5,0(a5)
80101ab4:	01078793          	addi	a5,a5,16
80101ab8:	00078513          	mv	a0,a5
80101abc:	e1dff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101ac0:	00050793          	mv	a5,a0
80101ac4:	0027f793          	andi	a5,a5,2
80101ac8:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:96
        while ( rx_full )
80101acc:	fef44783          	lbu	a5,-17(s0)
80101ad0:	fc0794e3          	bnez	a5,80101a98 <UART_init+0x180>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:106
        }

        /*
         * Clear status of the UART instance.
         */
        this_uart->status = (uint8_t)0;
80101ad4:	fdc42783          	lw	a5,-36(s0)
80101ad8:	00078223          	sb	zero,4(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:108
    }
}
80101adc:	00000013          	nop
80101ae0:	02c12083          	lw	ra,44(sp)
80101ae4:	02812403          	lw	s0,40(sp)
80101ae8:	03010113          	addi	sp,sp,48
80101aec:	00008067          	ret

80101af0 <UART_send>:
UART_send():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:121
(
    UART_instance_t * this_uart,
    const uint8_t * tx_buffer,
    size_t tx_size
)
{
80101af0:	fd010113          	addi	sp,sp,-48
80101af4:	02112623          	sw	ra,44(sp)
80101af8:	02812423          	sw	s0,40(sp)
80101afc:	03010413          	addi	s0,sp,48
80101b00:	fca42e23          	sw	a0,-36(s0)
80101b04:	fcb42c23          	sw	a1,-40(s0)
80101b08:	fcc42a23          	sw	a2,-44(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:125
    size_t char_idx;
    uint8_t tx_ready;

    HAL_ASSERT( this_uart != NULL_INSTANCE )
80101b0c:	fdc42783          	lw	a5,-36(s0)
80101b10:	00079463          	bnez	a5,80101b18 <UART_send+0x28>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:125 (discriminator 1)
80101b14:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:126
    HAL_ASSERT( tx_buffer != NULL_BUFFER )
80101b18:	fd842783          	lw	a5,-40(s0)
80101b1c:	00079463          	bnez	a5,80101b24 <UART_send+0x34>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:126 (discriminator 1)
80101b20:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:127
    HAL_ASSERT( tx_size > 0 )
80101b24:	fd442783          	lw	a5,-44(s0)
80101b28:	00079463          	bnez	a5,80101b30 <UART_send+0x40>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:127 (discriminator 1)
80101b2c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:129
      
    if( (this_uart != NULL_INSTANCE) &&
80101b30:	fdc42783          	lw	a5,-36(s0)
80101b34:	08078063          	beqz	a5,80101bb4 <UART_send+0xc4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:129 (discriminator 1)
80101b38:	fd842783          	lw	a5,-40(s0)
80101b3c:	06078c63          	beqz	a5,80101bb4 <UART_send+0xc4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:130
        (tx_buffer != NULL_BUFFER)   &&
80101b40:	fd442783          	lw	a5,-44(s0)
80101b44:	06078863          	beqz	a5,80101bb4 <UART_send+0xc4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:133
        (tx_size > (size_t)0) )
    {
        for ( char_idx = (size_t)0; char_idx < tx_size; char_idx++ )
80101b48:	fe042623          	sw	zero,-20(s0)
80101b4c:	05c0006f          	j	80101ba8 <UART_send+0xb8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:137 (discriminator 1)
        {
            /* Wait for UART to become ready to transmit. */
            do {
                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
80101b50:	fdc42783          	lw	a5,-36(s0)
80101b54:	0007a783          	lw	a5,0(a5)
80101b58:	01078793          	addi	a5,a5,16
80101b5c:	00078513          	mv	a0,a5
80101b60:	d79ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101b64:	00050793          	mv	a5,a0
80101b68:	0017f793          	andi	a5,a5,1
80101b6c:	fef405a3          	sb	a5,-21(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:139 (discriminator 1)
                                                              STATUS_TXRDY_MASK;
            } while ( !tx_ready );
80101b70:	feb44783          	lbu	a5,-21(s0)
80101b74:	fc078ee3          	beqz	a5,80101b50 <UART_send+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:141 (discriminator 2)
            /* Send next character in the buffer. */
            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
80101b78:	fdc42783          	lw	a5,-36(s0)
80101b7c:	0007a683          	lw	a3,0(a5)
80101b80:	fd842703          	lw	a4,-40(s0)
80101b84:	fec42783          	lw	a5,-20(s0)
80101b88:	00f707b3          	add	a5,a4,a5
80101b8c:	0007c783          	lbu	a5,0(a5)
80101b90:	00078593          	mv	a1,a5
80101b94:	00068513          	mv	a0,a3
80101b98:	d39ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:133 (discriminator 2)
        for ( char_idx = (size_t)0; char_idx < tx_size; char_idx++ )
80101b9c:	fec42783          	lw	a5,-20(s0)
80101ba0:	00178793          	addi	a5,a5,1
80101ba4:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:133 (discriminator 1)
80101ba8:	fec42703          	lw	a4,-20(s0)
80101bac:	fd442783          	lw	a5,-44(s0)
80101bb0:	faf760e3          	bltu	a4,a5,80101b50 <UART_send+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:145
                              (uint_fast8_t)tx_buffer[char_idx] );
        }
    }
}
80101bb4:	00000013          	nop
80101bb8:	02c12083          	lw	ra,44(sp)
80101bbc:	02812403          	lw	s0,40(sp)
80101bc0:	03010113          	addi	sp,sp,48
80101bc4:	00008067          	ret

80101bc8 <UART_get_rx>:
UART_get_rx():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:199
(
    UART_instance_t * this_uart,
    uint8_t * rx_buffer,
    size_t buff_size
)
{
80101bc8:	fd010113          	addi	sp,sp,-48
80101bcc:	02112623          	sw	ra,44(sp)
80101bd0:	02812423          	sw	s0,40(sp)
80101bd4:	02912223          	sw	s1,36(sp)
80101bd8:	03010413          	addi	s0,sp,48
80101bdc:	fca42e23          	sw	a0,-36(s0)
80101be0:	fcb42c23          	sw	a1,-40(s0)
80101be4:	fcc42a23          	sw	a2,-44(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:202
    uint8_t new_status;
    uint8_t rx_full;
    size_t rx_idx = 0u;
80101be8:	fe042423          	sw	zero,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:204
    
    HAL_ASSERT( this_uart != NULL_INSTANCE )
80101bec:	fdc42783          	lw	a5,-36(s0)
80101bf0:	00079463          	bnez	a5,80101bf8 <UART_get_rx+0x30>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:204 (discriminator 1)
80101bf4:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:205
    HAL_ASSERT( rx_buffer != NULL_BUFFER )
80101bf8:	fd842783          	lw	a5,-40(s0)
80101bfc:	00079463          	bnez	a5,80101c04 <UART_get_rx+0x3c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:205 (discriminator 1)
80101c00:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:206
    HAL_ASSERT( buff_size > 0 )
80101c04:	fd442783          	lw	a5,-44(s0)
80101c08:	00079463          	bnez	a5,80101c10 <UART_get_rx+0x48>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:206 (discriminator 1)
80101c0c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:208
      
    if( (this_uart != NULL_INSTANCE) &&
80101c10:	fdc42783          	lw	a5,-36(s0)
80101c14:	0e078663          	beqz	a5,80101d00 <UART_get_rx+0x138>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:208 (discriminator 1)
80101c18:	fd842783          	lw	a5,-40(s0)
80101c1c:	0e078263          	beqz	a5,80101d00 <UART_get_rx+0x138>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:209
        (rx_buffer != NULL_BUFFER)   &&
80101c20:	fd442783          	lw	a5,-44(s0)
80101c24:	0c078e63          	beqz	a5,80101d00 <UART_get_rx+0x138>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:212
        (buff_size > 0u) )
    {
        rx_idx = 0u;
80101c28:	fe042423          	sw	zero,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:213
        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
80101c2c:	fdc42783          	lw	a5,-36(s0)
80101c30:	0007a783          	lw	a5,0(a5)
80101c34:	01078793          	addi	a5,a5,16
80101c38:	00078513          	mv	a0,a5
80101c3c:	c9dff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101c40:	00050793          	mv	a5,a0
80101c44:	fef403a3          	sb	a5,-25(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:214
        this_uart->status |= new_status;
80101c48:	fdc42783          	lw	a5,-36(s0)
80101c4c:	0047c703          	lbu	a4,4(a5)
80101c50:	fe744783          	lbu	a5,-25(s0)
80101c54:	00f767b3          	or	a5,a4,a5
80101c58:	0ff7f713          	andi	a4,a5,255
80101c5c:	fdc42783          	lw	a5,-36(s0)
80101c60:	00e78223          	sb	a4,4(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:215
        rx_full = new_status & STATUS_RXFULL_MASK;
80101c64:	fe744783          	lbu	a5,-25(s0)
80101c68:	0027f793          	andi	a5,a5,2
80101c6c:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:216
        while ( ( rx_full ) && ( rx_idx < buff_size ) )
80101c70:	07c0006f          	j	80101cec <UART_get_rx+0x124>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:218
        {
            rx_buffer[rx_idx] = HAL_get_8bit_reg( this_uart->base_address,
80101c74:	fdc42783          	lw	a5,-36(s0)
80101c78:	0007a783          	lw	a5,0(a5)
80101c7c:	00478693          	addi	a3,a5,4
80101c80:	fd842703          	lw	a4,-40(s0)
80101c84:	fe842783          	lw	a5,-24(s0)
80101c88:	00f704b3          	add	s1,a4,a5
80101c8c:	00068513          	mv	a0,a3
80101c90:	c49ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101c94:	00050793          	mv	a5,a0
80101c98:	00f48023          	sb	a5,0(s1)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:220
                                                  RXDATA );
            rx_idx++;
80101c9c:	fe842783          	lw	a5,-24(s0)
80101ca0:	00178793          	addi	a5,a5,1
80101ca4:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:221
            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
80101ca8:	fdc42783          	lw	a5,-36(s0)
80101cac:	0007a783          	lw	a5,0(a5)
80101cb0:	01078793          	addi	a5,a5,16
80101cb4:	00078513          	mv	a0,a5
80101cb8:	c21ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101cbc:	00050793          	mv	a5,a0
80101cc0:	fef403a3          	sb	a5,-25(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:222
            this_uart->status |= new_status;
80101cc4:	fdc42783          	lw	a5,-36(s0)
80101cc8:	0047c703          	lbu	a4,4(a5)
80101ccc:	fe744783          	lbu	a5,-25(s0)
80101cd0:	00f767b3          	or	a5,a4,a5
80101cd4:	0ff7f713          	andi	a4,a5,255
80101cd8:	fdc42783          	lw	a5,-36(s0)
80101cdc:	00e78223          	sb	a4,4(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:223
            rx_full = new_status & STATUS_RXFULL_MASK;
80101ce0:	fe744783          	lbu	a5,-25(s0)
80101ce4:	0027f793          	andi	a5,a5,2
80101ce8:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:216
        while ( ( rx_full ) && ( rx_idx < buff_size ) )
80101cec:	fef44783          	lbu	a5,-17(s0)
80101cf0:	00078863          	beqz	a5,80101d00 <UART_get_rx+0x138>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:216 (discriminator 1)
80101cf4:	fe842703          	lw	a4,-24(s0)
80101cf8:	fd442783          	lw	a5,-44(s0)
80101cfc:	f6f76ce3          	bltu	a4,a5,80101c74 <UART_get_rx+0xac>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:226
        }
    }
    return rx_idx;
80101d00:	fe842783          	lw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:227
}
80101d04:	00078513          	mv	a0,a5
80101d08:	02c12083          	lw	ra,44(sp)
80101d0c:	02812403          	lw	s0,40(sp)
80101d10:	02412483          	lw	s1,36(sp)
80101d14:	03010113          	addi	sp,sp,48
80101d18:	00008067          	ret

80101d1c <UART_polled_tx_string>:
UART_polled_tx_string():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:239
UART_polled_tx_string
( 
    UART_instance_t * this_uart, 
    const uint8_t * p_sz_string
)
{
80101d1c:	fd010113          	addi	sp,sp,-48
80101d20:	02112623          	sw	ra,44(sp)
80101d24:	02812423          	sw	s0,40(sp)
80101d28:	03010413          	addi	s0,sp,48
80101d2c:	fca42e23          	sw	a0,-36(s0)
80101d30:	fcb42c23          	sw	a1,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:243
    uint32_t char_idx;
    uint8_t tx_ready;

    HAL_ASSERT( this_uart != NULL_INSTANCE )
80101d34:	fdc42783          	lw	a5,-36(s0)
80101d38:	00079463          	bnez	a5,80101d40 <UART_polled_tx_string+0x24>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:243 (discriminator 1)
80101d3c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:244
    HAL_ASSERT( p_sz_string != NULL_BUFFER )
80101d40:	fd842783          	lw	a5,-40(s0)
80101d44:	00079463          	bnez	a5,80101d4c <UART_polled_tx_string+0x30>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:244 (discriminator 1)
80101d48:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:246
    
    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
80101d4c:	fdc42783          	lw	a5,-36(s0)
80101d50:	08078063          	beqz	a5,80101dd0 <UART_polled_tx_string+0xb4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
80101d54:	fd842783          	lw	a5,-40(s0)
80101d58:	06078c63          	beqz	a5,80101dd0 <UART_polled_tx_string+0xb4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:248
    {
        char_idx = 0U;
80101d5c:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:249
        while( 0U != p_sz_string[char_idx] )
80101d60:	05c0006f          	j	80101dbc <UART_polled_tx_string+0xa0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
        {
            /* Wait for UART to become ready to transmit. */
            do {
                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
80101d64:	fdc42783          	lw	a5,-36(s0)
80101d68:	0007a783          	lw	a5,0(a5)
80101d6c:	01078793          	addi	a5,a5,16
80101d70:	00078513          	mv	a0,a5
80101d74:	b65ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80101d78:	00050793          	mv	a5,a0
80101d7c:	0017f793          	andi	a5,a5,1
80101d80:	fef405a3          	sb	a5,-21(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
                                                              STATUS_TXRDY_MASK;
            } while ( !tx_ready );
80101d84:	feb44783          	lbu	a5,-21(s0)
80101d88:	fc078ee3          	beqz	a5,80101d64 <UART_polled_tx_string+0x48>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:257
            /* Send next character in the buffer. */
            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
80101d8c:	fdc42783          	lw	a5,-36(s0)
80101d90:	0007a683          	lw	a3,0(a5)
80101d94:	fd842703          	lw	a4,-40(s0)
80101d98:	fec42783          	lw	a5,-20(s0)
80101d9c:	00f707b3          	add	a5,a4,a5
80101da0:	0007c783          	lbu	a5,0(a5)
80101da4:	00078593          	mv	a1,a5
80101da8:	00068513          	mv	a0,a3
80101dac:	b25ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:259
                              (uint_fast8_t)p_sz_string[char_idx] );
            char_idx++;
80101db0:	fec42783          	lw	a5,-20(s0)
80101db4:	00178793          	addi	a5,a5,1
80101db8:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:249
        while( 0U != p_sz_string[char_idx] )
80101dbc:	fd842703          	lw	a4,-40(s0)
80101dc0:	fec42783          	lw	a5,-20(s0)
80101dc4:	00f707b3          	add	a5,a4,a5
80101dc8:	0007c783          	lbu	a5,0(a5)
80101dcc:	f8079ce3          	bnez	a5,80101d64 <UART_polled_tx_string+0x48>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreUARTapb/core_uart_apb.c:262
        }
    }
}
80101dd0:	00000013          	nop
80101dd4:	02c12083          	lw	ra,44(sp)
80101dd8:	02812403          	lw	s0,40(sp)
80101ddc:	03010113          	addi	sp,sp,48
80101de0:	00008067          	ret

80101de4 <SPI_init>:
SPI_init():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:68
(
    spi_instance_t * this_spi,
    addr_t base_addr,
    uint16_t fifo_depth
)
{
80101de4:	fe010113          	addi	sp,sp,-32
80101de8:	00112e23          	sw	ra,28(sp)
80101dec:	00812c23          	sw	s0,24(sp)
80101df0:	02010413          	addi	s0,sp,32
80101df4:	fea42623          	sw	a0,-20(s0)
80101df8:	feb42423          	sw	a1,-24(s0)
80101dfc:	00060793          	mv	a5,a2
80101e00:	fef41323          	sh	a5,-26(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:69
    HAL_ASSERT( NULL_INSTANCE != this_spi );
80101e04:	fec42783          	lw	a5,-20(s0)
80101e08:	00079463          	bnez	a5,80101e10 <SPI_init+0x2c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:69 (discriminator 1)
80101e0c:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:70
    HAL_ASSERT( NULL_ADDR != base_addr );
80101e10:	fe842783          	lw	a5,-24(s0)
80101e14:	00079463          	bnez	a5,80101e1c <SPI_init+0x38>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:70 (discriminator 1)
80101e18:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:71
    HAL_ASSERT( SPI_MAX_FIFO_DEPTH  >= fifo_depth );
80101e1c:	fe645703          	lhu	a4,-26(s0)
80101e20:	02000793          	li	a5,32
80101e24:	00e7f463          	bgeu	a5,a4,80101e2c <SPI_init+0x48>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:71 (discriminator 1)
80101e28:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:72
    HAL_ASSERT( SPI_MIN_FIFO_DEPTH  <= fifo_depth );
80101e2c:	fe645783          	lhu	a5,-26(s0)
80101e30:	00079463          	bnez	a5,80101e38 <SPI_init+0x54>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:72 (discriminator 1)
80101e34:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:74

    if( ( NULL_INSTANCE != this_spi ) && ( base_addr != NULL_ADDR ) )
80101e38:	fec42783          	lw	a5,-20(s0)
80101e3c:	0e078463          	beqz	a5,80101f24 <SPI_init+0x140>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:74 (discriminator 1)
80101e40:	fe842783          	lw	a5,-24(s0)
80101e44:	0e078063          	beqz	a5,80101f24 <SPI_init+0x140>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:84
         * Relies on the fact that byte filling with 0x00 will equate
         * to 0 for any non byte sized items too.
         */

        /* First fill struct with 0s */
        memset( this_spi, 0, sizeof(spi_instance_t) );
80101e48:	04c00613          	li	a2,76
80101e4c:	00000593          	li	a1,0
80101e50:	fec42503          	lw	a0,-20(s0)
80101e54:	261010ef          	jal	ra,801038b4 <memset>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:87

        /* Configure CoreSPI instance attributes */
        this_spi->base_addr = (addr_t)base_addr;
80101e58:	fec42783          	lw	a5,-20(s0)
80101e5c:	fe842703          	lw	a4,-24(s0)
80101e60:	00e7a023          	sw	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:90

        /* Store FIFO depth or fall back to minimum if out of range */
        if( ( SPI_MAX_FIFO_DEPTH  >= fifo_depth ) && ( SPI_MIN_FIFO_DEPTH  <= fifo_depth ) )
80101e64:	fe645703          	lhu	a4,-26(s0)
80101e68:	02000793          	li	a5,32
80101e6c:	00e7ee63          	bltu	a5,a4,80101e88 <SPI_init+0xa4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:90 (discriminator 1)
80101e70:	fe645783          	lhu	a5,-26(s0)
80101e74:	00078a63          	beqz	a5,80101e88 <SPI_init+0xa4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:92
        {
            this_spi->fifo_depth = fifo_depth;
80101e78:	fec42783          	lw	a5,-20(s0)
80101e7c:	fe645703          	lhu	a4,-26(s0)
80101e80:	04e79223          	sh	a4,68(a5)
80101e84:	0100006f          	j	80101e94 <SPI_init+0xb0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:96
        }
        else
        {
            this_spi->fifo_depth = SPI_MIN_FIFO_DEPTH;
80101e88:	fec42783          	lw	a5,-20(s0)
80101e8c:	00100713          	li	a4,1
80101e90:	04e79223          	sh	a4,68(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:99
        }
        /* Make sure the CoreSPI is disabled while we configure it */
        HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
80101e94:	fec42783          	lw	a5,-20(s0)
80101e98:	0007a783          	lw	a5,0(a5)
80101e9c:	00000693          	li	a3,0
80101ea0:	00100613          	li	a2,1
80101ea4:	00000593          	li	a1,0
80101ea8:	00078513          	mv	a0,a5
80101eac:	a35ff0ef          	jal	ra,801018e0 <HW_set_8bit_reg_field>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:102

        /* Ensure all slaves are deselected */
        HAL_set_8bit_reg( this_spi->base_addr, SSEL, 0u );
80101eb0:	fec42783          	lw	a5,-20(s0)
80101eb4:	0007a783          	lw	a5,0(a5)
80101eb8:	02478793          	addi	a5,a5,36
80101ebc:	00000593          	li	a1,0
80101ec0:	00078513          	mv	a0,a5
80101ec4:	a0dff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:105

        /* Flush the receive and transmit FIFOs*/
        HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
80101ec8:	fec42783          	lw	a5,-20(s0)
80101ecc:	0007a783          	lw	a5,0(a5)
80101ed0:	01c78793          	addi	a5,a5,28
80101ed4:	00300593          	li	a1,3
80101ed8:	00078513          	mv	a0,a5
80101edc:	9f5ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:108

        /* Clear all interrupts */
        HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
80101ee0:	fec42783          	lw	a5,-20(s0)
80101ee4:	0007a783          	lw	a5,0(a5)
80101ee8:	00478793          	addi	a5,a5,4
80101eec:	0ff00593          	li	a1,255
80101ef0:	00078513          	mv	a0,a5
80101ef4:	9ddff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:111

        /* Ensure RXAVAIL, TXRFM, SSEND and CMDINT are disabled */
        HAL_set_8bit_reg( this_spi->base_addr, CTRL2, 0u );
80101ef8:	fec42783          	lw	a5,-20(s0)
80101efc:	0007a783          	lw	a5,0(a5)
80101f00:	01878793          	addi	a5,a5,24
80101f04:	00000593          	li	a1,0
80101f08:	00078513          	mv	a0,a5
80101f0c:	9c5ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:117
        /*
         * Enable the CoreSPI in the reset default of master mode
         * with TXUNDERRUN, RXOVFLOW and TXDONE interrupts disabled.
         * The driver does not currently use interrupts in master mode.
         */
        HAL_set_8bit_reg( this_spi->base_addr, CTRL1,  ENABLE | CTRL1_MASTER_MASK );
80101f10:	fec42783          	lw	a5,-20(s0)
80101f14:	0007a783          	lw	a5,0(a5)
80101f18:	00300593          	li	a1,3
80101f1c:	00078513          	mv	a0,a5
80101f20:	9b1ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:119
    }
}
80101f24:	00000013          	nop
80101f28:	01c12083          	lw	ra,28(sp)
80101f2c:	01812403          	lw	s0,24(sp)
80101f30:	02010113          	addi	sp,sp,32
80101f34:	00008067          	ret

80101f38 <SPI_configure_master_mode>:
SPI_configure_master_mode():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:165
 */
void SPI_configure_master_mode
(
    spi_instance_t * this_spi
)
{
80101f38:	fe010113          	addi	sp,sp,-32
80101f3c:	00112e23          	sw	ra,28(sp)
80101f40:	00812c23          	sw	s0,24(sp)
80101f44:	02010413          	addi	s0,sp,32
80101f48:	fea42623          	sw	a0,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:166
    HAL_ASSERT( NULL_INSTANCE != this_spi );
80101f4c:	fec42783          	lw	a5,-20(s0)
80101f50:	00079463          	bnez	a5,80101f58 <SPI_configure_master_mode+0x20>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:166 (discriminator 1)
80101f54:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:168
    
    if( NULL_INSTANCE != this_spi )
80101f58:	fec42783          	lw	a5,-20(s0)
80101f5c:	08078263          	beqz	a5,80101fe0 <SPI_configure_master_mode+0xa8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:171
    {
        /* Disable the CoreSPI for a little while, while we configure the CoreSPI */
        HAL_set_8bit_reg_field(this_spi->base_addr, CTRL1_ENABLE, DISABLE);
80101f60:	fec42783          	lw	a5,-20(s0)
80101f64:	0007a783          	lw	a5,0(a5)
80101f68:	00000693          	li	a3,0
80101f6c:	00100613          	li	a2,1
80101f70:	00000593          	li	a1,0
80101f74:	00078513          	mv	a0,a5
80101f78:	969ff0ef          	jal	ra,801018e0 <HW_set_8bit_reg_field>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:174

        /* Reset slave transfer mode to unknown in case it has been set previously */
        this_spi->slave_xfer_mode = SPI_SLAVE_XFER_NONE;
80101f7c:	fec42783          	lw	a5,-20(s0)
80101f80:	0407a423          	sw	zero,72(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:177

        /* Flush the receive and transmit FIFOs*/
        HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
80101f84:	fec42783          	lw	a5,-20(s0)
80101f88:	0007a783          	lw	a5,0(a5)
80101f8c:	01c78793          	addi	a5,a5,28
80101f90:	00300593          	li	a1,3
80101f94:	00078513          	mv	a0,a5
80101f98:	939ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:180

        /* Clear all interrupts */
        HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
80101f9c:	fec42783          	lw	a5,-20(s0)
80101fa0:	0007a783          	lw	a5,0(a5)
80101fa4:	00478793          	addi	a5,a5,4
80101fa8:	0ff00593          	li	a1,255
80101fac:	00078513          	mv	a0,a5
80101fb0:	921ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:183

        /* Ensure RXAVAIL, TXRFM, SSEND and CMDINT are disabled */
        HAL_set_8bit_reg( this_spi->base_addr, CTRL2, 0u );
80101fb4:	fec42783          	lw	a5,-20(s0)
80101fb8:	0007a783          	lw	a5,0(a5)
80101fbc:	01878793          	addi	a5,a5,24
80101fc0:	00000593          	li	a1,0
80101fc4:	00078513          	mv	a0,a5
80101fc8:	909ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:186

        /* Enable the CoreSPI in master mode with TXUNDERRUN, RXOVFLOW and TXDONE interrupts disabled */
        HAL_set_8bit_reg( this_spi->base_addr, CTRL1, ENABLE | CTRL1_MASTER_MASK );
80101fcc:	fec42783          	lw	a5,-20(s0)
80101fd0:	0007a783          	lw	a5,0(a5)
80101fd4:	00300593          	li	a1,3
80101fd8:	00078513          	mv	a0,a5
80101fdc:	8f5ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:188
    }
}
80101fe0:	00000013          	nop
80101fe4:	01c12083          	lw	ra,28(sp)
80101fe8:	01812403          	lw	s0,24(sp)
80101fec:	02010113          	addi	sp,sp,32
80101ff0:	00008067          	ret

80101ff4 <SPI_set_slave_select>:
SPI_set_slave_select():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:199
void SPI_set_slave_select
(
    spi_instance_t * this_spi,
    spi_slave_t slave
)
{
80101ff4:	fd010113          	addi	sp,sp,-48
80101ff8:	02112623          	sw	ra,44(sp)
80101ffc:	02812423          	sw	s0,40(sp)
80102000:	03010413          	addi	s0,sp,48
80102004:	fca42e23          	sw	a0,-36(s0)
80102008:	fcb42c23          	sw	a1,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:200
    spi_slave_t temp = (spi_slave_t)(0x00u) ;
8010200c:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:202

    HAL_ASSERT( NULL_INSTANCE != this_spi );
80102010:	fdc42783          	lw	a5,-36(s0)
80102014:	00079463          	bnez	a5,8010201c <SPI_set_slave_select+0x28>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:202 (discriminator 1)
80102018:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:203
    HAL_ASSERT( SPI_MAX_NB_OF_SLAVES > slave );
8010201c:	fd842703          	lw	a4,-40(s0)
80102020:	00700793          	li	a5,7
80102024:	00e7f463          	bgeu	a5,a4,8010202c <SPI_set_slave_select+0x38>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:203 (discriminator 1)
80102028:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:205
    
    if( ( NULL_INSTANCE != this_spi ) && ( SPI_MAX_NB_OF_SLAVES > slave ) )
8010202c:	fdc42783          	lw	a5,-36(s0)
80102030:	0a078663          	beqz	a5,801020dc <SPI_set_slave_select+0xe8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:205 (discriminator 1)
80102034:	fd842703          	lw	a4,-40(s0)
80102038:	00700793          	li	a5,7
8010203c:	0ae7e063          	bltu	a5,a4,801020dc <SPI_set_slave_select+0xe8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:208
    {
        /* This function is only intended to be used with an SPI master */
        if( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
80102040:	fdc42783          	lw	a5,-36(s0)
80102044:	0007a783          	lw	a5,0(a5)
80102048:	00200613          	li	a2,2
8010204c:	00100593          	li	a1,1
80102050:	00078513          	mv	a0,a5
80102054:	8b5ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
80102058:	00050793          	mv	a5,a0
8010205c:	08078063          	beqz	a5,801020dc <SPI_set_slave_select+0xe8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:211
        {
            /* Recover from receiver overflow because of previous slave */
            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW ) )
80102060:	fdc42783          	lw	a5,-36(s0)
80102064:	0007a783          	lw	a5,0(a5)
80102068:	02078793          	addi	a5,a5,32
8010206c:	01000613          	li	a2,16
80102070:	00400593          	li	a1,4
80102074:	00078513          	mv	a0,a5
80102078:	891ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
8010207c:	00050793          	mv	a5,a0
80102080:	00078713          	mv	a4,a5
80102084:	00100793          	li	a5,1
80102088:	00f71663          	bne	a4,a5,80102094 <SPI_set_slave_select+0xa0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:213
            {
                 recover_from_rx_overflow( this_spi );
8010208c:	fdc42503          	lw	a0,-36(s0)
80102090:	730000ef          	jal	ra,801027c0 <recover_from_rx_overflow>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:216
            }
            /* Set the correct slave select bit */
            temp = (spi_slave_t)( HAL_get_8bit_reg( this_spi->base_addr, SSEL ) | ((uint32_t)1u << (uint32_t)slave) );
80102094:	fdc42783          	lw	a5,-36(s0)
80102098:	0007a783          	lw	a5,0(a5)
8010209c:	02478793          	addi	a5,a5,36
801020a0:	00078513          	mv	a0,a5
801020a4:	835ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
801020a8:	00050793          	mv	a5,a0
801020ac:	00078693          	mv	a3,a5
801020b0:	fd842783          	lw	a5,-40(s0)
801020b4:	00100713          	li	a4,1
801020b8:	00f717b3          	sll	a5,a4,a5
801020bc:	00f6e7b3          	or	a5,a3,a5
801020c0:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:217
            HAL_set_8bit_reg( this_spi->base_addr, SSEL, (uint_fast8_t)temp );
801020c4:	fdc42783          	lw	a5,-36(s0)
801020c8:	0007a783          	lw	a5,0(a5)
801020cc:	02478793          	addi	a5,a5,36
801020d0:	fec42583          	lw	a1,-20(s0)
801020d4:	00078513          	mv	a0,a5
801020d8:	ff8ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:220
        }
    }
}
801020dc:	00000013          	nop
801020e0:	02c12083          	lw	ra,44(sp)
801020e4:	02812403          	lw	s0,40(sp)
801020e8:	03010113          	addi	sp,sp,48
801020ec:	00008067          	ret

801020f0 <SPI_clear_slave_select>:
SPI_clear_slave_select():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:231
void SPI_clear_slave_select
(
    spi_instance_t * this_spi,
    spi_slave_t slave
)
{
801020f0:	fd010113          	addi	sp,sp,-48
801020f4:	02112623          	sw	ra,44(sp)
801020f8:	02812423          	sw	s0,40(sp)
801020fc:	03010413          	addi	s0,sp,48
80102100:	fca42e23          	sw	a0,-36(s0)
80102104:	fcb42c23          	sw	a1,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:232
    spi_slave_t temp = (spi_slave_t) (0x00u) ;
80102108:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:234

    HAL_ASSERT( NULL_INSTANCE != this_spi );
8010210c:	fdc42783          	lw	a5,-36(s0)
80102110:	00079463          	bnez	a5,80102118 <SPI_clear_slave_select+0x28>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:234 (discriminator 1)
80102114:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:235
    HAL_ASSERT( SPI_MAX_NB_OF_SLAVES > slave );
80102118:	fd842703          	lw	a4,-40(s0)
8010211c:	00700793          	li	a5,7
80102120:	00e7f463          	bgeu	a5,a4,80102128 <SPI_clear_slave_select+0x38>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:235 (discriminator 1)
80102124:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:237
    
    if( ( NULL_INSTANCE != this_spi ) && ( SPI_MAX_NB_OF_SLAVES > slave ) )
80102128:	fdc42783          	lw	a5,-36(s0)
8010212c:	0a078863          	beqz	a5,801021dc <SPI_clear_slave_select+0xec>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:237 (discriminator 1)
80102130:	fd842703          	lw	a4,-40(s0)
80102134:	00700793          	li	a5,7
80102138:	0ae7e263          	bltu	a5,a4,801021dc <SPI_clear_slave_select+0xec>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:240
    {
        /* This function is only intended to be used with an SPI master. */
        if( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) )
8010213c:	fdc42783          	lw	a5,-36(s0)
80102140:	0007a783          	lw	a5,0(a5)
80102144:	00200613          	li	a2,2
80102148:	00100593          	li	a1,1
8010214c:	00078513          	mv	a0,a5
80102150:	fb8ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
80102154:	00050793          	mv	a5,a0
80102158:	08078263          	beqz	a5,801021dc <SPI_clear_slave_select+0xec>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:243
        {
            /* Recover from receiver overflow because of previous slave */
            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW) )
8010215c:	fdc42783          	lw	a5,-36(s0)
80102160:	0007a783          	lw	a5,0(a5)
80102164:	02078793          	addi	a5,a5,32
80102168:	01000613          	li	a2,16
8010216c:	00400593          	li	a1,4
80102170:	00078513          	mv	a0,a5
80102174:	f94ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
80102178:	00050793          	mv	a5,a0
8010217c:	00078713          	mv	a4,a5
80102180:	00100793          	li	a5,1
80102184:	00f71663          	bne	a4,a5,80102190 <SPI_clear_slave_select+0xa0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:245
            {
                 recover_from_rx_overflow( this_spi );
80102188:	fdc42503          	lw	a0,-36(s0)
8010218c:	634000ef          	jal	ra,801027c0 <recover_from_rx_overflow>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:248
            }
            /* Clear the correct slave select bit */
            temp = (spi_slave_t)( HAL_get_8bit_reg( this_spi->base_addr, SSEL ) & ~((uint32_t)1u << (uint32_t)slave) );
80102190:	fdc42783          	lw	a5,-36(s0)
80102194:	0007a783          	lw	a5,0(a5)
80102198:	02478793          	addi	a5,a5,36
8010219c:	00078513          	mv	a0,a5
801021a0:	f38ff0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
801021a4:	00050793          	mv	a5,a0
801021a8:	00078693          	mv	a3,a5
801021ac:	fd842783          	lw	a5,-40(s0)
801021b0:	00100713          	li	a4,1
801021b4:	00f717b3          	sll	a5,a4,a5
801021b8:	fff7c793          	not	a5,a5
801021bc:	00f6f7b3          	and	a5,a3,a5
801021c0:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:249
            HAL_set_8bit_reg( this_spi->base_addr, SSEL, (uint_fast8_t)temp ) ;
801021c4:	fdc42783          	lw	a5,-36(s0)
801021c8:	0007a783          	lw	a5,0(a5)
801021cc:	02478793          	addi	a5,a5,36
801021d0:	fec42583          	lw	a1,-20(s0)
801021d4:	00078513          	mv	a0,a5
801021d8:	ef8ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:252
        }
    }
}
801021dc:	00000013          	nop
801021e0:	02c12083          	lw	ra,44(sp)
801021e4:	02812403          	lw	s0,40(sp)
801021e8:	03010113          	addi	sp,sp,48
801021ec:	00008067          	ret

801021f0 <SPI_transfer_block>:
SPI_transfer_block():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:307
    const uint8_t * cmd_buffer,
    uint16_t cmd_byte_size,
    uint8_t * rx_buffer,
    uint16_t rx_byte_size
)
{
801021f0:	fd010113          	addi	sp,sp,-48
801021f4:	02112623          	sw	ra,44(sp)
801021f8:	02812423          	sw	s0,40(sp)
801021fc:	03010413          	addi	s0,sp,48
80102200:	fca42e23          	sw	a0,-36(s0)
80102204:	fcb42c23          	sw	a1,-40(s0)
80102208:	00060793          	mv	a5,a2
8010220c:	fcd42823          	sw	a3,-48(s0)
80102210:	fcf41b23          	sh	a5,-42(s0)
80102214:	00070793          	mv	a5,a4
80102218:	fcf41a23          	sh	a5,-44(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:308
    uint32_t transfer_size = 0U;   /* Total number of bytes to  transfer. */
8010221c:	fe042223          	sw	zero,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:309
    uint16_t transfer_idx = 0U;    /* Number of bytes transferred so far */
80102220:	fe041723          	sh	zero,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:310
    uint16_t tx_idx = 0u;          /* Number of valid data bytes sent */
80102224:	fe041623          	sh	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:311
    uint16_t rx_idx = 0u;          /* Number of valid response bytes received */
80102228:	fe041523          	sh	zero,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:312
    uint16_t transit = 0U;         /* Number of bytes "in flight" to avoid FIFO errors */
8010222c:	fe041423          	sh	zero,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:314

    HAL_ASSERT( NULL_INSTANCE != this_spi );
80102230:	fdc42783          	lw	a5,-36(s0)
80102234:	00079463          	bnez	a5,8010223c <SPI_transfer_block+0x4c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:314 (discriminator 1)
80102238:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:316

    if( NULL_INSTANCE != this_spi )
8010223c:	fdc42783          	lw	a5,-36(s0)
80102240:	56078663          	beqz	a5,801027ac <SPI_transfer_block+0x5bc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:319
    {
        /* This function is only intended to be used with an SPI master. */
        if( ( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) ) &&
80102244:	fdc42783          	lw	a5,-36(s0)
80102248:	0007a783          	lw	a5,0(a5)
8010224c:	00200613          	li	a2,2
80102250:	00100593          	li	a1,1
80102254:	00078513          	mv	a0,a5
80102258:	eb0ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
8010225c:	00050793          	mv	a5,a0
80102260:	54078663          	beqz	a5,801027ac <SPI_transfer_block+0x5bc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:321 (discriminator 1)
            /* Check for empty transfer as well */
            ( 0u != ( (uint32_t)cmd_byte_size + (uint32_t)rx_byte_size ) ) )
80102264:	fd645703          	lhu	a4,-42(s0)
80102268:	fd445783          	lhu	a5,-44(s0)
8010226c:	00f707b3          	add	a5,a4,a5
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:319 (discriminator 1)
        if( ( DISABLE != HAL_get_8bit_reg_field(this_spi->base_addr, CTRL1_MASTER ) ) &&
80102270:	52078e63          	beqz	a5,801027ac <SPI_transfer_block+0x5bc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:328
            /*
             * tansfer_size is one less than the real amount as we have to write
             * the last frame separately to trigger the slave deselect in case
             * the SPS option is in place.
             */
            transfer_size = ( (uint32_t)cmd_byte_size + (uint32_t)rx_byte_size ) - 1u;
80102274:	fd645703          	lhu	a4,-42(s0)
80102278:	fd445783          	lhu	a5,-44(s0)
8010227c:	00f707b3          	add	a5,a4,a5
80102280:	fff78793          	addi	a5,a5,-1
80102284:	fef42223          	sw	a5,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:330
            /* Flush the receive and transmit FIFOs */
            HAL_set_8bit_reg(this_spi->base_addr, CMD, (uint32_t)(CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK ));
80102288:	fdc42783          	lw	a5,-36(s0)
8010228c:	0007a783          	lw	a5,0(a5)
80102290:	01c78793          	addi	a5,a5,28
80102294:	00300593          	li	a1,3
80102298:	00078513          	mv	a0,a5
8010229c:	e34ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:333

            /* Recover from receiver overflow because of previous slave */
            if( ENABLE == HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXOVFLOW) )
801022a0:	fdc42783          	lw	a5,-36(s0)
801022a4:	0007a783          	lw	a5,0(a5)
801022a8:	02078793          	addi	a5,a5,32
801022ac:	01000613          	li	a2,16
801022b0:	00400593          	li	a1,4
801022b4:	00078513          	mv	a0,a5
801022b8:	e50ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
801022bc:	00050793          	mv	a5,a0
801022c0:	00078713          	mv	a4,a5
801022c4:	00100793          	li	a5,1
801022c8:	00f71663          	bne	a4,a5,801022d4 <SPI_transfer_block+0xe4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:335
            {
                 recover_from_rx_overflow( this_spi );
801022cc:	fdc42503          	lw	a0,-36(s0)
801022d0:	4f0000ef          	jal	ra,801027c0 <recover_from_rx_overflow>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:339
            }

            /* Disable the Core SPI for a little bit, while we load the TX FIFO */
            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
801022d4:	fdc42783          	lw	a5,-36(s0)
801022d8:	0007a783          	lw	a5,0(a5)
801022dc:	00000693          	li	a3,0
801022e0:	00100613          	li	a2,1
801022e4:	00000593          	li	a1,0
801022e8:	00078513          	mv	a0,a5
801022ec:	df4ff0ef          	jal	ra,801018e0 <HW_set_8bit_reg_field>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:341

            while( ( tx_idx < transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
801022f0:	06c0006f          	j	8010235c <SPI_transfer_block+0x16c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:343
            {
                if( tx_idx < cmd_byte_size )
801022f4:	fec45703          	lhu	a4,-20(s0)
801022f8:	fd645783          	lhu	a5,-42(s0)
801022fc:	02f77863          	bgeu	a4,a5,8010232c <SPI_transfer_block+0x13c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:346
                {
                    /* Push out valid data */
                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)cmd_buffer[tx_idx] );
80102300:	fdc42783          	lw	a5,-36(s0)
80102304:	0007a783          	lw	a5,0(a5)
80102308:	00c78693          	addi	a3,a5,12
8010230c:	fec45783          	lhu	a5,-20(s0)
80102310:	fd842703          	lw	a4,-40(s0)
80102314:	00f707b3          	add	a5,a4,a5
80102318:	0007c783          	lbu	a5,0(a5)
8010231c:	00078593          	mv	a1,a5
80102320:	00068513          	mv	a0,a3
80102324:	d1cff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
80102328:	01c0006f          	j	80102344 <SPI_transfer_block+0x154>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:351
                }
                else
                {
                    /* Push out 0s to get data back from slave */
                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
8010232c:	fdc42783          	lw	a5,-36(s0)
80102330:	0007a783          	lw	a5,0(a5)
80102334:	00c78793          	addi	a5,a5,12
80102338:	00000593          	li	a1,0
8010233c:	00078513          	mv	a0,a5
80102340:	d00ff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:353
                }
                ++transit;
80102344:	fe845783          	lhu	a5,-24(s0)
80102348:	00178793          	addi	a5,a5,1
8010234c:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:354
                ++tx_idx;
80102350:	fec45783          	lhu	a5,-20(s0)
80102354:	00178793          	addi	a5,a5,1
80102358:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:341
            while( ( tx_idx < transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
8010235c:	fec45783          	lhu	a5,-20(s0)
80102360:	fe442703          	lw	a4,-28(s0)
80102364:	00e7fa63          	bgeu	a5,a4,80102378 <SPI_transfer_block+0x188>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:341 (discriminator 1)
80102368:	fdc42783          	lw	a5,-36(s0)
8010236c:	0447d783          	lhu	a5,68(a5)
80102370:	fec45703          	lhu	a4,-20(s0)
80102374:	f8f760e3          	bltu	a4,a5,801022f4 <SPI_transfer_block+0x104>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:358
            }

            /* If room left to put last frame in before the off, then do it */
            if( ( tx_idx == transfer_size ) && ( tx_idx < this_spi->fifo_depth ) )
80102378:	fec45783          	lhu	a5,-20(s0)
8010237c:	fe442703          	lw	a4,-28(s0)
80102380:	06f71e63          	bne	a4,a5,801023fc <SPI_transfer_block+0x20c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:358 (discriminator 1)
80102384:	fdc42783          	lw	a5,-36(s0)
80102388:	0447d783          	lhu	a5,68(a5)
8010238c:	fec45703          	lhu	a4,-20(s0)
80102390:	06f77663          	bgeu	a4,a5,801023fc <SPI_transfer_block+0x20c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:360
            {
                if( tx_idx < cmd_byte_size )
80102394:	fec45703          	lhu	a4,-20(s0)
80102398:	fd645783          	lhu	a5,-42(s0)
8010239c:	02f77863          	bgeu	a4,a5,801023cc <SPI_transfer_block+0x1dc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:363
                {
                    /* Push out valid data, not expecting any reply this time */
                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, (uint32_t)cmd_buffer[tx_idx] );
801023a0:	fdc42783          	lw	a5,-36(s0)
801023a4:	0007a783          	lw	a5,0(a5)
801023a8:	02878693          	addi	a3,a5,40
801023ac:	fec45783          	lhu	a5,-20(s0)
801023b0:	fd842703          	lw	a4,-40(s0)
801023b4:	00f707b3          	add	a5,a4,a5
801023b8:	0007c783          	lbu	a5,0(a5)
801023bc:	00078593          	mv	a1,a5
801023c0:	00068513          	mv	a0,a3
801023c4:	c7cff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
801023c8:	01c0006f          	j	801023e4 <SPI_transfer_block+0x1f4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:368
                }
                else
                {
                    /* Push out last 0 to get data back from slave */
                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, 0U );
801023cc:	fdc42783          	lw	a5,-36(s0)
801023d0:	0007a783          	lw	a5,0(a5)
801023d4:	02878793          	addi	a5,a5,40
801023d8:	00000593          	li	a1,0
801023dc:	00078513          	mv	a0,a5
801023e0:	c60ff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:371
                }

                ++transit;
801023e4:	fe845783          	lhu	a5,-24(s0)
801023e8:	00178793          	addi	a5,a5,1
801023ec:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:372
                ++tx_idx;
801023f0:	fec45783          	lhu	a5,-20(s0)
801023f4:	00178793          	addi	a5,a5,1
801023f8:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:376
            }

            /* FIFO is all loaded up so enable Core SPI to start transfer */
            HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
801023fc:	fdc42783          	lw	a5,-36(s0)
80102400:	0007a783          	lw	a5,0(a5)
80102404:	00100693          	li	a3,1
80102408:	00100613          	li	a2,1
8010240c:	00000593          	li	a1,0
80102410:	00078513          	mv	a0,a5
80102414:	cccff0ef          	jal	ra,801018e0 <HW_set_8bit_reg_field>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:391
             *
             * First stage transfers remaining command bytes (if any).
             * At this stage anything in the RX FIFO can be discarded as it is
             * not part of a valid response.
             */
            while( tx_idx < cmd_byte_size )
80102418:	0dc0006f          	j	801024f4 <SPI_transfer_block+0x304>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:393
            {
                if( transit < this_spi->fifo_depth )
8010241c:	fdc42783          	lw	a5,-36(s0)
80102420:	0447d783          	lhu	a5,68(a5)
80102424:	fe845703          	lhu	a4,-24(s0)
80102428:	06f77e63          	bgeu	a4,a5,801024a4 <SPI_transfer_block+0x2b4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:396
                {
                    /* Send another byte. */
                    if( tx_idx == transfer_size ) /* Last frame is special... */
8010242c:	fec45783          	lhu	a5,-20(s0)
80102430:	fe442703          	lw	a4,-28(s0)
80102434:	02f71863          	bne	a4,a5,80102464 <SPI_transfer_block+0x274>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:398
                    {
                        HAL_set_32bit_reg( this_spi->base_addr, TXLAST, (uint32_t)cmd_buffer[tx_idx] );
80102438:	fdc42783          	lw	a5,-36(s0)
8010243c:	0007a783          	lw	a5,0(a5)
80102440:	02878693          	addi	a3,a5,40
80102444:	fec45783          	lhu	a5,-20(s0)
80102448:	fd842703          	lw	a4,-40(s0)
8010244c:	00f707b3          	add	a5,a4,a5
80102450:	0007c783          	lbu	a5,0(a5)
80102454:	00078593          	mv	a1,a5
80102458:	00068513          	mv	a0,a3
8010245c:	be4ff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
80102460:	02c0006f          	j	8010248c <SPI_transfer_block+0x29c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:402
                    }
                    else
                    {
                        HAL_set_32bit_reg( this_spi->base_addr, TXDATA, (uint32_t)cmd_buffer[tx_idx] );
80102464:	fdc42783          	lw	a5,-36(s0)
80102468:	0007a783          	lw	a5,0(a5)
8010246c:	00c78693          	addi	a3,a5,12
80102470:	fec45783          	lhu	a5,-20(s0)
80102474:	fd842703          	lw	a4,-40(s0)
80102478:	00f707b3          	add	a5,a4,a5
8010247c:	0007c783          	lbu	a5,0(a5)
80102480:	00078593          	mv	a1,a5
80102484:	00068513          	mv	a0,a3
80102488:	bb8ff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:404
                    }
                    ++tx_idx;
8010248c:	fec45783          	lhu	a5,-20(s0)
80102490:	00178793          	addi	a5,a5,1
80102494:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:405
                    ++transit;
80102498:	fe845783          	lhu	a5,-24(s0)
8010249c:	00178793          	addi	a5,a5,1
801024a0:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:407
                }
                if( !HAL_get_8bit_reg_field( this_spi->base_addr, STATUS_RXEMPTY ) )
801024a4:	fdc42783          	lw	a5,-36(s0)
801024a8:	0007a783          	lw	a5,0(a5)
801024ac:	02078793          	addi	a5,a5,32
801024b0:	00400613          	li	a2,4
801024b4:	00200593          	li	a1,2
801024b8:	00078513          	mv	a0,a5
801024bc:	c4cff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
801024c0:	00050793          	mv	a5,a0
801024c4:	02079863          	bnez	a5,801024f4 <SPI_transfer_block+0x304>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:410
                {
                    /* Read and discard. */
                    HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
801024c8:	fdc42783          	lw	a5,-36(s0)
801024cc:	0007a783          	lw	a5,0(a5)
801024d0:	00878793          	addi	a5,a5,8
801024d4:	00078513          	mv	a0,a5
801024d8:	b70ff0ef          	jal	ra,80101848 <HW_get_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:411
                    ++transfer_idx;
801024dc:	fee45783          	lhu	a5,-18(s0)
801024e0:	00178793          	addi	a5,a5,1
801024e4:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:412
                    --transit;
801024e8:	fe845783          	lhu	a5,-24(s0)
801024ec:	fff78793          	addi	a5,a5,-1
801024f0:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:391
            while( tx_idx < cmd_byte_size )
801024f4:	fec45703          	lhu	a4,-20(s0)
801024f8:	fd645783          	lhu	a5,-42(s0)
801024fc:	f2f760e3          	bltu	a4,a5,8010241c <SPI_transfer_block+0x22c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:420
            /*
             * Now, we are writing dummy bytes to push through the response from
             * the slave but we still have to keep discarding any read data that
             * corresponds with one of our command bytes.
             */
            while( transfer_idx < cmd_byte_size )
80102500:	0a00006f          	j	801025a0 <SPI_transfer_block+0x3b0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:422
            {
                if( transit < this_spi->fifo_depth )
80102504:	fdc42783          	lw	a5,-36(s0)
80102508:	0447d783          	lhu	a5,68(a5)
8010250c:	fe845703          	lhu	a4,-24(s0)
80102510:	04f77063          	bgeu	a4,a5,80102550 <SPI_transfer_block+0x360>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:424
                {
                    if( tx_idx < transfer_size )
80102514:	fec45783          	lhu	a5,-20(s0)
80102518:	fe442703          	lw	a4,-28(s0)
8010251c:	02e7fa63          	bgeu	a5,a4,80102550 <SPI_transfer_block+0x360>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:426
                    {
                        HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
80102520:	fdc42783          	lw	a5,-36(s0)
80102524:	0007a783          	lw	a5,0(a5)
80102528:	00c78793          	addi	a5,a5,12
8010252c:	00000593          	li	a1,0
80102530:	00078513          	mv	a0,a5
80102534:	b0cff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:427
                        ++tx_idx;
80102538:	fec45783          	lhu	a5,-20(s0)
8010253c:	00178793          	addi	a5,a5,1
80102540:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:428
                        ++transit;
80102544:	fe845783          	lhu	a5,-24(s0)
80102548:	00178793          	addi	a5,a5,1
8010254c:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:431
                    }
                }
                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
80102550:	fdc42783          	lw	a5,-36(s0)
80102554:	0007a783          	lw	a5,0(a5)
80102558:	02078793          	addi	a5,a5,32
8010255c:	00400613          	li	a2,4
80102560:	00200593          	li	a1,2
80102564:	00078513          	mv	a0,a5
80102568:	ba0ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
8010256c:	00050793          	mv	a5,a0
80102570:	02079863          	bnez	a5,801025a0 <SPI_transfer_block+0x3b0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:434
                {
                    /* Read and discard. */
                    HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
80102574:	fdc42783          	lw	a5,-36(s0)
80102578:	0007a783          	lw	a5,0(a5)
8010257c:	00878793          	addi	a5,a5,8
80102580:	00078513          	mv	a0,a5
80102584:	ac4ff0ef          	jal	ra,80101848 <HW_get_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:435
                    ++transfer_idx;
80102588:	fee45783          	lhu	a5,-18(s0)
8010258c:	00178793          	addi	a5,a5,1
80102590:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:436
                    --transit;
80102594:	fe845783          	lhu	a5,-24(s0)
80102598:	fff78793          	addi	a5,a5,-1
8010259c:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:420
            while( transfer_idx < cmd_byte_size )
801025a0:	fee45703          	lhu	a4,-18(s0)
801025a4:	fd645783          	lhu	a5,-42(s0)
801025a8:	f4f76ee3          	bltu	a4,a5,80102504 <SPI_transfer_block+0x314>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:443
            }
            /*
             * Now we are now only sending dummy data to push through the
             * valid response data which we store in the response buffer.
             */
            while( tx_idx < transfer_size )
801025ac:	0b80006f          	j	80102664 <SPI_transfer_block+0x474>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:445
            {
                if( transit < this_spi->fifo_depth )
801025b0:	fdc42783          	lw	a5,-36(s0)
801025b4:	0447d783          	lhu	a5,68(a5)
801025b8:	fe845703          	lhu	a4,-24(s0)
801025bc:	02f77a63          	bgeu	a4,a5,801025f0 <SPI_transfer_block+0x400>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:447
                {
                    HAL_set_32bit_reg( this_spi->base_addr, TXDATA, 0U );
801025c0:	fdc42783          	lw	a5,-36(s0)
801025c4:	0007a783          	lw	a5,0(a5)
801025c8:	00c78793          	addi	a5,a5,12
801025cc:	00000593          	li	a1,0
801025d0:	00078513          	mv	a0,a5
801025d4:	a6cff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:448
                    ++tx_idx;
801025d8:	fec45783          	lhu	a5,-20(s0)
801025dc:	00178793          	addi	a5,a5,1
801025e0:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:449
                    ++transit;
801025e4:	fe845783          	lhu	a5,-24(s0)
801025e8:	00178793          	addi	a5,a5,1
801025ec:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:451
                }
                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
801025f0:	fdc42783          	lw	a5,-36(s0)
801025f4:	0007a783          	lw	a5,0(a5)
801025f8:	02078793          	addi	a5,a5,32
801025fc:	00400613          	li	a2,4
80102600:	00200593          	li	a1,2
80102604:	00078513          	mv	a0,a5
80102608:	b00ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
8010260c:	00050793          	mv	a5,a0
80102610:	04079a63          	bnez	a5,80102664 <SPI_transfer_block+0x474>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:454
                {
                    /* Process received byte. */
                    rx_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
80102614:	fdc42783          	lw	a5,-36(s0)
80102618:	0007a783          	lw	a5,0(a5)
8010261c:	00878793          	addi	a5,a5,8
80102620:	00078513          	mv	a0,a5
80102624:	a24ff0ef          	jal	ra,80101848 <HW_get_32bit_reg>
80102628:	00050693          	mv	a3,a0
8010262c:	fea45783          	lhu	a5,-22(s0)
80102630:	fd042703          	lw	a4,-48(s0)
80102634:	00f707b3          	add	a5,a4,a5
80102638:	0ff6f713          	andi	a4,a3,255
8010263c:	00e78023          	sb	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:455
                    ++rx_idx;
80102640:	fea45783          	lhu	a5,-22(s0)
80102644:	00178793          	addi	a5,a5,1
80102648:	fef41523          	sh	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:456
                    ++transfer_idx;
8010264c:	fee45783          	lhu	a5,-18(s0)
80102650:	00178793          	addi	a5,a5,1
80102654:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:457
                    --transit;
80102658:	fe845783          	lhu	a5,-24(s0)
8010265c:	fff78793          	addi	a5,a5,-1
80102660:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:443
            while( tx_idx < transfer_size )
80102664:	fec45783          	lhu	a5,-20(s0)
80102668:	fe442703          	lw	a4,-28(s0)
8010266c:	f4e7e2e3          	bltu	a5,a4,801025b0 <SPI_transfer_block+0x3c0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:461
                }
            }
            /* If we still need to send the last frame */
            while( tx_idx == transfer_size )
80102670:	0b80006f          	j	80102728 <SPI_transfer_block+0x538>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:463
            {
                if( transit < this_spi->fifo_depth )
80102674:	fdc42783          	lw	a5,-36(s0)
80102678:	0447d783          	lhu	a5,68(a5)
8010267c:	fe845703          	lhu	a4,-24(s0)
80102680:	02f77a63          	bgeu	a4,a5,801026b4 <SPI_transfer_block+0x4c4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:465
                {
                    HAL_set_32bit_reg( this_spi->base_addr, TXLAST, 0U );
80102684:	fdc42783          	lw	a5,-36(s0)
80102688:	0007a783          	lw	a5,0(a5)
8010268c:	02878793          	addi	a5,a5,40
80102690:	00000593          	li	a1,0
80102694:	00078513          	mv	a0,a5
80102698:	9a8ff0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:466
                    ++tx_idx;
8010269c:	fec45783          	lhu	a5,-20(s0)
801026a0:	00178793          	addi	a5,a5,1
801026a4:	fef41623          	sh	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:467
                    ++transit;
801026a8:	fe845783          	lhu	a5,-24(s0)
801026ac:	00178793          	addi	a5,a5,1
801026b0:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:469
                }
                if( !HAL_get_8bit_reg_field( this_spi->base_addr, STATUS_RXEMPTY ) )
801026b4:	fdc42783          	lw	a5,-36(s0)
801026b8:	0007a783          	lw	a5,0(a5)
801026bc:	02078793          	addi	a5,a5,32
801026c0:	00400613          	li	a2,4
801026c4:	00200593          	li	a1,2
801026c8:	00078513          	mv	a0,a5
801026cc:	a3cff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
801026d0:	00050793          	mv	a5,a0
801026d4:	04079a63          	bnez	a5,80102728 <SPI_transfer_block+0x538>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:472
                {
                    /* Process received byte. */
                    rx_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
801026d8:	fdc42783          	lw	a5,-36(s0)
801026dc:	0007a783          	lw	a5,0(a5)
801026e0:	00878793          	addi	a5,a5,8
801026e4:	00078513          	mv	a0,a5
801026e8:	960ff0ef          	jal	ra,80101848 <HW_get_32bit_reg>
801026ec:	00050693          	mv	a3,a0
801026f0:	fea45783          	lhu	a5,-22(s0)
801026f4:	fd042703          	lw	a4,-48(s0)
801026f8:	00f707b3          	add	a5,a4,a5
801026fc:	0ff6f713          	andi	a4,a3,255
80102700:	00e78023          	sb	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:473
                    ++rx_idx;
80102704:	fea45783          	lhu	a5,-22(s0)
80102708:	00178793          	addi	a5,a5,1
8010270c:	fef41523          	sh	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:474
                    ++transfer_idx;
80102710:	fee45783          	lhu	a5,-18(s0)
80102714:	00178793          	addi	a5,a5,1
80102718:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:475
                    --transit;
8010271c:	fe845783          	lhu	a5,-24(s0)
80102720:	fff78793          	addi	a5,a5,-1
80102724:	fef41423          	sh	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:461
            while( tx_idx == transfer_size )
80102728:	fec45783          	lhu	a5,-20(s0)
8010272c:	fe442703          	lw	a4,-28(s0)
80102730:	f4f702e3          	beq	a4,a5,80102674 <SPI_transfer_block+0x484>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:482
            }
            /*
             * Finally, we are now finished sending data and are only reading
             * valid response data which we store in the response buffer.
             */
            while( transfer_idx <= transfer_size )
80102734:	06c0006f          	j	801027a0 <SPI_transfer_block+0x5b0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:484
            {
                if( !HAL_get_8bit_reg_field(this_spi->base_addr, STATUS_RXEMPTY ) )
80102738:	fdc42783          	lw	a5,-36(s0)
8010273c:	0007a783          	lw	a5,0(a5)
80102740:	02078793          	addi	a5,a5,32
80102744:	00400613          	li	a2,4
80102748:	00200593          	li	a1,2
8010274c:	00078513          	mv	a0,a5
80102750:	9b8ff0ef          	jal	ra,80101908 <HW_get_8bit_reg_field>
80102754:	00050793          	mv	a5,a0
80102758:	04079463          	bnez	a5,801027a0 <SPI_transfer_block+0x5b0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:487
                {
                    /* Process received byte. */
                    rx_buffer[rx_idx] = (uint8_t)HAL_get_32bit_reg( this_spi->base_addr, RXDATA );
8010275c:	fdc42783          	lw	a5,-36(s0)
80102760:	0007a783          	lw	a5,0(a5)
80102764:	00878793          	addi	a5,a5,8
80102768:	00078513          	mv	a0,a5
8010276c:	8dcff0ef          	jal	ra,80101848 <HW_get_32bit_reg>
80102770:	00050693          	mv	a3,a0
80102774:	fea45783          	lhu	a5,-22(s0)
80102778:	fd042703          	lw	a4,-48(s0)
8010277c:	00f707b3          	add	a5,a4,a5
80102780:	0ff6f713          	andi	a4,a3,255
80102784:	00e78023          	sb	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:488
                    ++rx_idx;
80102788:	fea45783          	lhu	a5,-22(s0)
8010278c:	00178793          	addi	a5,a5,1
80102790:	fef41523          	sh	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:489
                    ++transfer_idx;
80102794:	fee45783          	lhu	a5,-18(s0)
80102798:	00178793          	addi	a5,a5,1
8010279c:	fef41723          	sh	a5,-18(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:482
            while( transfer_idx <= transfer_size )
801027a0:	fee45783          	lhu	a5,-18(s0)
801027a4:	fe442703          	lw	a4,-28(s0)
801027a8:	f8f778e3          	bgeu	a4,a5,80102738 <SPI_transfer_block+0x548>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:494
                }
            }
        }
    }
}
801027ac:	00000013          	nop
801027b0:	02c12083          	lw	ra,44(sp)
801027b4:	02812403          	lw	s0,40(sp)
801027b8:	03010113          	addi	sp,sp,48
801027bc:	00008067          	ret

801027c0 <recover_from_rx_overflow>:
recover_from_rx_overflow():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:1331
 */
static void recover_from_rx_overflow
(
    const spi_instance_t * this_spi
)
{
801027c0:	fe010113          	addi	sp,sp,-32
801027c4:	00112e23          	sw	ra,28(sp)
801027c8:	00812c23          	sw	s0,24(sp)
801027cc:	02010413          	addi	s0,sp,32
801027d0:	fea42623          	sw	a0,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:1333
    /* Disable CoreSPI */
    HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, DISABLE );
801027d4:	fec42783          	lw	a5,-20(s0)
801027d8:	0007a783          	lw	a5,0(a5)
801027dc:	00000693          	li	a3,0
801027e0:	00100613          	li	a2,1
801027e4:	00000593          	li	a1,0
801027e8:	00078513          	mv	a0,a5
801027ec:	8f4ff0ef          	jal	ra,801018e0 <HW_set_8bit_reg_field>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:1336

    /* Reset TX and RX FIFOs */
    HAL_set_8bit_reg( this_spi->base_addr, CMD, CMD_TXFIFORST_MASK | CMD_RXFIFORST_MASK );
801027f0:	fec42783          	lw	a5,-20(s0)
801027f4:	0007a783          	lw	a5,0(a5)
801027f8:	01c78793          	addi	a5,a5,28
801027fc:	00300593          	li	a1,3
80102800:	00078513          	mv	a0,a5
80102804:	8ccff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:1339

    /* Clear all interrupts */
    HAL_set_8bit_reg( this_spi->base_addr, INTCLR, SPI_ALL_INTS );
80102808:	fec42783          	lw	a5,-20(s0)
8010280c:	0007a783          	lw	a5,0(a5)
80102810:	00478793          	addi	a5,a5,4
80102814:	0ff00593          	li	a1,255
80102818:	00078513          	mv	a0,a5
8010281c:	8b4ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:1342

    /* Enable CoreSPI */
    HAL_set_8bit_reg_field( this_spi->base_addr, CTRL1_ENABLE, ENABLE );
80102820:	fec42783          	lw	a5,-20(s0)
80102824:	0007a783          	lw	a5,0(a5)
80102828:	00100693          	li	a3,1
8010282c:	00100613          	li	a2,1
80102830:	00000593          	li	a1,0
80102834:	00078513          	mv	a0,a5
80102838:	8a8ff0ef          	jal	ra,801018e0 <HW_set_8bit_reg_field>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreSPI/core_spi.c:1343
}
8010283c:	00000013          	nop
80102840:	01c12083          	lw	ra,28(sp)
80102844:	01812403          	lw	s0,24(sp)
80102848:	02010113          	addi	sp,sp,32
8010284c:	00008067          	ret

80102850 <GPIO_init>:
GPIO_init():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:37
(
    gpio_instance_t *   this_gpio,
    addr_t              base_addr,
    gpio_apb_width_t    bus_width
)
{
80102850:	fd010113          	addi	sp,sp,-48
80102854:	02112623          	sw	ra,44(sp)
80102858:	02812423          	sw	s0,40(sp)
8010285c:	03010413          	addi	s0,sp,48
80102860:	fca42e23          	sw	a0,-36(s0)
80102864:	fcb42c23          	sw	a1,-40(s0)
80102868:	fcc42a23          	sw	a2,-44(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:38
    uint8_t i = 0;
8010286c:	fe0407a3          	sb	zero,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:39
    addr_t cfg_reg_addr = base_addr;
80102870:	fd842783          	lw	a5,-40(s0)
80102874:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:41
    
    this_gpio->base_addr = base_addr;
80102878:	fdc42783          	lw	a5,-36(s0)
8010287c:	fd842703          	lw	a4,-40(s0)
80102880:	00e7a023          	sw	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:42
    this_gpio->apb_bus_width = bus_width;
80102884:	fdc42783          	lw	a5,-36(s0)
80102888:	fd442703          	lw	a4,-44(s0)
8010288c:	00e7a223          	sw	a4,4(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:45
    
    /* Clear configuration. */
    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
80102890:	fe0407a3          	sb	zero,-17(s0)
80102894:	fd842783          	lw	a5,-40(s0)
80102898:	fef42423          	sw	a5,-24(s0)
8010289c:	0280006f          	j	801028c4 <GPIO_init+0x74>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:47 (discriminator 3)
    {
        HW_set_8bit_reg( cfg_reg_addr, 0 );
801028a0:	00000593          	li	a1,0
801028a4:	fe842503          	lw	a0,-24(s0)
801028a8:	828ff0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:48 (discriminator 3)
        cfg_reg_addr += 4;
801028ac:	fe842783          	lw	a5,-24(s0)
801028b0:	00478793          	addi	a5,a5,4
801028b4:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:45 (discriminator 3)
    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
801028b8:	fef44783          	lbu	a5,-17(s0)
801028bc:	00178793          	addi	a5,a5,1
801028c0:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:45 (discriminator 1)
801028c4:	fef44703          	lbu	a4,-17(s0)
801028c8:	01f00793          	li	a5,31
801028cc:	fce7fae3          	bgeu	a5,a4,801028a0 <GPIO_init+0x50>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:51
    }
    /* Clear any pending interrupts */
    switch( this_gpio->apb_bus_width )
801028d0:	fdc42783          	lw	a5,-36(s0)
801028d4:	0047a783          	lw	a5,4(a5)
801028d8:	00100713          	li	a4,1
801028dc:	02e78663          	beq	a5,a4,80102908 <GPIO_init+0xb8>
801028e0:	06078263          	beqz	a5,80102944 <GPIO_init+0xf4>
801028e4:	00200713          	li	a4,2
801028e8:	0ce79063          	bne	a5,a4,801029a8 <GPIO_init+0x158>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:54
    {
        case GPIO_APB_32_BITS_BUS:
            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
801028ec:	fdc42783          	lw	a5,-36(s0)
801028f0:	0007a783          	lw	a5,0(a5)
801028f4:	08078793          	addi	a5,a5,128
801028f8:	fff00593          	li	a1,-1
801028fc:	00078513          	mv	a0,a5
80102900:	f41fe0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:55
            break;
80102904:	0ac0006f          	j	801029b0 <GPIO_init+0x160>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:58
            
        case GPIO_APB_16_BITS_BUS:
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
80102908:	fdc42783          	lw	a5,-36(s0)
8010290c:	0007a783          	lw	a5,0(a5)
80102910:	08078713          	addi	a4,a5,128
80102914:	000107b7          	lui	a5,0x10
80102918:	fff78593          	addi	a1,a5,-1 # ffff <STACK_SIZE+0xefff>
8010291c:	00070513          	mv	a0,a4
80102920:	f69fe0ef          	jal	ra,80101888 <HW_set_16bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:59
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
80102924:	fdc42783          	lw	a5,-36(s0)
80102928:	0007a783          	lw	a5,0(a5)
8010292c:	08478713          	addi	a4,a5,132
80102930:	000107b7          	lui	a5,0x10
80102934:	fff78593          	addi	a1,a5,-1 # ffff <STACK_SIZE+0xefff>
80102938:	00070513          	mv	a0,a4
8010293c:	f4dfe0ef          	jal	ra,80101888 <HW_set_16bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:60
            break;
80102940:	0700006f          	j	801029b0 <GPIO_init+0x160>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:63
            
        case GPIO_APB_8_BITS_BUS:
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
80102944:	fdc42783          	lw	a5,-36(s0)
80102948:	0007a783          	lw	a5,0(a5)
8010294c:	08078793          	addi	a5,a5,128
80102950:	0ff00593          	li	a1,255
80102954:	00078513          	mv	a0,a5
80102958:	f79fe0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:64
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
8010295c:	fdc42783          	lw	a5,-36(s0)
80102960:	0007a783          	lw	a5,0(a5)
80102964:	08478793          	addi	a5,a5,132
80102968:	0ff00593          	li	a1,255
8010296c:	00078513          	mv	a0,a5
80102970:	f61fe0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:65
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
80102974:	fdc42783          	lw	a5,-36(s0)
80102978:	0007a783          	lw	a5,0(a5)
8010297c:	08878793          	addi	a5,a5,136
80102980:	0ff00593          	li	a1,255
80102984:	00078513          	mv	a0,a5
80102988:	f49fe0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:66
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
8010298c:	fdc42783          	lw	a5,-36(s0)
80102990:	0007a783          	lw	a5,0(a5)
80102994:	08c78793          	addi	a5,a5,140
80102998:	0ff00593          	li	a1,255
8010299c:	00078513          	mv	a0,a5
801029a0:	f31fe0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:67
            break;
801029a4:	00c0006f          	j	801029b0 <GPIO_init+0x160>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:70 (discriminator 1)
            
        default:
            HAL_ASSERT(0);
801029a8:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:71 (discriminator 1)
            break;
801029ac:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:73
    }
}
801029b0:	00000013          	nop
801029b4:	02c12083          	lw	ra,44(sp)
801029b8:	02812403          	lw	s0,40(sp)
801029bc:	03010113          	addi	sp,sp,48
801029c0:	00008067          	ret

801029c4 <GPIO_set_output>:
GPIO_set_output():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:232
(
    gpio_instance_t *   this_gpio,
    gpio_id_t           port_id,
    uint8_t             value
)
{
801029c4:	fd010113          	addi	sp,sp,-48
801029c8:	02112623          	sw	ra,44(sp)
801029cc:	02812423          	sw	s0,40(sp)
801029d0:	03010413          	addi	s0,sp,48
801029d4:	fca42e23          	sw	a0,-36(s0)
801029d8:	fcb42c23          	sw	a1,-40(s0)
801029dc:	00060793          	mv	a5,a2
801029e0:	fcf40ba3          	sb	a5,-41(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:233
    HAL_ASSERT( port_id < NB_OF_GPIO );
801029e4:	fd842703          	lw	a4,-40(s0)
801029e8:	01f00793          	li	a5,31
801029ec:	00e7f463          	bgeu	a5,a4,801029f4 <GPIO_set_output+0x30>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:233 (discriminator 1)
801029f0:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:236
    
            
    switch( this_gpio->apb_bus_width )
801029f4:	fdc42783          	lw	a5,-36(s0)
801029f8:	0047a783          	lw	a5,4(a5)
801029fc:	00100713          	li	a4,1
80102a00:	0ae78863          	beq	a5,a4,80102ab0 <GPIO_set_output+0xec>
80102a04:	16078e63          	beqz	a5,80102b80 <GPIO_set_output+0x1bc>
80102a08:	00200713          	li	a4,2
80102a0c:	24e79263          	bne	a5,a4,80102c50 <GPIO_set_output+0x28c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:242
    {
        case GPIO_APB_32_BITS_BUS:
            {
                uint32_t outputs_state;
                
                outputs_state = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
80102a10:	fdc42783          	lw	a5,-36(s0)
80102a14:	0007a783          	lw	a5,0(a5)
80102a18:	0a078793          	addi	a5,a5,160
80102a1c:	00078513          	mv	a0,a5
80102a20:	e29fe0ef          	jal	ra,80101848 <HW_get_32bit_reg>
80102a24:	fea42623          	sw	a0,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:243
                if ( 0 == value )
80102a28:	fd744783          	lbu	a5,-41(s0)
80102a2c:	02079463          	bnez	a5,80102a54 <GPIO_set_output+0x90>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:245
                {
                    outputs_state &= ~(1 << port_id);
80102a30:	fd842783          	lw	a5,-40(s0)
80102a34:	00100713          	li	a4,1
80102a38:	00f717b3          	sll	a5,a4,a5
80102a3c:	fff7c793          	not	a5,a5
80102a40:	00078713          	mv	a4,a5
80102a44:	fec42783          	lw	a5,-20(s0)
80102a48:	00e7f7b3          	and	a5,a5,a4
80102a4c:	fef42623          	sw	a5,-20(s0)
80102a50:	0200006f          	j	80102a70 <GPIO_set_output+0xac>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:249
                }
                else
                {
                    outputs_state |= 1 << port_id;
80102a54:	fd842783          	lw	a5,-40(s0)
80102a58:	00100713          	li	a4,1
80102a5c:	00f717b3          	sll	a5,a4,a5
80102a60:	00078713          	mv	a4,a5
80102a64:	fec42783          	lw	a5,-20(s0)
80102a68:	00e7e7b3          	or	a5,a5,a4
80102a6c:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:251
                }
                HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
80102a70:	fdc42783          	lw	a5,-36(s0)
80102a74:	0007a783          	lw	a5,0(a5)
80102a78:	0a078793          	addi	a5,a5,160
80102a7c:	fec42583          	lw	a1,-20(s0)
80102a80:	00078513          	mv	a0,a5
80102a84:	dbdfe0ef          	jal	ra,80101840 <HW_set_32bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:260
                 * the expected value may indicate that some of the GPIOs may not exist due to
                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
                 * It may also indicate that the base address or APB bus width passed as
                 * parameter to the GPIO_init() function do not match the hardware design.
                 */
                HAL_ASSERT( HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT ) == outputs_state );
80102a88:	fdc42783          	lw	a5,-36(s0)
80102a8c:	0007a783          	lw	a5,0(a5)
80102a90:	0a078793          	addi	a5,a5,160
80102a94:	00078513          	mv	a0,a5
80102a98:	db1fe0ef          	jal	ra,80101848 <HW_get_32bit_reg>
80102a9c:	00050713          	mv	a4,a0
80102aa0:	fec42783          	lw	a5,-20(s0)
80102aa4:	1ae78a63          	beq	a5,a4,80102c58 <GPIO_set_output+0x294>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:260 (discriminator 1)
80102aa8:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:262 (discriminator 1)
            }
            break;
80102aac:	1ac0006f          	j	80102c58 <GPIO_set_output+0x294>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:267
            
        case GPIO_APB_16_BITS_BUS:
            {
                uint16_t outputs_state;
                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 4) * 4);
80102ab0:	fdc42783          	lw	a5,-36(s0)
80102ab4:	0007a703          	lw	a4,0(a5)
80102ab8:	fd842783          	lw	a5,-40(s0)
80102abc:	0047d793          	srli	a5,a5,0x4
80102ac0:	00279793          	slli	a5,a5,0x2
80102ac4:	00f707b3          	add	a5,a4,a5
80102ac8:	0a078793          	addi	a5,a5,160
80102acc:	fef42223          	sw	a5,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:269
                
                outputs_state = HW_get_16bit_reg( gpio_out_reg_addr );
80102ad0:	fe442503          	lw	a0,-28(s0)
80102ad4:	dbdfe0ef          	jal	ra,80101890 <HW_get_16bit_reg>
80102ad8:	00050793          	mv	a5,a0
80102adc:	fef41523          	sh	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:270
                if ( 0 == value )
80102ae0:	fd744783          	lbu	a5,-41(s0)
80102ae4:	04079063          	bnez	a5,80102b24 <GPIO_set_output+0x160>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:272
                {
                    outputs_state &= ~(1 << (port_id & 0x0F));
80102ae8:	fd842783          	lw	a5,-40(s0)
80102aec:	00f7f793          	andi	a5,a5,15
80102af0:	00100713          	li	a4,1
80102af4:	00f717b3          	sll	a5,a4,a5
80102af8:	01079793          	slli	a5,a5,0x10
80102afc:	4107d793          	srai	a5,a5,0x10
80102b00:	fff7c793          	not	a5,a5
80102b04:	01079713          	slli	a4,a5,0x10
80102b08:	41075713          	srai	a4,a4,0x10
80102b0c:	fea41783          	lh	a5,-22(s0)
80102b10:	00f777b3          	and	a5,a4,a5
80102b14:	01079793          	slli	a5,a5,0x10
80102b18:	4107d793          	srai	a5,a5,0x10
80102b1c:	fef41523          	sh	a5,-22(s0)
80102b20:	0300006f          	j	80102b50 <GPIO_set_output+0x18c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:276
                }
                else
                {
                    outputs_state |= 1 << (port_id & 0x0F);
80102b24:	fd842783          	lw	a5,-40(s0)
80102b28:	00f7f793          	andi	a5,a5,15
80102b2c:	00100713          	li	a4,1
80102b30:	00f717b3          	sll	a5,a4,a5
80102b34:	01079713          	slli	a4,a5,0x10
80102b38:	41075713          	srai	a4,a4,0x10
80102b3c:	fea41783          	lh	a5,-22(s0)
80102b40:	00f767b3          	or	a5,a4,a5
80102b44:	01079793          	slli	a5,a5,0x10
80102b48:	4107d793          	srai	a5,a5,0x10
80102b4c:	fef41523          	sh	a5,-22(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:278
                }
                HW_set_16bit_reg( gpio_out_reg_addr, outputs_state );
80102b50:	fea45783          	lhu	a5,-22(s0)
80102b54:	00078593          	mv	a1,a5
80102b58:	fe442503          	lw	a0,-28(s0)
80102b5c:	d2dfe0ef          	jal	ra,80101888 <HW_set_16bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:287
                 * the expected value may indicate that some of the GPIOs may not exist due to
                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
                 * It may also indicate that the base address or APB bus width passed as
                 * parameter to the GPIO_init() function do not match the hardware design.
                 */
                HAL_ASSERT( HW_get_16bit_reg( gpio_out_reg_addr ) == outputs_state );
80102b60:	fe442503          	lw	a0,-28(s0)
80102b64:	d2dfe0ef          	jal	ra,80101890 <HW_get_16bit_reg>
80102b68:	00050793          	mv	a5,a0
80102b6c:	00078713          	mv	a4,a5
80102b70:	fea45783          	lhu	a5,-22(s0)
80102b74:	0ee78663          	beq	a5,a4,80102c60 <GPIO_set_output+0x29c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:287 (discriminator 1)
80102b78:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:289 (discriminator 1)
            }
            break;
80102b7c:	0e40006f          	j	80102c60 <GPIO_set_output+0x29c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:294
            
        case GPIO_APB_8_BITS_BUS:
            {
                uint8_t outputs_state;
                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 3) * 4);
80102b80:	fdc42783          	lw	a5,-36(s0)
80102b84:	0007a703          	lw	a4,0(a5)
80102b88:	fd842783          	lw	a5,-40(s0)
80102b8c:	0037d793          	srli	a5,a5,0x3
80102b90:	00279793          	slli	a5,a5,0x2
80102b94:	00f707b3          	add	a5,a4,a5
80102b98:	0a078793          	addi	a5,a5,160
80102b9c:	fef42023          	sw	a5,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:296
                
                outputs_state = HW_get_8bit_reg( gpio_out_reg_addr );
80102ba0:	fe042503          	lw	a0,-32(s0)
80102ba4:	d35fe0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80102ba8:	00050793          	mv	a5,a0
80102bac:	fef404a3          	sb	a5,-23(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:297
                if ( 0 == value )
80102bb0:	fd744783          	lbu	a5,-41(s0)
80102bb4:	04079063          	bnez	a5,80102bf4 <GPIO_set_output+0x230>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:299
                {
                    outputs_state &= ~(1 << (port_id & 0x07));
80102bb8:	fd842783          	lw	a5,-40(s0)
80102bbc:	0077f793          	andi	a5,a5,7
80102bc0:	00100713          	li	a4,1
80102bc4:	00f717b3          	sll	a5,a4,a5
80102bc8:	01879793          	slli	a5,a5,0x18
80102bcc:	4187d793          	srai	a5,a5,0x18
80102bd0:	fff7c793          	not	a5,a5
80102bd4:	01879713          	slli	a4,a5,0x18
80102bd8:	41875713          	srai	a4,a4,0x18
80102bdc:	fe940783          	lb	a5,-23(s0)
80102be0:	00f777b3          	and	a5,a4,a5
80102be4:	01879793          	slli	a5,a5,0x18
80102be8:	4187d793          	srai	a5,a5,0x18
80102bec:	fef404a3          	sb	a5,-23(s0)
80102bf0:	0300006f          	j	80102c20 <GPIO_set_output+0x25c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:303
                }
                else
                {
                    outputs_state |= 1 << (port_id & 0x07);
80102bf4:	fd842783          	lw	a5,-40(s0)
80102bf8:	0077f793          	andi	a5,a5,7
80102bfc:	00100713          	li	a4,1
80102c00:	00f717b3          	sll	a5,a4,a5
80102c04:	01879713          	slli	a4,a5,0x18
80102c08:	41875713          	srai	a4,a4,0x18
80102c0c:	fe940783          	lb	a5,-23(s0)
80102c10:	00f767b3          	or	a5,a4,a5
80102c14:	01879793          	slli	a5,a5,0x18
80102c18:	4187d793          	srai	a5,a5,0x18
80102c1c:	fef404a3          	sb	a5,-23(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:305
                }
                HW_set_8bit_reg( gpio_out_reg_addr, outputs_state );
80102c20:	fe944783          	lbu	a5,-23(s0)
80102c24:	00078593          	mv	a1,a5
80102c28:	fe042503          	lw	a0,-32(s0)
80102c2c:	ca5fe0ef          	jal	ra,801018d0 <HW_set_8bit_reg>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:314
                 * the expected value may indicate that some of the GPIOs may not exist due to
                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
                 * It may also indicate that the base address or APB bus width passed as
                 * parameter to the GPIO_init() function do not match the hardware design.
                 */
                HAL_ASSERT( HW_get_8bit_reg( gpio_out_reg_addr ) == outputs_state );
80102c30:	fe042503          	lw	a0,-32(s0)
80102c34:	ca5fe0ef          	jal	ra,801018d8 <HW_get_8bit_reg>
80102c38:	00050793          	mv	a5,a0
80102c3c:	00078713          	mv	a4,a5
80102c40:	fe944783          	lbu	a5,-23(s0)
80102c44:	02e78263          	beq	a5,a4,80102c68 <GPIO_set_output+0x2a4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:314 (discriminator 1)
80102c48:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:316 (discriminator 1)
            }
            break;
80102c4c:	01c0006f          	j	80102c68 <GPIO_set_output+0x2a4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:319 (discriminator 1)
            
        default:
            HAL_ASSERT(0);
80102c50:	00100073          	ebreak
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:320 (discriminator 1)
            break;
80102c54:	0180006f          	j	80102c6c <GPIO_set_output+0x2a8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:262
            break;
80102c58:	00000013          	nop
80102c5c:	0100006f          	j	80102c6c <GPIO_set_output+0x2a8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:289
            break;
80102c60:	00000013          	nop
80102c64:	0080006f          	j	80102c6c <GPIO_set_output+0x2a8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:316
            break;
80102c68:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../drivers/CoreGPIO/core_gpio.c:322
    }
}
80102c6c:	00000013          	nop
80102c70:	02c12083          	lw	ra,44(sp)
80102c74:	02812403          	lw	s0,40(sp)
80102c78:	03010113          	addi	sp,sp,48
80102c7c:	00008067          	ret

80102c80 <MRV_disable_interrupts>:
MRV_disable_interrupts():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\miv_rv32_hal/miv_rv32_hal.h:630

  @return
  This functions returns the CORE_GPR_DED_RESET_REG bit value.
 */
static inline void MRV_disable_interrupts(void)
{
80102c80:	fe010113          	addi	sp,sp,-32
80102c84:	00812e23          	sw	s0,28(sp)
80102c88:	02010413          	addi	s0,sp,32
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\miv_rv32_hal/miv_rv32_hal.h:631
    clear_csr(mstatus, MSTATUS_MPIE);
80102c8c:	08000793          	li	a5,128
80102c90:	3007b7f3          	csrrc	a5,mstatus,a5
80102c94:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\miv_rv32_hal/miv_rv32_hal.h:632
    clear_csr(mstatus, MSTATUS_MIE);
80102c98:	300477f3          	csrrci	a5,mstatus,8
80102c9c:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\miv_rv32_hal/miv_rv32_hal.h:633
}
80102ca0:	00000013          	nop
80102ca4:	01c12403          	lw	s0,28(sp)
80102ca8:	02010113          	addi	sp,sp,32
80102cac:	00008067          	ret

80102cb0 <delay1>:
delay1():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:89

/////////////////
#define BUFFER_SIZE 4096

void delay1(volatile uint32_t n)
{
80102cb0:	fe010113          	addi	sp,sp,-32
80102cb4:	00812e23          	sw	s0,28(sp)
80102cb8:	02010413          	addi	s0,sp,32
80102cbc:	fea42623          	sw	a0,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:90
	while(n)
80102cc0:	0100006f          	j	80102cd0 <delay1+0x20>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:91
		n--;
80102cc4:	fec42783          	lw	a5,-20(s0)
80102cc8:	fff78793          	addi	a5,a5,-1
80102ccc:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:90
	while(n)
80102cd0:	fec42783          	lw	a5,-20(s0)
80102cd4:	fe0798e3          	bnez	a5,80102cc4 <delay1+0x14>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:92
}
80102cd8:	00000013          	nop
80102cdc:	01c12403          	lw	s0,28(sp)
80102ce0:	02010113          	addi	sp,sp,32
80102ce4:	00008067          	ret

80102ce8 <read_page_from_host_through_uart>:
read_page_from_host_through_uart():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:170
static uint32_t read_page_from_host_through_uart
(
		uint8_t * g_buffer,
		uint32_t length
)
{
80102ce8:	fc010113          	addi	sp,sp,-64
80102cec:	02112e23          	sw	ra,60(sp)
80102cf0:	02812c23          	sw	s0,56(sp)
80102cf4:	04010413          	addi	s0,sp,64
80102cf8:	fca42623          	sw	a0,-52(s0)
80102cfc:	fcb42423          	sw	a1,-56(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:172
	uint32_t num_bytes,factor,temp;
	volatile uint32_t i = 0;
80102d00:	fc042c23          	sw	zero,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:173
	num_bytes = length;
80102d04:	fc842783          	lw	a5,-56(s0)
80102d08:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:175
	char crc;
	size_t rx_size = 0;
80102d0c:	fe042023          	sw	zero,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:181


	uint8_t rx_buff[1],temp_add[2];
	//Write Ack "b" to indicate beginning of the transaction from the target

	if(g_src_image_target_address + length > g_file_size )
80102d10:	8281a703          	lw	a4,-2008(gp) # 70000028 <g_src_image_target_address>
80102d14:	fc842783          	lw	a5,-56(s0)
80102d18:	00f70733          	add	a4,a4,a5
80102d1c:	82c1a783          	lw	a5,-2004(gp) # 7000002c <g_file_size>
80102d20:	00e7fa63          	bgeu	a5,a4,80102d34 <read_page_from_host_through_uart+0x4c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:183
	{
		num_bytes = g_file_size - g_src_image_target_address;
80102d24:	82c1a703          	lw	a4,-2004(gp) # 7000002c <g_file_size>
80102d28:	8281a783          	lw	a5,-2008(gp) # 70000028 <g_src_image_target_address>
80102d2c:	40f707b3          	sub	a5,a4,a5
80102d30:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:185
	}
	if(g_src_image_target_address>= g_file_size)
80102d34:	8281a703          	lw	a4,-2008(gp) # 70000028 <g_src_image_target_address>
80102d38:	82c1a783          	lw	a5,-2004(gp) # 7000002c <g_file_size>
80102d3c:	00f76663          	bltu	a4,a5,80102d48 <read_page_from_host_through_uart+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:187
	{
		return 0;
80102d40:	00000793          	li	a5,0
80102d44:	3480006f          	j	8010308c <read_page_from_host_through_uart+0x3a4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:189
	}
	CRCFAIL:
80102d48:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:192


	UART_send(&g_uart, (const uint8_t * )"b",1);
80102d4c:	00100613          	li	a2,1
80102d50:	801047b7          	lui	a5,0x80104
80102d54:	bfc78593          	addi	a1,a5,-1028 # 80103bfc <__data_load+0xfffffeec>
80102d58:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102d5c:	d95fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:195
	//poll for Ack message from the host as an acknowledgment that the host is ready for receiving the transaction

	while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102d60:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:195 (discriminator 1)
80102d64:	fd440793          	addi	a5,s0,-44
80102d68:	00100613          	li	a2,1
80102d6c:	00078593          	mv	a1,a5
80102d70:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102d74:	e55fe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102d78:	00050793          	mv	a5,a0
80102d7c:	fe0784e3          	beqz	a5,80102d64 <read_page_from_host_through_uart+0x7c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:199
		;

#if 1
	temp = g_src_image_target_address/4096;
80102d80:	8281a783          	lw	a5,-2008(gp) # 70000028 <g_src_image_target_address>
80102d84:	00c7d793          	srli	a5,a5,0xc
80102d88:	fcf42e23          	sw	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:200
	temp_add[0] = temp&0xFF;
80102d8c:	fdc42783          	lw	a5,-36(s0)
80102d90:	0ff7f793          	andi	a5,a5,255
80102d94:	fcf40823          	sb	a5,-48(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:201
	temp_add[1] = (temp>>8)&0xFF;
80102d98:	fdc42783          	lw	a5,-36(s0)
80102d9c:	0087d793          	srli	a5,a5,0x8
80102da0:	0ff7f793          	andi	a5,a5,255
80102da4:	fcf408a3          	sb	a5,-47(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:202
	if(rx_buff[0]== 'a')
80102da8:	fd444703          	lbu	a4,-44(s0)
80102dac:	06100793          	li	a5,97
80102db0:	08f71e63          	bne	a4,a5,80102e4c <read_page_from_host_through_uart+0x164>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:204
	{
		UART_send(&g_uart,&temp_add[0],1);
80102db4:	fd040793          	addi	a5,s0,-48
80102db8:	00100613          	li	a2,1
80102dbc:	00078593          	mv	a1,a5
80102dc0:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102dc4:	d2dfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:205
		for(i=0;i<500;i++);
80102dc8:	fc042c23          	sw	zero,-40(s0)
80102dcc:	0100006f          	j	80102ddc <read_page_from_host_through_uart+0xf4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:205 (discriminator 3)
80102dd0:	fd842783          	lw	a5,-40(s0)
80102dd4:	00178793          	addi	a5,a5,1
80102dd8:	fcf42c23          	sw	a5,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:205 (discriminator 1)
80102ddc:	fd842703          	lw	a4,-40(s0)
80102de0:	1f300793          	li	a5,499
80102de4:	fee7f6e3          	bgeu	a5,a4,80102dd0 <read_page_from_host_through_uart+0xe8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:206
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102de8:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:206 (discriminator 1)
80102dec:	fd440793          	addi	a5,s0,-44
80102df0:	00100613          	li	a2,1
80102df4:	00078593          	mv	a1,a5
80102df8:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102dfc:	dcdfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102e00:	00050793          	mv	a5,a0
80102e04:	fe0784e3          	beqz	a5,80102dec <read_page_from_host_through_uart+0x104>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:209
			;

		if(rx_buff[0]== 'a')
80102e08:	fd444703          	lbu	a4,-44(s0)
80102e0c:	06100793          	li	a5,97
80102e10:	00f71e63          	bne	a4,a5,80102e2c <read_page_from_host_through_uart+0x144>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:210
			UART_send(&g_uart,&temp_add[1],1);
80102e14:	fd040793          	addi	a5,s0,-48
80102e18:	00178793          	addi	a5,a5,1
80102e1c:	00100613          	li	a2,1
80102e20:	00078593          	mv	a1,a5
80102e24:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102e28:	cc9fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:211
		for(i=0;i<500;i++);
80102e2c:	fc042c23          	sw	zero,-40(s0)
80102e30:	0100006f          	j	80102e40 <read_page_from_host_through_uart+0x158>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:211 (discriminator 3)
80102e34:	fd842783          	lw	a5,-40(s0)
80102e38:	00178793          	addi	a5,a5,1
80102e3c:	fcf42c23          	sw	a5,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:211 (discriminator 1)
80102e40:	fd842703          	lw	a4,-40(s0)
80102e44:	1f300793          	li	a5,499
80102e48:	fee7f6e3          	bgeu	a5,a4,80102e34 <read_page_from_host_through_uart+0x14c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:216

	}


	while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102e4c:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:216 (discriminator 1)
80102e50:	fd440793          	addi	a5,s0,-44
80102e54:	00100613          	li	a2,1
80102e58:	00078593          	mv	a1,a5
80102e5c:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102e60:	d69fe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102e64:	00050793          	mv	a5,a0
80102e68:	fe0784e3          	beqz	a5,80102e50 <read_page_from_host_through_uart+0x168>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:220
		;
#endif

	temp_add[0] = num_bytes&0xFF;
80102e6c:	fec42783          	lw	a5,-20(s0)
80102e70:	0ff7f793          	andi	a5,a5,255
80102e74:	fcf40823          	sb	a5,-48(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:221
	temp_add[1] = (num_bytes>>8)&0xFF;
80102e78:	fec42783          	lw	a5,-20(s0)
80102e7c:	0087d793          	srli	a5,a5,0x8
80102e80:	0ff7f793          	andi	a5,a5,255
80102e84:	fcf408a3          	sb	a5,-47(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:222
	if(rx_buff[0]== 'a')
80102e88:	fd444703          	lbu	a4,-44(s0)
80102e8c:	06100793          	li	a5,97
80102e90:	08f71e63          	bne	a4,a5,80102f2c <read_page_from_host_through_uart+0x244>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:225
	{

		UART_send(&g_uart,&temp_add[0],1);
80102e94:	fd040793          	addi	a5,s0,-48
80102e98:	00100613          	li	a2,1
80102e9c:	00078593          	mv	a1,a5
80102ea0:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102ea4:	c4dfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:226
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102ea8:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:226 (discriminator 1)
80102eac:	fd440793          	addi	a5,s0,-44
80102eb0:	00100613          	li	a2,1
80102eb4:	00078593          	mv	a1,a5
80102eb8:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102ebc:	d0dfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102ec0:	00050793          	mv	a5,a0
80102ec4:	fe0784e3          	beqz	a5,80102eac <read_page_from_host_through_uart+0x1c4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:228
			;
		for(i=0;i<500;i++);
80102ec8:	fc042c23          	sw	zero,-40(s0)
80102ecc:	0100006f          	j	80102edc <read_page_from_host_through_uart+0x1f4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:228 (discriminator 3)
80102ed0:	fd842783          	lw	a5,-40(s0)
80102ed4:	00178793          	addi	a5,a5,1
80102ed8:	fcf42c23          	sw	a5,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:228 (discriminator 1)
80102edc:	fd842703          	lw	a4,-40(s0)
80102ee0:	1f300793          	li	a5,499
80102ee4:	fee7f6e3          	bgeu	a5,a4,80102ed0 <read_page_from_host_through_uart+0x1e8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:229
		if(rx_buff[0]== 'a')
80102ee8:	fd444703          	lbu	a4,-44(s0)
80102eec:	06100793          	li	a5,97
80102ef0:	00f71e63          	bne	a4,a5,80102f0c <read_page_from_host_through_uart+0x224>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:230
			UART_send(&g_uart,&temp_add[1],1);
80102ef4:	fd040793          	addi	a5,s0,-48
80102ef8:	00178793          	addi	a5,a5,1
80102efc:	00100613          	li	a2,1
80102f00:	00078593          	mv	a1,a5
80102f04:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102f08:	be9fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:231
		for(i=0;i<500;i++);
80102f0c:	fc042c23          	sw	zero,-40(s0)
80102f10:	0100006f          	j	80102f20 <read_page_from_host_through_uart+0x238>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:231 (discriminator 3)
80102f14:	fd842783          	lw	a5,-40(s0)
80102f18:	00178793          	addi	a5,a5,1
80102f1c:	fcf42c23          	sw	a5,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:231 (discriminator 1)
80102f20:	fd842703          	lw	a4,-40(s0)
80102f24:	1f300793          	li	a5,499
80102f28:	fee7f6e3          	bgeu	a5,a4,80102f14 <read_page_from_host_through_uart+0x22c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:235
	}

	//poll for Ack message from the host as an acknowledgment that the host received the return bytes
	while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102f2c:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:235 (discriminator 1)
80102f30:	fd440793          	addi	a5,s0,-44
80102f34:	00100613          	li	a2,1
80102f38:	00078593          	mv	a1,a5
80102f3c:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102f40:	c89fe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102f44:	00050793          	mv	a5,a0
80102f48:	fe0784e3          	beqz	a5,80102f30 <read_page_from_host_through_uart+0x248>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:239
		;

#if 1
	if(rx_buff[0]== 'n')
80102f4c:	fd444703          	lbu	a4,-44(s0)
80102f50:	06e00793          	li	a5,110
80102f54:	06f71263          	bne	a4,a5,80102fb8 <read_page_from_host_through_uart+0x2d0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:241
	{
		for(i=0;i<num_bytes;i++)
80102f58:	fc042c23          	sw	zero,-40(s0)
80102f5c:	0480006f          	j	80102fa4 <read_page_from_host_through_uart+0x2bc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:243
		{
			rx_buff[0] = 0;
80102f60:	fc040a23          	sb	zero,-44(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:244
			while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102f64:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:244 (discriminator 1)
80102f68:	fd440793          	addi	a5,s0,-44
80102f6c:	00100613          	li	a2,1
80102f70:	00078593          	mv	a1,a5
80102f74:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102f78:	c51fe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102f7c:	00050793          	mv	a5,a0
80102f80:	fe0784e3          	beqz	a5,80102f68 <read_page_from_host_through_uart+0x280>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:246 (discriminator 2)
				;
			g_buffer[i] = rx_buff[0];
80102f84:	fd842783          	lw	a5,-40(s0)
80102f88:	fcc42703          	lw	a4,-52(s0)
80102f8c:	00f707b3          	add	a5,a4,a5
80102f90:	fd444703          	lbu	a4,-44(s0)
80102f94:	00e78023          	sb	a4,0(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:241 (discriminator 2)
		for(i=0;i<num_bytes;i++)
80102f98:	fd842783          	lw	a5,-40(s0)
80102f9c:	00178793          	addi	a5,a5,1
80102fa0:	fcf42c23          	sw	a5,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:241 (discriminator 1)
80102fa4:	fd842783          	lw	a5,-40(s0)
80102fa8:	fec42703          	lw	a4,-20(s0)
80102fac:	fae7eae3          	bltu	a5,a4,80102f60 <read_page_from_host_through_uart+0x278>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:249

		}
		rx_size = num_bytes;
80102fb0:	fec42783          	lw	a5,-20(s0)
80102fb4:	fef42023          	sw	a5,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:254
	}
#endif


	UART_send(&g_uart, (const uint8_t * )"a",1);
80102fb8:	00100613          	li	a2,1
80102fbc:	801047b7          	lui	a5,0x80104
80102fc0:	c0078593          	addi	a1,a5,-1024 # 80103c00 <__data_load+0xfffffef0>
80102fc4:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102fc8:	b29fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:256

	while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80102fcc:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:256 (discriminator 1)
80102fd0:	fd440793          	addi	a5,s0,-44
80102fd4:	00100613          	li	a2,1
80102fd8:	00078593          	mv	a1,a5
80102fdc:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80102fe0:	be9fe0ef          	jal	ra,80101bc8 <UART_get_rx>
80102fe4:	00050793          	mv	a5,a0
80102fe8:	fe0784e3          	beqz	a5,80102fd0 <read_page_from_host_through_uart+0x2e8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:258
		;
	factor = 1;
80102fec:	00100793          	li	a5,1
80102ff0:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:259
	crc = 0;
80102ff4:	fe0403a3          	sb	zero,-25(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:260
	while((num_bytes-1)/factor)
80102ff8:	0340006f          	j	8010302c <read_page_from_host_through_uart+0x344>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:262
	{
		crc = crc^g_buffer[factor];
80102ffc:	fcc42703          	lw	a4,-52(s0)
80103000:	fe842783          	lw	a5,-24(s0)
80103004:	00f707b3          	add	a5,a4,a5
80103008:	0007c783          	lbu	a5,0(a5)
8010300c:	01879713          	slli	a4,a5,0x18
80103010:	41875713          	srai	a4,a4,0x18
80103014:	fe744783          	lbu	a5,-25(s0)
80103018:	00f747b3          	xor	a5,a4,a5
8010301c:	fef403a3          	sb	a5,-25(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:263
		factor = factor*2;
80103020:	fe842783          	lw	a5,-24(s0)
80103024:	00179793          	slli	a5,a5,0x1
80103028:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:260
	while((num_bytes-1)/factor)
8010302c:	fec42783          	lw	a5,-20(s0)
80103030:	fff78793          	addi	a5,a5,-1
80103034:	fe842703          	lw	a4,-24(s0)
80103038:	fce7f2e3          	bgeu	a5,a4,80102ffc <read_page_from_host_through_uart+0x314>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:265
	}
	if(crc == (char)rx_buff[0])
8010303c:	fd444703          	lbu	a4,-44(s0)
80103040:	fe744783          	lbu	a5,-25(s0)
80103044:	02f71863          	bne	a4,a5,80103074 <read_page_from_host_through_uart+0x38c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:267
	{
		g_src_image_target_address += rx_size;
80103048:	8281a703          	lw	a4,-2008(gp) # 70000028 <g_src_image_target_address>
8010304c:	fe042783          	lw	a5,-32(s0)
80103050:	00f70733          	add	a4,a4,a5
80103054:	82e1a423          	sw	a4,-2008(gp) # 70000028 <g_src_image_target_address>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:269

		UART_send(&g_uart, (const uint8_t * )"a",1);
80103058:	00100613          	li	a2,1
8010305c:	801047b7          	lui	a5,0x80104
80103060:	c0078593          	addi	a1,a5,-1024 # 80103c00 <__data_load+0xfffffef0>
80103064:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103068:	a89fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:277
	{
		UART_send(&g_uart,(const uint8_t * )"n",1);
		goto CRCFAIL;
	}

	return rx_size;
8010306c:	fe042783          	lw	a5,-32(s0)
80103070:	01c0006f          	j	8010308c <read_page_from_host_through_uart+0x3a4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:273
		UART_send(&g_uart,(const uint8_t * )"n",1);
80103074:	00100613          	li	a2,1
80103078:	801047b7          	lui	a5,0x80104
8010307c:	c0478593          	addi	a1,a5,-1020 # 80103c04 <__data_load+0xfffffef4>
80103080:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103084:	a6dfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:274
		goto CRCFAIL;
80103088:	cc5ff06f          	j	80102d4c <read_page_from_host_through_uart+0x64>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:278 (discriminator 1)
}
8010308c:	00078513          	mv	a0,a5
80103090:	03c12083          	lw	ra,60(sp)
80103094:	03812403          	lw	s0,56(sp)
80103098:	04010113          	addi	sp,sp,64
8010309c:	00008067          	ret

801030a0 <number_size>:
number_size():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:280
uint32_t number_size(uint8_t *ptr)
{
801030a0:	fd010113          	addi	sp,sp,-48
801030a4:	02812623          	sw	s0,44(sp)
801030a8:	03010413          	addi	s0,sp,48
801030ac:	fca42e23          	sw	a0,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:281
	uint32_t temp = 0,i=0;
801030b0:	fe042623          	sw	zero,-20(s0)
801030b4:	fe042423          	sw	zero,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:282
	while(*ptr != '\0' && i<9)
801030b8:	0480006f          	j	80103100 <number_size+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:284
	{
		temp = temp*10+*ptr -'0';
801030bc:	fec42703          	lw	a4,-20(s0)
801030c0:	00070793          	mv	a5,a4
801030c4:	00279793          	slli	a5,a5,0x2
801030c8:	00e787b3          	add	a5,a5,a4
801030cc:	00179793          	slli	a5,a5,0x1
801030d0:	00078713          	mv	a4,a5
801030d4:	fdc42783          	lw	a5,-36(s0)
801030d8:	0007c783          	lbu	a5,0(a5)
801030dc:	00f707b3          	add	a5,a4,a5
801030e0:	fd078793          	addi	a5,a5,-48
801030e4:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:285
		ptr++;
801030e8:	fdc42783          	lw	a5,-36(s0)
801030ec:	00178793          	addi	a5,a5,1
801030f0:	fcf42e23          	sw	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:286
		i++;
801030f4:	fe842783          	lw	a5,-24(s0)
801030f8:	00178793          	addi	a5,a5,1
801030fc:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:282
	while(*ptr != '\0' && i<9)
80103100:	fdc42783          	lw	a5,-36(s0)
80103104:	0007c783          	lbu	a5,0(a5)
80103108:	00078863          	beqz	a5,80103118 <number_size+0x78>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:282 (discriminator 1)
8010310c:	fe842703          	lw	a4,-24(s0)
80103110:	00800793          	li	a5,8
80103114:	fae7f4e3          	bgeu	a5,a4,801030bc <number_size+0x1c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:288
	}
	return temp;
80103118:	fec42783          	lw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:289
}
8010311c:	00078513          	mv	a0,a5
80103120:	02c12403          	lw	s0,44(sp)
80103124:	03010113          	addi	sp,sp,48
80103128:	00008067          	ret

8010312c <copy_to_flash>:
copy_to_flash():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:291
void copy_to_flash(uint8_t * g_buffer,uint32_t length)
{
8010312c:	fd010113          	addi	sp,sp,-48
80103130:	02112623          	sw	ra,44(sp)
80103134:	02812423          	sw	s0,40(sp)
80103138:	03010413          	addi	s0,sp,48
8010313c:	fca42e23          	sw	a0,-36(s0)
80103140:	fcb42c23          	sw	a1,-40(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:292
	uint32_t i=0;
80103144:	fe042623          	sw	zero,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:293
	for(i=0;i<8;i++)
80103148:	fe042623          	sw	zero,-20(s0)
8010314c:	0400006f          	j	8010318c <copy_to_flash+0x60>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:295 (discriminator 3)
	{
		FLASH_program(g_flash_address+i*512 , &g_buffer[i*512], 512);
80103150:	fec42783          	lw	a5,-20(s0)
80103154:	00979713          	slli	a4,a5,0x9
80103158:	8301a783          	lw	a5,-2000(gp) # 70000030 <g_flash_address>
8010315c:	00f706b3          	add	a3,a4,a5
80103160:	fec42783          	lw	a5,-20(s0)
80103164:	00979793          	slli	a5,a5,0x9
80103168:	fdc42703          	lw	a4,-36(s0)
8010316c:	00f707b3          	add	a5,a4,a5
80103170:	20000613          	li	a2,512
80103174:	00078593          	mv	a1,a5
80103178:	00068513          	mv	a0,a3
8010317c:	c35fd0ef          	jal	ra,80100db0 <FLASH_program>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:293 (discriminator 3)
	for(i=0;i<8;i++)
80103180:	fec42783          	lw	a5,-20(s0)
80103184:	00178793          	addi	a5,a5,1
80103188:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:293 (discriminator 1)
8010318c:	fec42703          	lw	a4,-20(s0)
80103190:	00700793          	li	a5,7
80103194:	fae7fee3          	bgeu	a5,a4,80103150 <copy_to_flash+0x24>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:297
	}
	g_flash_address = g_flash_address + BUFFER_SIZE;
80103198:	8301a703          	lw	a4,-2000(gp) # 70000030 <g_flash_address>
8010319c:	000017b7          	lui	a5,0x1
801031a0:	00f70733          	add	a4,a4,a5
801031a4:	82e1a823          	sw	a4,-2000(gp) # 70000030 <g_flash_address>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:298
}
801031a8:	00000013          	nop
801031ac:	02c12083          	lw	ra,44(sp)
801031b0:	02812403          	lw	s0,40(sp)
801031b4:	03010113          	addi	sp,sp,48
801031b8:	00008067          	ret

801031bc <load_spi_flash_with_images_thruough_uart_intf>:
load_spi_flash_with_images_thruough_uart_intf():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:301

void load_spi_flash_with_images_thruough_uart_intf()
{
801031bc:	fc010113          	addi	sp,sp,-64
801031c0:	02112e23          	sw	ra,60(sp)
801031c4:	02812c23          	sw	s0,56(sp)
801031c8:	04010413          	addi	s0,sp,64
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:302
	volatile uint32_t erase_address = 0;
801031cc:	fe042423          	sw	zero,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:303
	volatile uint32_t erase_count=0;
801031d0:	fe042223          	sw	zero,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:304
	volatile uint32_t i = 0,length = 0;
801031d4:	fe042023          	sw	zero,-32(s0)
801031d8:	fc042e23          	sw	zero,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:309


	uint8_t rx_buff[8],num[9];
	uint8_t  manufacturer_id;
	uint8_t  device_id,led_state = 0;
801031dc:	fe0407a3          	sb	zero,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:312


	while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
801031e0:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:312 (discriminator 1)
801031e4:	fd440793          	addi	a5,s0,-44
801031e8:	00100613          	li	a2,1
801031ec:	00078593          	mv	a1,a5
801031f0:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801031f4:	9d5fe0ef          	jal	ra,80101bc8 <UART_get_rx>
801031f8:	00050793          	mv	a5,a0
801031fc:	fe0784e3          	beqz	a5,801031e4 <load_spi_flash_with_images_thruough_uart_intf+0x28>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:314
		;
	if(rx_buff[0] == 's') //signal from host PC to proceed to erase the flash.
80103200:	fd444703          	lbu	a4,-44(s0)
80103204:	07300793          	li	a5,115
80103208:	00f71c63          	bne	a4,a5,80103220 <load_spi_flash_with_images_thruough_uart_intf+0x64>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:315
		UART_send(&g_uart, (const uint8_t * )"a",1);
8010320c:	00100613          	li	a2,1
80103210:	801047b7          	lui	a5,0x80104
80103214:	c0078593          	addi	a1,a5,-1024 # 80103c00 <__data_load+0xfffffef0>
80103218:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010321c:	8d5fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:317

	FLASH_init();
80103220:	f80fd0ef          	jal	ra,801009a0 <FLASH_init>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:319

	FLASH_global_unprotect();
80103224:	90dfd0ef          	jal	ra,80100b30 <FLASH_global_unprotect>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:320
	FLASH_read_device_id
80103228:	fc640713          	addi	a4,s0,-58
8010322c:	fc740793          	addi	a5,s0,-57
80103230:	00070593          	mv	a1,a4
80103234:	00078513          	mv	a0,a5
80103238:	facfd0ef          	jal	ra,801009e4 <FLASH_read_device_id>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:328
			&device_id
	);
	//UART_init( &g_uart, COREUARTAPB0_BASE_ADDR, 59, (DATA_8_BITS | NO_PARITY) );


	erase_address = erase_count = 0;
8010323c:	00000793          	li	a5,0
80103240:	fef42223          	sw	a5,-28(s0)
80103244:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:329
	for(erase_count = 0;erase_count<=16;erase_count++)  //1MB erase 64
80103248:	fe042223          	sw	zero,-28(s0)
8010324c:	0800006f          	j	801032cc <load_spi_flash_with_images_thruough_uart_intf+0x110>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:331
	{
		GPIO_set_output( &g_gpio, GPIO_0,led_state);
80103250:	fef44783          	lbu	a5,-17(s0)
80103254:	00078613          	mv	a2,a5
80103258:	00000593          	li	a1,0
8010325c:	88c18513          	addi	a0,gp,-1908 # 7000008c <g_gpio>
80103260:	f64ff0ef          	jal	ra,801029c4 <GPIO_set_output>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:332
		FLASH_erase_64k_block(erase_address);
80103264:	fe842783          	lw	a5,-24(s0)
80103268:	00078513          	mv	a0,a5
8010326c:	969fd0ef          	jal	ra,80100bd4 <FLASH_erase_64k_block>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:333
		delay1(500);
80103270:	1f400513          	li	a0,500
80103274:	a3dff0ef          	jal	ra,80102cb0 <delay1>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:334
		FLASH_read(erase_address,g_read_buf,32);
80103278:	fe842703          	lw	a4,-24(s0)
8010327c:	02000613          	li	a2,32
80103280:	700007b7          	lui	a5,0x70000
80103284:	09c78593          	addi	a1,a5,156 # 7000009c <g_read_buf>
80103288:	00070513          	mv	a0,a4
8010328c:	fe4fd0ef          	jal	ra,80100a70 <FLASH_read>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:335
		erase_address+=0x10000;
80103290:	fe842703          	lw	a4,-24(s0)
80103294:	000107b7          	lui	a5,0x10
80103298:	00f707b3          	add	a5,a4,a5
8010329c:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:336
		if(g_read_buf[0] != 0xFF)
801032a0:	700007b7          	lui	a5,0x70000
801032a4:	09c78793          	addi	a5,a5,156 # 7000009c <g_read_buf>
801032a8:	0007c703          	lbu	a4,0(a5)
801032ac:	0ff00793          	li	a5,255
801032b0:	02f71663          	bne	a4,a5,801032dc <load_spi_flash_with_images_thruough_uart_intf+0x120>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:341 (discriminator 2)
		{

			break;
		}
		led_state = led_state ^ 1;
801032b4:	fef44783          	lbu	a5,-17(s0)
801032b8:	0017c793          	xori	a5,a5,1
801032bc:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:329 (discriminator 2)
	for(erase_count = 0;erase_count<=16;erase_count++)  //1MB erase 64
801032c0:	fe442783          	lw	a5,-28(s0)
801032c4:	00178793          	addi	a5,a5,1
801032c8:	fef42223          	sw	a5,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:329 (discriminator 1)
801032cc:	fe442703          	lw	a4,-28(s0)
801032d0:	01000793          	li	a5,16
801032d4:	f6e7fee3          	bgeu	a5,a4,80103250 <load_spi_flash_with_images_thruough_uart_intf+0x94>
801032d8:	0080006f          	j	801032e0 <load_spi_flash_with_images_thruough_uart_intf+0x124>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:339
			break;
801032dc:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:343
	}
	if(erase_count == 5)
801032e0:	fe442703          	lw	a4,-28(s0)
801032e4:	00500793          	li	a5,5
801032e8:	00f71c63          	bne	a4,a5,80103300 <load_spi_flash_with_images_thruough_uart_intf+0x144>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:345
	{
		GPIO_set_output( &g_gpio, GPIO_0,1); //erase successful
801032ec:	00100613          	li	a2,1
801032f0:	00000593          	li	a1,0
801032f4:	88c18513          	addi	a0,gp,-1908 # 7000008c <g_gpio>
801032f8:	eccff0ef          	jal	ra,801029c4 <GPIO_set_output>
801032fc:	2ac0006f          	j	801035a8 <load_spi_flash_with_images_thruough_uart_intf+0x3ec>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:349
	}
	else
	{
		GPIO_set_output( &g_gpio, GPIO_0,0); //erase failed
80103300:	00000613          	li	a2,0
80103304:	00000593          	li	a1,0
80103308:	88c18513          	addi	a0,gp,-1908 # 7000008c <g_gpio>
8010330c:	eb8ff0ef          	jal	ra,801029c4 <GPIO_set_output>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:354
	}


#if 1
	while(no_of_files<MAX_FILES)
80103310:	2980006f          	j	801035a8 <load_spi_flash_with_images_thruough_uart_intf+0x3ec>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:357
	{

		g_flash_address = flash_address[no_of_files];
80103314:	8241c783          	lbu	a5,-2012(gp) # 70000024 <no_of_files>
80103318:	00078693          	mv	a3,a5
8010331c:	700007b7          	lui	a5,0x70000
80103320:	00078713          	mv	a4,a5
80103324:	00269793          	slli	a5,a3,0x2
80103328:	00f707b3          	add	a5,a4,a5
8010332c:	0007a703          	lw	a4,0(a5) # 70000000 <RAM_START_ADDRESS>
80103330:	82e1a823          	sw	a4,-2000(gp) # 70000030 <g_flash_address>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:358
		g_src_image_target_address = 0;
80103334:	8201a423          	sw	zero,-2008(gp) # 70000028 <g_src_image_target_address>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:360
		/* start the handshake with the host */
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80103338:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:360 (discriminator 1)
8010333c:	fd440793          	addi	a5,s0,-44
80103340:	00100613          	li	a2,1
80103344:	00078593          	mv	a1,a5
80103348:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010334c:	87dfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80103350:	00050793          	mv	a5,a0
80103354:	fe0784e3          	beqz	a5,8010333c <load_spi_flash_with_images_thruough_uart_intf+0x180>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:362
			;
		if(rx_buff[0] == 'h')
80103358:	fd444703          	lbu	a4,-44(s0)
8010335c:	06800793          	li	a5,104
80103360:	00f71c63          	bne	a4,a5,80103378 <load_spi_flash_with_images_thruough_uart_intf+0x1bc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:363
			UART_send(&g_uart, (const uint8_t * )"a",1);
80103364:	00100613          	li	a2,1
80103368:	801047b7          	lui	a5,0x80104
8010336c:	c0078593          	addi	a1,a5,-1024 # 80103c00 <__data_load+0xfffffef0>
80103370:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103374:	f7cfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:364
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80103378:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:364 (discriminator 1)
8010337c:	fd440793          	addi	a5,s0,-44
80103380:	00100613          	li	a2,1
80103384:	00078593          	mv	a1,a5
80103388:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010338c:	83dfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80103390:	00050793          	mv	a5,a0
80103394:	fe0784e3          	beqz	a5,8010337c <load_spi_flash_with_images_thruough_uart_intf+0x1c0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:366
			;
		if(rx_buff[0] == 'n')
80103398:	fd444703          	lbu	a4,-44(s0)
8010339c:	06e00793          	li	a5,110
801033a0:	00f71c63          	bne	a4,a5,801033b8 <load_spi_flash_with_images_thruough_uart_intf+0x1fc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:367
			UART_send(&g_uart, (const uint8_t * )"d", 1 );
801033a4:	00100613          	li	a2,1
801033a8:	801047b7          	lui	a5,0x80104
801033ac:	c0878593          	addi	a1,a5,-1016 # 80103c08 <__data_load+0xfffffef8>
801033b0:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801033b4:	f3cfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:368
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
801033b8:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:368 (discriminator 1)
801033bc:	fd440793          	addi	a5,s0,-44
801033c0:	00100613          	li	a2,1
801033c4:	00078593          	mv	a1,a5
801033c8:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801033cc:	ffcfe0ef          	jal	ra,80101bc8 <UART_get_rx>
801033d0:	00050793          	mv	a5,a0
801033d4:	fe0784e3          	beqz	a5,801033bc <load_spi_flash_with_images_thruough_uart_intf+0x200>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:370
			;
		if(rx_buff[0] == 's')
801033d8:	fd444703          	lbu	a4,-44(s0)
801033dc:	07300793          	li	a5,115
801033e0:	00f71c63          	bne	a4,a5,801033f8 <load_spi_flash_with_images_thruough_uart_intf+0x23c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:371
			UART_send(&g_uart, (const uint8_t * )"h", 1 );
801033e4:	00100613          	li	a2,1
801033e8:	801047b7          	lui	a5,0x80104
801033ec:	c0c78593          	addi	a1,a5,-1012 # 80103c0c <__data_load+0xfffffefc>
801033f0:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801033f4:	efcfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:372
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
801033f8:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:372 (discriminator 1)
801033fc:	fd440793          	addi	a5,s0,-44
80103400:	00100613          	li	a2,1
80103404:	00078593          	mv	a1,a5
80103408:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010340c:	fbcfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80103410:	00050793          	mv	a5,a0
80103414:	fe0784e3          	beqz	a5,801033fc <load_spi_flash_with_images_thruough_uart_intf+0x240>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:374
			;
		if(rx_buff[0] == 'a')
80103418:	fd444703          	lbu	a4,-44(s0)
8010341c:	06100793          	li	a5,97
80103420:	00f71c63          	bne	a4,a5,80103438 <load_spi_flash_with_images_thruough_uart_intf+0x27c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:375
			UART_send(&g_uart, (const uint8_t * )"k", 1 );
80103424:	00100613          	li	a2,1
80103428:	801047b7          	lui	a5,0x80104
8010342c:	c1078593          	addi	a1,a5,-1008 # 80103c10 <__data_load+0xffffff00>
80103430:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103434:	ebcfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:376
		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80103438:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:376 (discriminator 1)
8010343c:	fd440793          	addi	a5,s0,-44
80103440:	00100613          	li	a2,1
80103444:	00078593          	mv	a1,a5
80103448:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010344c:	f7cfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80103450:	00050793          	mv	a5,a0
80103454:	fe0784e3          	beqz	a5,8010343c <load_spi_flash_with_images_thruough_uart_intf+0x280>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:378
			;
		if(rx_buff[0] == 'e')
80103458:	fd444703          	lbu	a4,-44(s0)
8010345c:	06500793          	li	a5,101
80103460:	00f71c63          	bne	a4,a5,80103478 <load_spi_flash_with_images_thruough_uart_intf+0x2bc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:380
		{
			UART_send(&g_uart, (const uint8_t * )"r", 1 );
80103464:	00100613          	li	a2,1
80103468:	801047b7          	lui	a5,0x80104
8010346c:	c1478593          	addi	a1,a5,-1004 # 80103c14 <__data_load+0xffffff04>
80103470:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103474:	e7cfe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:385
		}
		/* poll for starting Ack message from the host as an acknowledgment
		                   that the host is ready to send file size */

		while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
80103478:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:385 (discriminator 1)
8010347c:	fd440793          	addi	a5,s0,-44
80103480:	00100613          	li	a2,1
80103484:	00078593          	mv	a1,a5
80103488:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010348c:	f3cfe0ef          	jal	ra,80101bc8 <UART_get_rx>
80103490:	00050793          	mv	a5,a0
80103494:	fe0784e3          	beqz	a5,8010347c <load_spi_flash_with_images_thruough_uart_intf+0x2c0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:387
			;
		UART_send(&g_uart, (const uint8_t * )"a",1);
80103498:	00100613          	li	a2,1
8010349c:	801047b7          	lui	a5,0x80104
801034a0:	c0078593          	addi	a1,a5,-1024 # 80103c00 <__data_load+0xfffffef0>
801034a4:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801034a8:	e48fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:391


		/*poll for file size*/
		UART_send(&g_uart, (const uint8_t * )"z",1);
801034ac:	00100613          	li	a2,1
801034b0:	801047b7          	lui	a5,0x80104
801034b4:	c1878593          	addi	a1,a5,-1000 # 80103c18 <__data_load+0xffffff08>
801034b8:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801034bc:	e34fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:392
		i=0;
801034c0:	fe042023          	sw	zero,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:393
		while(i<9)
801034c4:	0440006f          	j	80103508 <load_spi_flash_with_images_thruough_uart_intf+0x34c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:395
		{
			while(!(UART_get_rx ( &g_uart, rx_buff, 1 )))
801034c8:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:395 (discriminator 1)
801034cc:	fd440793          	addi	a5,s0,-44
801034d0:	00100613          	li	a2,1
801034d4:	00078593          	mv	a1,a5
801034d8:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801034dc:	eecfe0ef          	jal	ra,80101bc8 <UART_get_rx>
801034e0:	00050793          	mv	a5,a0
801034e4:	fe0784e3          	beqz	a5,801034cc <load_spi_flash_with_images_thruough_uart_intf+0x310>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:398
				;

			num[i] = rx_buff[0];
801034e8:	fe042783          	lw	a5,-32(s0)
801034ec:	fd444703          	lbu	a4,-44(s0)
801034f0:	ff040693          	addi	a3,s0,-16
801034f4:	00f687b3          	add	a5,a3,a5
801034f8:	fce78c23          	sb	a4,-40(a5)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:399
			i++;
801034fc:	fe042783          	lw	a5,-32(s0)
80103500:	00178793          	addi	a5,a5,1
80103504:	fef42023          	sw	a5,-32(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:393
		while(i<9)
80103508:	fe042703          	lw	a4,-32(s0)
8010350c:	00800793          	li	a5,8
80103510:	fae7fce3          	bgeu	a5,a4,801034c8 <load_spi_flash_with_images_thruough_uart_intf+0x30c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:401
		}
		g_file_size = number_size(num);//;atoi((const char*)rx_buff);
80103514:	fc840793          	addi	a5,s0,-56
80103518:	00078513          	mv	a0,a5
8010351c:	b85ff0ef          	jal	ra,801030a0 <number_size>
80103520:	00050713          	mv	a4,a0
80103524:	82e1a623          	sw	a4,-2004(gp) # 7000002c <g_file_size>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:403

		UART_send(&g_uart, (const uint8_t * )"a",1);
80103528:	00100613          	li	a2,1
8010352c:	801047b7          	lui	a5,0x80104
80103530:	c0078593          	addi	a1,a5,-1024 # 80103c00 <__data_load+0xfffffef0>
80103534:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103538:	db8fe0ef          	jal	ra,80101af0 <UART_send>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:407

		do
		{
			length = read_page_from_host_through_uart(g_write_buffer, BUFFER_SIZE);
8010353c:	000015b7          	lui	a1,0x1
80103540:	700017b7          	lui	a5,0x70001
80103544:	0a078513          	addi	a0,a5,160 # 700010a0 <g_write_buffer>
80103548:	fa0ff0ef          	jal	ra,80102ce8 <read_page_from_host_through_uart>
8010354c:	00050793          	mv	a5,a0
80103550:	fcf42e23          	sw	a5,-36(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:408
			if(length>0)
80103554:	fdc42783          	lw	a5,-36(s0)
80103558:	00078c63          	beqz	a5,80103570 <load_spi_flash_with_images_thruough_uart_intf+0x3b4>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:410
			{
				copy_to_flash(g_write_buffer,length);
8010355c:	fdc42783          	lw	a5,-36(s0)
80103560:	00078593          	mv	a1,a5
80103564:	700017b7          	lui	a5,0x70001
80103568:	0a078513          	addi	a0,a5,160 # 700010a0 <g_write_buffer>
8010356c:	bc1ff0ef          	jal	ra,8010312c <copy_to_flash>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:414
				//memcpy(ddr_add1,g_page_buffer,length);
				//ddr_add1 +=  length;
			}
			led_state = led_state ^ 1;
80103570:	fef44783          	lbu	a5,-17(s0)
80103574:	0017c793          	xori	a5,a5,1
80103578:	fef407a3          	sb	a5,-17(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:415
			GPIO_set_output( &g_gpio, GPIO_1,led_state);
8010357c:	fef44783          	lbu	a5,-17(s0)
80103580:	00078613          	mv	a2,a5
80103584:	00100593          	li	a1,1
80103588:	88c18513          	addi	a0,gp,-1908 # 7000008c <g_gpio>
8010358c:	c38ff0ef          	jal	ra,801029c4 <GPIO_set_output>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:416
		}while(length!=0);
80103590:	fdc42783          	lw	a5,-36(s0)
80103594:	fa0794e3          	bnez	a5,8010353c <load_spi_flash_with_images_thruough_uart_intf+0x380>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:419
		//ddr_add += 0x30000;

		no_of_files++;
80103598:	8241c783          	lbu	a5,-2012(gp) # 70000024 <no_of_files>
8010359c:	00178793          	addi	a5,a5,1
801035a0:	0ff7f713          	andi	a4,a5,255
801035a4:	82e18223          	sb	a4,-2012(gp) # 70000024 <no_of_files>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:354
	while(no_of_files<MAX_FILES)
801035a8:	8241c783          	lbu	a5,-2012(gp) # 70000024 <no_of_files>
801035ac:	d60784e3          	beqz	a5,80103314 <load_spi_flash_with_images_thruough_uart_intf+0x158>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:421
	}
	if(no_of_files==MAX_FILES)
801035b0:	8241c703          	lbu	a4,-2012(gp) # 70000024 <no_of_files>
801035b4:	00100793          	li	a5,1
801035b8:	00f71a63          	bne	a4,a5,801035cc <load_spi_flash_with_images_thruough_uart_intf+0x410>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:423
	{
		GPIO_set_output( &g_gpio, GPIO_1,1);
801035bc:	00100613          	li	a2,1
801035c0:	00100593          	li	a1,1
801035c4:	88c18513          	addi	a0,gp,-1908 # 7000008c <g_gpio>
801035c8:	bfcff0ef          	jal	ra,801029c4 <GPIO_set_output>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:426
	}
#endif
}
801035cc:	00000013          	nop
801035d0:	03c12083          	lw	ra,60(sp)
801035d4:	03812403          	lw	s0,56(sp)
801035d8:	04010113          	addi	sp,sp,64
801035dc:	00008067          	ret

801035e0 <read_program_from_flash_and_copy_to_ddr>:
read_program_from_flash_and_copy_to_ddr():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:430
#endif
#if 1
void read_program_from_flash_and_copy_to_ddr()
{
801035e0:	fe010113          	addi	sp,sp,-32
801035e4:	00112e23          	sw	ra,28(sp)
801035e8:	00812c23          	sw	s0,24(sp)
801035ec:	02010413          	addi	s0,sp,32
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:431
	volatile uint32_t i=0,address=flash_address[0],j;
801035f0:	fe042623          	sw	zero,-20(s0)
801035f4:	700007b7          	lui	a5,0x70000
801035f8:	00078793          	mv	a5,a5
801035fc:	0007a783          	lw	a5,0(a5) # 70000000 <RAM_START_ADDRESS>
80103600:	fef42423          	sw	a5,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:433
	uint8_t manufacturer_id,device_id;
	UART_polled_tx_string( &g_uart, ( uint8_t*)"\n\rApplication copying to DDR from SPI flash is in progress...\n\r");
80103604:	801047b7          	lui	a5,0x80104
80103608:	c1c78593          	addi	a1,a5,-996 # 80103c1c <__data_load+0xffffff0c>
8010360c:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103610:	f0cfe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:434
	FLASH_init();
80103614:	b8cfd0ef          	jal	ra,801009a0 <FLASH_init>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:435
	FLASH_global_unprotect();
80103618:	d18fd0ef          	jal	ra,80100b30 <FLASH_global_unprotect>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:436
	FLASH_read_device_id
8010361c:	fe240713          	addi	a4,s0,-30
80103620:	fe340793          	addi	a5,s0,-29
80103624:	00070593          	mv	a1,a4
80103628:	00078513          	mv	a0,a5
8010362c:	bb8fd0ef          	jal	ra,801009e4 <FLASH_read_device_id>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:442
	(
			&manufacturer_id,
			&device_id
	);
	//ddr memory initialization with 0x55
	for(i=0;i<DDR_APP_MAX_SIZE;i=i+4)
80103630:	fe042623          	sw	zero,-20(s0)
80103634:	02c0006f          	j	80103660 <read_program_from_flash_and_copy_to_ddr+0x80>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:444 (discriminator 3)
	{
		*(volatile uint32_t*)(DDR_BASE_ADDRESS+i) = 0x55555555;
80103638:	fec42703          	lw	a4,-20(s0)
8010363c:	802007b7          	lui	a5,0x80200
80103640:	00f707b3          	add	a5,a4,a5
80103644:	00078713          	mv	a4,a5
80103648:	555557b7          	lui	a5,0x55555
8010364c:	55578793          	addi	a5,a5,1365 # 55555555 <RAM_SIZE+0x55545555>
80103650:	00f72023          	sw	a5,0(a4) # 80000000 <__data_load+0xffefc2f0>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:442 (discriminator 3)
	for(i=0;i<DDR_APP_MAX_SIZE;i=i+4)
80103654:	fec42783          	lw	a5,-20(s0)
80103658:	00478793          	addi	a5,a5,4
8010365c:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:442 (discriminator 1)
80103660:	fec42703          	lw	a4,-20(s0)
80103664:	001007b7          	lui	a5,0x100
80103668:	fcf768e3          	bltu	a4,a5,80103638 <read_program_from_flash_and_copy_to_ddr+0x58>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:446
	}
	for(i=0;i<DDR_APP_MAX_SIZE;i=i+FLASH_SEGMENT_SIZE)
8010366c:	fe042623          	sw	zero,-20(s0)
80103670:	0800006f          	j	801036f0 <read_program_from_flash_and_copy_to_ddr+0x110>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:448
	{
		FLASH_read(address+i , &g_read_buf[0], FLASH_SEGMENT_SIZE);
80103674:	fe842703          	lw	a4,-24(s0)
80103678:	fec42783          	lw	a5,-20(s0)
8010367c:	00f70733          	add	a4,a4,a5
80103680:	10000613          	li	a2,256
80103684:	700007b7          	lui	a5,0x70000
80103688:	09c78593          	addi	a1,a5,156 # 7000009c <g_read_buf>
8010368c:	00070513          	mv	a0,a4
80103690:	be0fd0ef          	jal	ra,80100a70 <FLASH_read>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:450
		//memcpy((uint8_t*)(DDR_BASE_ADDRESS+i),&g_read_buf[0],FLASH_SEGMENT_SIZE);
		for(j=0;j<FLASH_SEGMENT_SIZE;j++)
80103694:	fe042223          	sw	zero,-28(s0)
80103698:	0400006f          	j	801036d8 <read_program_from_flash_and_copy_to_ddr+0xf8>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:452 (discriminator 3)
		{
			*(volatile uint8_t*)(DDR_BASE_ADDRESS+i+j) = g_read_buf[j];
8010369c:	fe442783          	lw	a5,-28(s0)
801036a0:	fec42683          	lw	a3,-20(s0)
801036a4:	fe442703          	lw	a4,-28(s0)
801036a8:	00e686b3          	add	a3,a3,a4
801036ac:	80200737          	lui	a4,0x80200
801036b0:	00e68733          	add	a4,a3,a4
801036b4:	00070693          	mv	a3,a4
801036b8:	70000737          	lui	a4,0x70000
801036bc:	09c70713          	addi	a4,a4,156 # 7000009c <g_read_buf>
801036c0:	00f707b3          	add	a5,a4,a5
801036c4:	0007c783          	lbu	a5,0(a5)
801036c8:	00f68023          	sb	a5,0(a3)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:450 (discriminator 3)
		for(j=0;j<FLASH_SEGMENT_SIZE;j++)
801036cc:	fe442783          	lw	a5,-28(s0)
801036d0:	00178793          	addi	a5,a5,1
801036d4:	fef42223          	sw	a5,-28(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:450 (discriminator 1)
801036d8:	fe442703          	lw	a4,-28(s0)
801036dc:	0ff00793          	li	a5,255
801036e0:	fae7fee3          	bgeu	a5,a4,8010369c <read_program_from_flash_and_copy_to_ddr+0xbc>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:446 (discriminator 2)
	for(i=0;i<DDR_APP_MAX_SIZE;i=i+FLASH_SEGMENT_SIZE)
801036e4:	fec42783          	lw	a5,-20(s0)
801036e8:	10078793          	addi	a5,a5,256
801036ec:	fef42623          	sw	a5,-20(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:446 (discriminator 1)
801036f0:	fec42703          	lw	a4,-20(s0)
801036f4:	001007b7          	lui	a5,0x100
801036f8:	f6f76ee3          	bltu	a4,a5,80103674 <read_program_from_flash_and_copy_to_ddr+0x94>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:455
		}
	}
	if(manufacturer_id == 0x20)
801036fc:	fe344703          	lbu	a4,-29(s0)
80103700:	02000793          	li	a5,32
80103704:	00f71a63          	bne	a4,a5,80103718 <read_program_from_flash_and_copy_to_ddr+0x138>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:457
	{
		UART_polled_tx_string( &g_uart, ( uint8_t*)"\n\rApplication Successfully copied to DDR from SPI flash\n\r");
80103708:	801047b7          	lui	a5,0x80104
8010370c:	c5c78593          	addi	a1,a5,-932 # 80103c5c <__data_load+0xffffff4c>
80103710:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103714:	e08fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:461
	}


}
80103718:	00000013          	nop
8010371c:	01c12083          	lw	ra,28(sp)
80103720:	01812403          	lw	s0,24(sp)
80103724:	02010113          	addi	sp,sp,32
80103728:	00008067          	ret

8010372c <main>:
main():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:465
#endif

int main()
{
8010372c:	ef010113          	addi	sp,sp,-272
80103730:	10112623          	sw	ra,268(sp)
80103734:	10812423          	sw	s0,264(sp)
80103738:	11010413          	addi	s0,sp,272
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:470
	uint8_t rx_data[MAX_RX_DATA_SIZE];
	size_t rx_size;
	char wait_in_bl;

	GPIO_init( &g_gpio, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS );
8010373c:	00200613          	li	a2,2
80103740:	750005b7          	lui	a1,0x75000
80103744:	88c18513          	addi	a0,gp,-1908 # 7000008c <g_gpio>
80103748:	908ff0ef          	jal	ra,80102850 <GPIO_init>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:480

    /**************************************************************************
      * Initialize CoreUARTapb with its base address, baud value, and line
      * configuration.
      *************************************************************************/
	UART_init( &g_uart, COREUARTAPB0_BASE_ADDR,\
8010374c:	00100693          	li	a3,1
80103750:	01400613          	li	a2,20
80103754:	710005b7          	lui	a1,0x71000
80103758:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010375c:	9bcfe0ef          	jal	ra,80101918 <UART_init>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:488


    /**************************************************************************
     * Display greeting message message.
     *************************************************************************/
	UART_polled_tx_string( &g_uart, g_greeting_msg);
80103760:	801047b7          	lui	a5,0x80104
80103764:	91078593          	addi	a1,a5,-1776 # 80103910 <__data_load+0xfffffc00>
80103768:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010376c:	db0fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:546
    {

         /**********************************************************************
         * Read data received by the UART.
         *********************************************************************/
    	UART_polled_tx_string( &g_uart, g_instructions_msg);
80103770:	801047b7          	lui	a5,0x80104
80103774:	ac878593          	addi	a1,a5,-1336 # 80103ac8 <__data_load+0xfffffdb8>
80103778:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
8010377c:	da0fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:547
    	while(!(UART_get_rx ( &g_uart, rx_data, 1 )))
80103780:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:547 (discriminator 1)
80103784:	ef040793          	addi	a5,s0,-272
80103788:	00100613          	li	a2,1
8010378c:	00078593          	mv	a1,a5
80103790:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103794:	c34fe0ef          	jal	ra,80101bc8 <UART_get_rx>
80103798:	00050793          	mv	a5,a0
8010379c:	fe0784e3          	beqz	a5,80103784 <main+0x58>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:556
         *********************************************************************/


        {
            //UART_send( &g_uart, rx_data, 1 );
    		delay1(1000);
801037a0:	3e800513          	li	a0,1000
801037a4:	d0cff0ef          	jal	ra,80102cb0 <delay1>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:557
            UART_polled_tx_string( &g_uart, (uint8_t*)"\n\r");
801037a8:	801047b7          	lui	a5,0x80104
801037ac:	c9878593          	addi	a1,a5,-872 # 80103c98 <__data_load+0xffffff88>
801037b0:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801037b4:	d68fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:558
            switch(rx_data[0])
801037b8:	ef044783          	lbu	a5,-272(s0)
801037bc:	03100713          	li	a4,49
801037c0:	04e78263          	beq	a5,a4,80103804 <main+0xd8>
801037c4:	03100713          	li	a4,49
801037c8:	00f74863          	blt	a4,a5,801037d8 <main+0xac>
801037cc:	03000713          	li	a4,48
801037d0:	00e78e63          	beq	a5,a4,801037ec <main+0xc0>
801037d4:	0840006f          	j	80103858 <main+0x12c>
801037d8:	03200713          	li	a4,50
801037dc:	02e78863          	beq	a5,a4,8010380c <main+0xe0>
801037e0:	03300713          	li	a4,51
801037e4:	04e78663          	beq	a5,a4,80103830 <main+0x104>
801037e8:	0700006f          	j	80103858 <main+0x12c>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:561
            {
                case '0':
                	UART_polled_tx_string( &g_uart, (uint8_t*)"******** Initiate SPI Programming ******\n\r");
801037ec:	801047b7          	lui	a5,0x80104
801037f0:	c9c78593          	addi	a1,a5,-868 # 80103c9c <__data_load+0xffffff8c>
801037f4:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
801037f8:	d24fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:562
                	load_spi_flash_with_images_thruough_uart_intf();
801037fc:	9c1ff0ef          	jal	ra,801031bc <load_spi_flash_with_images_thruough_uart_intf>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:563
                    break;
80103800:	06c0006f          	j	8010386c <main+0x140>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:565
                case '1': // transfer file to DDR
                	read_program_from_flash_and_copy_to_ddr();
80103804:	dddff0ef          	jal	ra,801035e0 <read_program_from_flash_and_copy_to_ddr>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:566
                    break;
80103808:	0640006f          	j	8010386c <main+0x140>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:568
                case '2':
                	UART_polled_tx_string( &g_uart, (uint8_t*)"Application Execution control will be transferred to DDR\n\r");
8010380c:	801047b7          	lui	a5,0x80104
80103810:	cc878593          	addi	a1,a5,-824 # 80103cc8 <__data_load+0xffffffb8>
80103814:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103818:	d04fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:569
                	Bootloader_JumpToApplication((uint32_t)0x80200000, (uint32_t)0x80200004);
8010381c:	802007b7          	lui	a5,0x80200
80103820:	00478593          	addi	a1,a5,4 # 80200004 <__data_load+0xfc2f4>
80103824:	80200537          	lui	a0,0x80200
80103828:	048000ef          	jal	ra,80103870 <Bootloader_JumpToApplication>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:570
                    break;
8010382c:	0400006f          	j	8010386c <main+0x140>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:572
                case '3':
                	read_program_from_flash_and_copy_to_ddr();
80103830:	db1ff0ef          	jal	ra,801035e0 <read_program_from_flash_and_copy_to_ddr>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:573
                	UART_polled_tx_string( &g_uart, (uint8_t*)"Application Execution control will be transferred to DDR\n\r");
80103834:	801047b7          	lui	a5,0x80104
80103838:	cc878593          	addi	a1,a5,-824 # 80103cc8 <__data_load+0xffffffb8>
8010383c:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103840:	cdcfe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:574
					Bootloader_JumpToApplication((uint32_t)0x80200000, (uint32_t)0x80200004);
80103844:	802007b7          	lui	a5,0x80200
80103848:	00478593          	addi	a1,a5,4 # 80200004 <__data_load+0xfc2f4>
8010384c:	80200537          	lui	a0,0x80200
80103850:	020000ef          	jal	ra,80103870 <Bootloader_JumpToApplication>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:575
					break;
80103854:	0180006f          	j	8010386c <main+0x140>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:577
                default:
                	UART_polled_tx_string( &g_uart, g_instructions_msg);
80103858:	801047b7          	lui	a5,0x80104
8010385c:	ac878593          	addi	a1,a5,-1336 # 80103ac8 <__data_load+0xfffffdb8>
80103860:	89418513          	addi	a0,gp,-1900 # 70000094 <g_uart>
80103864:	cb8fe0ef          	jal	ra,80101d1c <UART_polled_tx_string>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:578
                	 break;
80103868:	00000013          	nop
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:546
    	UART_polled_tx_string( &g_uart, g_instructions_msg);
8010386c:	f05ff06f          	j	80103770 <main+0x44>

80103870 <Bootloader_JumpToApplication>:
Bootloader_JumpToApplication():
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:642
* Call this function if you want to switch to another program
* de-init any loaded drivers before calling this function
*/

static void Bootloader_JumpToApplication(uint32_t stack_location, uint32_t reset_vector)
{
80103870:	fe010113          	addi	sp,sp,-32
80103874:	00112e23          	sw	ra,28(sp)
80103878:	00812c23          	sw	s0,24(sp)
8010387c:	02010413          	addi	s0,sp,32
80103880:	fea42623          	sw	a0,-20(s0)
80103884:	feb42423          	sw	a1,-24(s0)
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:645
               /* Restore PLIC to known state: */
               //__disable_irq(); org
				MRV_disable_interrupts();
80103888:	bf8ff0ef          	jal	ra,80102c80 <MRV_disable_interrupts>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:647
               // PLIC_init(); org
               MRV_disable_interrupts();
8010388c:	bf4ff0ef          	jal	ra,80102c80 <MRV_disable_interrupts>
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:650

               /* Disable all interrupts: */
               write_csr(mie, 0);
80103890:	30405073          	csrwi	mie,0
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:653

               /* Start executing from the top of DDR memory: */
               __asm volatile("lui ra,0x80200");
80103894:	802000b7          	lui	ra,0x80200
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:658

    /*
     * Flush the cache.
     */
               __asm volatile ("fence.i");
80103898:	0000100f          	fence.i
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:665
    /*
     * We need to explicitly execute a return instruction in case the compiler had
     * done some return address register manipulation in this function's veneer.
     */

               __asm volatile("ret");
8010389c:	00008067          	ret
C:\2023\Microchip_Projects\Design_updates\2023.2\SoftConsole_updated\miv-rv32im-bootloader\Debug/../main.c:668

               /*User application execution should now start and never return here.... */
}
801038a0:	00000013          	nop
801038a4:	01c12083          	lw	ra,28(sp)
801038a8:	01812403          	lw	s0,24(sp)
801038ac:	02010113          	addi	sp,sp,32
801038b0:	00008067          	ret

801038b4 <memset>:
memset():
801038b4:	00050313          	mv	t1,a0
801038b8:	00060a63          	beqz	a2,801038cc <memset+0x18>
801038bc:	00b30023          	sb	a1,0(t1)
801038c0:	fff60613          	addi	a2,a2,-1
801038c4:	00130313          	addi	t1,t1,1
801038c8:	fe061ae3          	bnez	a2,801038bc <memset+0x8>
801038cc:	00008067          	ret

801038d0 <local_irq_handler_table>:
801038d0:	801016e0 801016c4 801016fc 80101810     ................
801038e0:	801017c0 801017c0 801017c0 801017c0     ................
801038f0:	80101718 80101734 80101750 8010176c     ....4...P...l...
80103900:	80101788 801017a4 801017d8 801017f4     ................

80103910 <g_greeting_msg>:
80103910:	0a0d0a0d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ....============
80103920:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
80103930:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
80103940:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
80103950:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
80103960:	0d3d3d3d 2020200a 20202020 20202020     ===..           
80103970:	20202020 20202020 63694d20 65736f72              Microse
80103980:	4d20696d 20562d69 746f6f42 616f4c20     mi Mi-V Boot Loa
80103990:	20726564 302e3176 0a0d302e 3d3d3d3d     der v1.0.0..====
801039a0:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
801039b0:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
801039c0:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
801039d0:	3d3d3d3d 3d3d3d3d 3d3d3d3d 3d3d3d3d     ================
801039e0:	3d3d3d3d 3d3d3d3d 0d3d3d3d 6854200a     ===========.. Th
801039f0:	62207369 20746f6f 64616f6c 70207265     is boot loader p
80103a00:	69766f72 20736564 20656874 6c6c6f66     rovides the foll
80103a10:	6e69776f 65662067 72757461 0d3a7365     owing features:.
80103a20:	2020200a 4c202d20 2064616f 72702061     .    - Load a pr
80103a30:	6172676f 6e69206d 53206f74 46204950     ogram into SPI F
80103a40:	6873616c 6d656d20 2079726f 6e697375     lash memory usin
80103a50:	41552067 0d2e5452 2020200a 4c202d20     g UART...    - L
80103a60:	2064616f 72702061 6172676f 7266206d     oad a program fr
80103a70:	53206d6f 66204950 6873616c 746e6920     om SPI flash int
80103a80:	7865206f 6e726574 44206c61 6d205244     o external DDR m
80103a90:	726f6d65 0a0d2079 20202020 614c202d     emory ..    - La
80103aa0:	68636e75 65687420 616f6c20 20646564     unch the loaded 
80103ab0:	676f7270 206d6172 6d6f7266 52444420     program from DDR
80103ac0:	200a0d2e 00000000                       ... ....

80103ac8 <g_instructions_msg>:
80103ac8:	0a0d0a0d 2d2d2d2d 2d2d2d2d 2d2d2d2d     ....------------
80103ad8:	2d2d2d2d 2d2d2d2d 2d2d2d2d 2d2d2d2d     ----------------
80103ae8:	2d2d2d2d 2d2d2d2d 2d2d2d2d 2d2d2d2d     ----------------
80103af8:	2d2d2d2d 2d2d2d2d 2d2d2d2d 2d2d2d2d     ----------------
80103b08:	2d2d2d2d 2d2d2d2d 2d2d2d2d 2d2d2d2d     ----------------
80103b18:	0d2d2d2d 704f200a 6e6f6974 0d0a3a73     ---.. Options:..
80103b28:	70795420 20302065 70206f74 72676f72      Type 0 to progr
80103b38:	66206d61 6873616c 74697720 70612068     am flash with ap
80103b48:	63696c70 6f697461 6d69206e 20656761     plication image 
80103b58:	54200d0a 20657079 6f742031 706f6320     .. Type 1 to cop
80103b68:	72702079 6172676f 7266206d 66206d6f     y program from f
80103b78:	6873616c 206f7420 20524444 54200d0a     lash to DDR .. T
80103b88:	20657079 6f742032 61747320 70207472     ype 2 to start p
80103b98:	72676f72 6c206d61 6564616f 6e692064     rogram loaded in
80103ba8:	52444420 200d0a20 65707954 74203320      DDR .. Type 3 t
80103bb8:	6f63206f 70207970 72676f72 66206d61     o copy program f
80103bc8:	206d6f72 73616c66 6f742068 52444420     rom flash to DDR
80103bd8:	646e6120 75616c20 2068636e 20656874      and launch the 
80103be8:	676f7270 206d6172 6d6f7266 52444420     program from DDR
80103bf8:	000d0a20 00000062 00000061 0000006e      ...b...a...n...
80103c08:	00000064 00000068 0000006b 00000072     d...h...k...r...
80103c18:	0000007a 70410d0a 63696c70 6f697461     z.....Applicatio
80103c28:	6f63206e 6e697970 6f742067 52444420     n copying to DDR
80103c38:	6f726620 5053206d 6c662049 20687361      from SPI flash 
80103c48:	69207369 7270206e 6572676f 2e2e7373     is in progress..
80103c58:	000d0a2e 70410d0a 63696c70 6f697461     ......Applicatio
80103c68:	7553206e 73656363 6c756673 6320796c     n Successfully c
80103c78:	6569706f 6f742064 52444420 6f726620     opied to DDR fro
80103c88:	5053206d 6c662049 0a687361 0000000d     m SPI flash.....
80103c98:	00000d0a 2a2a2a2a 2a2a2a2a 696e4920     ....******** Ini
80103ca8:	74616974 50532065 72502049 6172676f     tiate SPI Progra
80103cb8:	6e696d6d 2a2a2067 2a2a2a2a 00000d0a     mming ******....
80103cc8:	6c707041 74616369 206e6f69 63657845     Application Exec
80103cd8:	6f697475 6f63206e 6f72746e 6977206c     ution control wi
80103ce8:	62206c6c 72742065 66736e61 65727265     ll be transferre
80103cf8:	6f742064 52444420 00000d0a 00000000     d to DDR........
	...
