   1              		.file	"core_gpio.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0_m2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              		.section	.text.GPIO_init,"ax",@progbits
   8              		.align	2
   9              		.globl	GPIO_init
  11              	GPIO_init:
  12 0000 130101FF 		addi	sp,sp,-16
  13 0004 23248100 		sw	s0,8(sp)
  14 0008 23229100 		sw	s1,4(sp)
  15 000c 23202101 		sw	s2,0(sp)
  16 0010 23261100 		sw	ra,12(sp)
  17 0014 13090500 		mv	s2,a0
  18 0018 2320B900 		sw	a1,0(s2)
  19 001c 13840500 		mv	s0,a1
  20 0020 2322C500 		sw	a2,4(a0)
  21 0024 93840508 		addi	s1,a1,128
  22              	.L2:
  23 0028 13050400 		mv	a0,s0
  24 002c 93050000 		li	a1,0
  25 0030 13044400 		addi	s0,s0,4
  26 0034 97000000 		call	HW_set_8bit_reg
  26      E7800000 
  27 003c E31694FE 		bne	s0,s1,.L2
  28 0040 83274900 		lw	a5,4(s2)
  29 0044 13071000 		li	a4,1
  30 0048 638CE702 		beq	a5,a4,.L3
  31 004c 63880708 		beq	a5,zero,.L4
  32 0050 13072000 		li	a4,2
  33 0054 6396E706 		bne	a5,a4,.L5
  34 0058 03250900 		lw	a0,0(s2)
  35 005c 03248100 		lw	s0,8(sp)
  36 0060 8320C100 		lw	ra,12(sp)
  37 0064 83244100 		lw	s1,4(sp)
  38 0068 03290100 		lw	s2,0(sp)
  39 006c 9305F0FF 		li	a1,-1
  40 0070 13050508 		addi	a0,a0,128
  41 0074 13010101 		addi	sp,sp,16
  42 0078 17030000 		tail	HW_set_32bit_reg
  42      67000300 
  43              	.L3:
  44 0080 03250900 		lw	a0,0(s2)
  45 0084 37040100 		li	s0,65536
  46 0088 9305F4FF 		addi	a1,s0,-1
  47 008c 13050508 		addi	a0,a0,128
  48 0090 97000000 		call	HW_set_16bit_reg
  48      E7800000 
  49 0098 03250900 		lw	a0,0(s2)
  50 009c 9305F4FF 		addi	a1,s0,-1
  51 00a0 03248100 		lw	s0,8(sp)
  52 00a4 8320C100 		lw	ra,12(sp)
  53 00a8 83244100 		lw	s1,4(sp)
  54 00ac 03290100 		lw	s2,0(sp)
  55 00b0 13054508 		addi	a0,a0,132
  56 00b4 13010101 		addi	sp,sp,16
  57 00b8 17030000 		tail	HW_set_16bit_reg
  57      67000300 
  58              	.L5:
  59              	 #APP
  60              	# 70 "../drivers/CoreGPIO/core_gpio.c" 1
   1              	/*******************************************************************************
   2              	 * (c) Copyright 2008-2023 Microchip FPGA Embedded Systems Solutions.
   3              	 * 
   4              	 * SPDX-License-Identifier: MIT
   5              	 *
   6              	 * @file core_gpio.c
   7              	 * @author Microchip FPGA Embedded Systems Solutions
   8              	 * @brief CoreGPIO bare metal driver implementation.
   9              	 *
  10              	 */
  11              	#include "coregpio_regs.h"
  12              	#include "core_gpio.h"
  13              	
  14              	/*-------------------------------------------------------------------------*//**
  15              	 *
  16              	 */
  17              	#define GPIO_INT_ENABLE_MASK        (uint32_t)0x00000008UL
  18              	#define OUTPUT_BUFFER_ENABLE_MASK   0x00000004UL
  19              	
  20              	
  21              	#define NB_OF_GPIO  32
  22              	
  23              	#define CLEAR_ALL_IRQ32     (uint32_t)0xFFFFFFFF
  24              	#define CLEAR_ALL_IRQ16     (uint16_t)0xFFFF
  25              	#define CLEAR_ALL_IRQ8      (uint8_t)0xFF
  26              	
  27              	/*-------------------------------------------------------------------------*//**
  28              	 * GPIO_init()
  29              	 * See "core_gpio.h" for details of how to use this function.
  30              	 */
  31              	void GPIO_init
  32              	(
  33              	    gpio_instance_t *   this_gpio,
  34              	    addr_t              base_addr,
  35              	    gpio_apb_width_t    bus_width
  36              	)
  37              	{
  38              	    uint8_t i = 0;
  39              	    addr_t cfg_reg_addr = base_addr;
  40              	    
  41              	    this_gpio->base_addr = base_addr;
  42              	    this_gpio->apb_bus_width = bus_width;
  43              	    
  44              	    /* Clear configuration. */
  45              	    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
  46              	    {
  47              	        HW_set_8bit_reg( cfg_reg_addr, 0 );
  48              	        cfg_reg_addr += 4;
  49              	    }
  50              	    /* Clear any pending interrupts */
  51              	    switch( this_gpio->apb_bus_width )
  52              	    {
  53              	        case GPIO_APB_32_BITS_BUS:
  54              	            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
  55              	            break;
  56              	            
  57              	        case GPIO_APB_16_BITS_BUS:
  58              	            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
  59              	            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
  60              	            break;
  61              	            
  62              	        case GPIO_APB_8_BITS_BUS:
  63              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
  64              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
  65              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
  66              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
  67              	            break;
  68              	            
  69              	        default:
  70 00c0 73001000 	            HAL_ASSERT(0);
  71              	            break;
  61              		ebreak
  62              	# 0 "" 2
  63              	 #NO_APP
  64 00c4 8320C100 		lw	ra,12(sp)
  65 00c8 03248100 		lw	s0,8(sp)
  66 00cc 83244100 		lw	s1,4(sp)
  67 00d0 03290100 		lw	s2,0(sp)
  68 00d4 13010101 		addi	sp,sp,16
  69 00d8 67800000 		jr	ra
  70              	.L4:
  71 00dc 03250900 		lw	a0,0(s2)
  72 00e0 9305F00F 		li	a1,255
  73 00e4 13050508 		addi	a0,a0,128
  74 00e8 97000000 		call	HW_set_8bit_reg
  74      E7800000 
  75 00f0 03250900 		lw	a0,0(s2)
  76 00f4 9305F00F 		li	a1,255
  77 00f8 13054508 		addi	a0,a0,132
  78 00fc 97000000 		call	HW_set_8bit_reg
  78      E7800000 
  79 0104 03250900 		lw	a0,0(s2)
  80 0108 9305F00F 		li	a1,255
  81 010c 13058508 		addi	a0,a0,136
  82 0110 97000000 		call	HW_set_8bit_reg
  82      E7800000 
  83 0118 03250900 		lw	a0,0(s2)
  84 011c 03248100 		lw	s0,8(sp)
  85 0120 8320C100 		lw	ra,12(sp)
  86 0124 83244100 		lw	s1,4(sp)
  87 0128 03290100 		lw	s2,0(sp)
  88 012c 9305F00F 		li	a1,255
  89 0130 1305C508 		addi	a0,a0,140
  90 0134 13010101 		addi	sp,sp,16
  91 0138 17030000 		tail	HW_set_8bit_reg
  91      67000300 
  93              		.section	.text.GPIO_config,"ax",@progbits
  94              		.align	2
  95              		.globl	GPIO_config
  97              	GPIO_config:
  98 0000 9307F001 		li	a5,31
  99 0004 63EEB704 		bgtu	a1,a5,.L16
 100 0008 83270500 		lw	a5,0(a0)
 101 000c 130101FF 		addi	sp,sp,-16
 102 0010 23248100 		sw	s0,8(sp)
 103 0014 13942500 		slli	s0,a1,2
 104 0018 3304F400 		add	s0,s0,a5
 105 001c 13050400 		mv	a0,s0
 106 0020 93050600 		mv	a1,a2
 107 0024 23229100 		sw	s1,4(sp)
 108 0028 23261100 		sw	ra,12(sp)
 109 002c 93040600 		mv	s1,a2
 110 0030 97000000 		call	HW_set_32bit_reg
 110      E7800000 
 111 0038 13050400 		mv	a0,s0
 112 003c 97000000 		call	HW_get_32bit_reg
 112      E7800000 
 113 0044 63049500 		beq	a0,s1,.L9
 114              	 #APP
 115              	# 101 "../drivers/CoreGPIO/core_gpio.c" 1
  72              	    }
  73              	}
  74              	
  75              	/*-------------------------------------------------------------------------*//**
  76              	 * GPIO_config
  77              	 * See "core_gpio.h" for details of how to use this function.
  78              	 */
  79              	void GPIO_config
  80              	(
  81              	    gpio_instance_t *   this_gpio,
  82              	    gpio_id_t           port_id,
  83              	    uint32_t            config
  84              	)
  85              	{
  86              	    HAL_ASSERT( port_id < NB_OF_GPIO );
  87              	    
  88              	    if ( port_id < NB_OF_GPIO )
  89              	    {
  90              	        uint32_t cfg_reg_addr = this_gpio->base_addr;
  91              	        cfg_reg_addr += (port_id * 4);
  92              	        HW_set_32bit_reg( cfg_reg_addr, config );
  93              	        
  94              	        /*
  95              	         * Verify that the configuration was correctly written. Failure to read
  96              	         * back the expected value may indicate that the GPIO port was configured
  97              	         * as part of the hardware flow and cannot be modified through software.
  98              	         * It may also indicate that the base address passed as parameter to
  99              	         * GPIO_init() was incorrect.
 100              	         */
 101 0048 73001000 	        HAL_ASSERT( HW_get_32bit_reg( cfg_reg_addr ) == config );
 102              	    }
 116              		ebreak
 117              	# 0 "" 2
 118              	 #NO_APP
 119              	.L9:
 120 004c 8320C100 		lw	ra,12(sp)
 121 0050 03248100 		lw	s0,8(sp)
 122 0054 83244100 		lw	s1,4(sp)
 123 0058 13010101 		addi	sp,sp,16
 124 005c 67800000 		jr	ra
 125              	.L16:
 126              	 #APP
 127              	# 86 "../drivers/CoreGPIO/core_gpio.c" 1
 128              		ebreak
 129              	# 0 "" 2
 130              	 #NO_APP
 131 0064 67800000 		ret
 133              		.section	.text.GPIO_get_inputs,"ax",@progbits
 134              		.align	2
 135              		.globl	GPIO_get_inputs
 137              	GPIO_get_inputs:
 138 0000 83274500 		lw	a5,4(a0)
 139 0004 130101FF 		addi	sp,sp,-16
 140 0008 23248100 		sw	s0,8(sp)
 141 000c 23261100 		sw	ra,12(sp)
 142 0010 23229100 		sw	s1,4(sp)
 143 0014 23202101 		sw	s2,0(sp)
 144 0018 13071000 		li	a4,1
 145 001c 13040500 		mv	s0,a0
 146 0020 638AE702 		beq	a5,a4,.L18
 147 0024 638A0708 		beq	a5,zero,.L19
 148 0028 13072000 		li	a4,2
 149 002c 6396E706 		bne	a5,a4,.L20
 150 0030 03250500 		lw	a0,0(a0)
 151 0034 03248100 		lw	s0,8(sp)
 152 0038 8320C100 		lw	ra,12(sp)
 153 003c 83244100 		lw	s1,4(sp)
 154 0040 03290100 		lw	s2,0(sp)
 155 0044 13050509 		addi	a0,a0,144
 156 0048 13010101 		addi	sp,sp,16
 157 004c 17030000 		tail	HW_get_32bit_reg
 157      67000300 
 158              	.L18:
 159 0054 03250500 		lw	a0,0(a0)
 160 0058 13050509 		addi	a0,a0,144
 161 005c 97000000 		call	HW_get_16bit_reg
 161      E7800000 
 162 0064 93040500 		mv	s1,a0
 163 0068 03250400 		lw	a0,0(s0)
 164 006c 13054509 		addi	a0,a0,148
 165 0070 97000000 		call	HW_get_16bit_reg
 165      E7800000 
 166 0078 8320C100 		lw	ra,12(sp)
 167 007c 03248100 		lw	s0,8(sp)
 168 0080 13150501 		slli	a0,a0,16
 169 0084 33659500 		or	a0,a0,s1
 170 0088 03290100 		lw	s2,0(sp)
 171 008c 83244100 		lw	s1,4(sp)
 172 0090 13010101 		addi	sp,sp,16
 173 0094 67800000 		jr	ra
 174              	.L20:
 175              	 #APP
 176              	# 178 "../drivers/CoreGPIO/core_gpio.c" 1
 103              	}
 104              	
 105              	/*-------------------------------------------------------------------------*//**
 106              	 * GPIO_set_outputs
 107              	 * See "core_gpio.h" for details of how to use this function.
 108              	 */
 109              	void GPIO_set_outputs
 110              	(
 111              	    gpio_instance_t *   this_gpio,
 112              	    uint32_t            value
 113              	)
 114              	{
 115              	    switch( this_gpio->apb_bus_width )
 116              	    {
 117              	        case GPIO_APB_32_BITS_BUS:
 118              	            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
 119              	            break;
 120              	            
 121              	        case GPIO_APB_16_BITS_BUS:
 122              	            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
 123              	            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
 124              	            break;
 125              	            
 126              	        case GPIO_APB_8_BITS_BUS:
 127              	            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
 128              	            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
 129              	            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
 130              	            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
 131              	            break;
 132              	            
 133              	        default:
 134              	            HAL_ASSERT(0);
 135              	            break;
 136              	    }
 137              	    
 138              	    /*
 139              	     * Verify that the output register was correctly written. Failure to read back
 140              	     * the expected value may indicate that some of the GPIOs may not exist due to
 141              	     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
 142              	     * It may also indicate that the base address or APB bus width passed as
 143              	     * parameter to the GPIO_init() function do not match the hardware design.
 144              	     */
 145              	    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
 146              	}
 147              	
 148              	/*-------------------------------------------------------------------------*//**
 149              	 * GPIO_get_inputs
 150              	 * See "core_gpio.h" for details of how to use this function.
 151              	 */
 152              	uint32_t GPIO_get_inputs
 153              	(
 154              	    gpio_instance_t *   this_gpio
 155              	)
 156              	{
 157              	    uint32_t gpio_in = 0;
 158              	    
 159              	    switch( this_gpio->apb_bus_width )
 160              	    {
 161              	        case GPIO_APB_32_BITS_BUS:
 162              	            gpio_in = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_IN );
 163              	            break;
 164              	            
 165              	        case GPIO_APB_16_BITS_BUS:
 166              	            gpio_in |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_IN0 );
 167              	            gpio_in |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_IN1 ) << 16);
 168              	            break;
 169              	            
 170              	        case GPIO_APB_8_BITS_BUS:
 171              	            gpio_in |= HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN0 );
 172              	            gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN1 ) << 8);
 173              	            gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN2 ) << 16);
 174              	            gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN3 ) << 24);
 175              	            break;
 176              	            
 177              	        default:
 178 0098 73001000 	            HAL_ASSERT(0);
 179              	            break;
 177              		ebreak
 178              	# 0 "" 2
 179              	 #NO_APP
 180 009c 8320C100 		lw	ra,12(sp)
 181 00a0 03248100 		lw	s0,8(sp)
 182 00a4 83244100 		lw	s1,4(sp)
 183 00a8 03290100 		lw	s2,0(sp)
 184 00ac 13050000 		li	a0,0
 185 00b0 13010101 		addi	sp,sp,16
 186 00b4 67800000 		jr	ra
 187              	.L19:
 188 00b8 03250500 		lw	a0,0(a0)
 189 00bc 13050509 		addi	a0,a0,144
 190 00c0 97000000 		call	HW_get_8bit_reg
 190      E7800000 
 191 00c8 13090500 		mv	s2,a0
 192 00cc 03250400 		lw	a0,0(s0)
 193 00d0 13054509 		addi	a0,a0,148
 194 00d4 97000000 		call	HW_get_8bit_reg
 194      E7800000 
 195 00dc 93040500 		mv	s1,a0
 196 00e0 03250400 		lw	a0,0(s0)
 197 00e4 93948400 		slli	s1,s1,8
 198 00e8 13058509 		addi	a0,a0,152
 199 00ec 97000000 		call	HW_get_8bit_reg
 199      E7800000 
 200 00f4 83270400 		lw	a5,0(s0)
 201 00f8 13150501 		slli	a0,a0,16
 202 00fc B3E4A400 		or	s1,s1,a0
 203 0100 1385C709 		addi	a0,a5,156
 204 0104 97000000 		call	HW_get_8bit_reg
 204      E7800000 
 205 010c 8320C100 		lw	ra,12(sp)
 206 0110 03248100 		lw	s0,8(sp)
 207 0114 B3E42401 		or	s1,s1,s2
 208 0118 13158501 		slli	a0,a0,24
 209 011c 33659500 		or	a0,a0,s1
 210 0120 03290100 		lw	s2,0(sp)
 211 0124 83244100 		lw	s1,4(sp)
 212 0128 13010101 		addi	sp,sp,16
 213 012c 67800000 		jr	ra
 215              		.section	.text.GPIO_get_outputs,"ax",@progbits
 216              		.align	2
 217              		.globl	GPIO_get_outputs
 219              	GPIO_get_outputs:
 220 0000 83274500 		lw	a5,4(a0)
 221 0004 130101FF 		addi	sp,sp,-16
 222 0008 23248100 		sw	s0,8(sp)
 223 000c 23261100 		sw	ra,12(sp)
 224 0010 23229100 		sw	s1,4(sp)
 225 0014 23202101 		sw	s2,0(sp)
 226 0018 13071000 		li	a4,1
 227 001c 13040500 		mv	s0,a0
 228 0020 638AE702 		beq	a5,a4,.L24
 229 0024 638A0708 		beq	a5,zero,.L25
 230 0028 13072000 		li	a4,2
 231 002c 6396E706 		bne	a5,a4,.L26
 232 0030 03250500 		lw	a0,0(a0)
 233 0034 03248100 		lw	s0,8(sp)
 234 0038 8320C100 		lw	ra,12(sp)
 235 003c 83244100 		lw	s1,4(sp)
 236 0040 03290100 		lw	s2,0(sp)
 237 0044 1305050A 		addi	a0,a0,160
 238 0048 13010101 		addi	sp,sp,16
 239 004c 17030000 		tail	HW_get_32bit_reg
 239      67000300 
 240              	.L24:
 241 0054 03250500 		lw	a0,0(a0)
 242 0058 1305050A 		addi	a0,a0,160
 243 005c 97000000 		call	HW_get_16bit_reg
 243      E7800000 
 244 0064 93040500 		mv	s1,a0
 245 0068 03250400 		lw	a0,0(s0)
 246 006c 1305450A 		addi	a0,a0,164
 247 0070 97000000 		call	HW_get_16bit_reg
 247      E7800000 
 248 0078 8320C100 		lw	ra,12(sp)
 249 007c 03248100 		lw	s0,8(sp)
 250 0080 13150501 		slli	a0,a0,16
 251 0084 33659500 		or	a0,a0,s1
 252 0088 03290100 		lw	s2,0(sp)
 253 008c 83244100 		lw	s1,4(sp)
 254 0090 13010101 		addi	sp,sp,16
 255 0094 67800000 		jr	ra
 256              	.L26:
 257              	 #APP
 258              	# 215 "../drivers/CoreGPIO/core_gpio.c" 1
 180              	    }
 181              	    
 182              	    return gpio_in;
 183              	}
 184              	
 185              	/*-------------------------------------------------------------------------*//**
 186              	 * GPIO_get_outputs
 187              	 * See "core_gpio.h" for details of how to use this function.
 188              	 */
 189              	uint32_t GPIO_get_outputs
 190              	(
 191              	    gpio_instance_t *   this_gpio
 192              	)
 193              	{
 194              	    uint32_t gpio_out = 0;
 195              	    
 196              	    switch( this_gpio->apb_bus_width )
 197              	    {
 198              	        case GPIO_APB_32_BITS_BUS:
 199              	            gpio_out = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
 200              	            break;
 201              	            
 202              	        case GPIO_APB_16_BITS_BUS:
 203              	            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
 204              	            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 16);
 205              	            break;
 206              	            
 207              	        case GPIO_APB_8_BITS_BUS:
 208              	            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
 209              	            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 8);
 210              	            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT2 ) << 16);
 211              	            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT3 ) << 24);
 212              	            break;
 213              	            
 214              	        default:
 215 0098 73001000 	            HAL_ASSERT(0);
 216              	            break;
 259              		ebreak
 260              	# 0 "" 2
 261              	 #NO_APP
 262 009c 8320C100 		lw	ra,12(sp)
 263 00a0 03248100 		lw	s0,8(sp)
 264 00a4 83244100 		lw	s1,4(sp)
 265 00a8 03290100 		lw	s2,0(sp)
 266 00ac 13050000 		li	a0,0
 267 00b0 13010101 		addi	sp,sp,16
 268 00b4 67800000 		jr	ra
 269              	.L25:
 270 00b8 03250500 		lw	a0,0(a0)
 271 00bc 1305050A 		addi	a0,a0,160
 272 00c0 97000000 		call	HW_get_16bit_reg
 272      E7800000 
 273 00c8 13090500 		mv	s2,a0
 274 00cc 03250400 		lw	a0,0(s0)
 275 00d0 1305450A 		addi	a0,a0,164
 276 00d4 97000000 		call	HW_get_16bit_reg
 276      E7800000 
 277 00dc 93040500 		mv	s1,a0
 278 00e0 03250400 		lw	a0,0(s0)
 279 00e4 93948400 		slli	s1,s1,8
 280 00e8 1305850A 		addi	a0,a0,168
 281 00ec 97000000 		call	HW_get_16bit_reg
 281      E7800000 
 282 00f4 83270400 		lw	a5,0(s0)
 283 00f8 13150501 		slli	a0,a0,16
 284 00fc B3E4A400 		or	s1,s1,a0
 285 0100 1385C70A 		addi	a0,a5,172
 286 0104 97000000 		call	HW_get_16bit_reg
 286      E7800000 
 287 010c 8320C100 		lw	ra,12(sp)
 288 0110 03248100 		lw	s0,8(sp)
 289 0114 B3E42401 		or	s1,s1,s2
 290 0118 13158501 		slli	a0,a0,24
 291 011c 33659500 		or	a0,a0,s1
 292 0120 03290100 		lw	s2,0(sp)
 293 0124 83244100 		lw	s1,4(sp)
 294 0128 13010101 		addi	sp,sp,16
 295 012c 67800000 		jr	ra
 297              		.section	.text.GPIO_set_outputs,"ax",@progbits
 298              		.align	2
 299              		.globl	GPIO_set_outputs
 301              	GPIO_set_outputs:
 302 0000 83274500 		lw	a5,4(a0)
 303 0004 130101FF 		addi	sp,sp,-16
 304 0008 23248100 		sw	s0,8(sp)
 305 000c 23229100 		sw	s1,4(sp)
 306 0010 23261100 		sw	ra,12(sp)
 307 0014 13071000 		li	a4,1
 308 0018 13040500 		mv	s0,a0
 309 001c 93840500 		mv	s1,a1
 310 0020 6384E704 		beq	a5,a4,.L30
 311 0024 638E0706 		beq	a5,zero,.L31
 312 0028 13072000 		li	a4,2
 313 002c 6396E706 		bne	a5,a4,.L32
 314 0030 03250500 		lw	a0,0(a0)
 315 0034 1305050A 		addi	a0,a0,160
 316 0038 97000000 		call	HW_set_32bit_reg
 316      E7800000 
 317              	.L33:
 318 0040 13050400 		mv	a0,s0
 319 0044 97000000 		call	GPIO_get_outputs
 319      E7800000 
 320 004c 63049500 		beq	a0,s1,.L29
 321              	 #APP
 322              	# 145 "../drivers/CoreGPIO/core_gpio.c" 1
 323              		ebreak
 324              	# 0 "" 2
 325              	 #NO_APP
 326              	.L29:
 327 0054 8320C100 		lw	ra,12(sp)
 328 0058 03248100 		lw	s0,8(sp)
 329 005c 83244100 		lw	s1,4(sp)
 330 0060 13010101 		addi	sp,sp,16
 331 0064 67800000 		jr	ra
 332              	.L30:
 333 0068 03250500 		lw	a0,0(a0)
 334 006c 93950501 		slli	a1,a1,16
 335 0070 93D50501 		srli	a1,a1,16
 336 0074 1305050A 		addi	a0,a0,160
 337 0078 97000000 		call	HW_set_16bit_reg
 337      E7800000 
 338 0080 03250400 		lw	a0,0(s0)
 339 0084 93D50401 		srli	a1,s1,16
 340 0088 1305450A 		addi	a0,a0,164
 341 008c 97000000 		call	HW_set_16bit_reg
 341      E7800000 
 342 0094 6FF0DFFA 		j	.L33
 343              	.L32:
 344              	 #APP
 345              	# 134 "../drivers/CoreGPIO/core_gpio.c" 1
 346              		ebreak
 347              	# 0 "" 2
 348              	 #NO_APP
 349 009c 6FF05FFA 		j	.L33
 350              	.L31:
 351 00a0 03250500 		lw	a0,0(a0)
 352 00a4 93F5F50F 		andi	a1,a1,0xff
 353 00a8 1305050A 		addi	a0,a0,160
 354 00ac 97000000 		call	HW_set_8bit_reg
 354      E7800000 
 355 00b4 03250400 		lw	a0,0(s0)
 356 00b8 93D58400 		srli	a1,s1,8
 357 00bc 93F5F50F 		andi	a1,a1,0xff
 358 00c0 1305450A 		addi	a0,a0,164
 359 00c4 97000000 		call	HW_set_8bit_reg
 359      E7800000 
 360 00cc 03250400 		lw	a0,0(s0)
 361 00d0 93D50401 		srli	a1,s1,16
 362 00d4 93F5F50F 		andi	a1,a1,0xff
 363 00d8 1305850A 		addi	a0,a0,168
 364 00dc 97000000 		call	HW_set_8bit_reg
 364      E7800000 
 365 00e4 03250400 		lw	a0,0(s0)
 366 00e8 93D58401 		srli	a1,s1,24
 367 00ec 1305C50A 		addi	a0,a0,172
 368 00f0 97000000 		call	HW_set_8bit_reg
 368      E7800000 
 369 00f8 6FF09FF4 		j	.L33
 371              		.section	.text.GPIO_set_output,"ax",@progbits
 372              		.align	2
 373              		.globl	GPIO_set_output
 375              	GPIO_set_output:
 376 0000 130101FE 		addi	sp,sp,-32
 377 0004 23282101 		sw	s2,16(sp)
 378 0008 23263101 		sw	s3,12(sp)
 379 000c 23244101 		sw	s4,8(sp)
 380 0010 232E1100 		sw	ra,28(sp)
 381 0014 232C8100 		sw	s0,24(sp)
 382 0018 232A9100 		sw	s1,20(sp)
 383 001c 9307F001 		li	a5,31
 384 0020 13890500 		mv	s2,a1
 385 0024 93090500 		mv	s3,a0
 386 0028 130A0600 		mv	s4,a2
 387 002c 63F4B700 		bleu	a1,a5,.L37
 388              	 #APP
 389              	# 233 "../drivers/CoreGPIO/core_gpio.c" 1
 217              	    }
 218              	    
 219              	    return gpio_out;
 220              	}
 221              	
 222              	/*-------------------------------------------------------------------------*//**
 223              	 * GPIO_set_output
 224              	 * See "core_gpio.h" for details of how to use this function.
 225              	 */
 226              	void GPIO_set_output
 227              	(
 228              	    gpio_instance_t *   this_gpio,
 229              	    gpio_id_t           port_id,
 230              	    uint8_t             value
 231              	)
 232              	{
 233 0030 73001000 	    HAL_ASSERT( port_id < NB_OF_GPIO );
 234              	    
 390              		ebreak
 391              	# 0 "" 2
 392              	 #NO_APP
 393              	.L37:
 394 0034 03A44900 		lw	s0,4(s3)
 395 0038 93041000 		li	s1,1
 396 003c 6300940E 		beq	s0,s1,.L38
 397 0040 630E0406 		beq	s0,zero,.L39
 398 0044 93072000 		li	a5,2
 399 0048 6318F404 		bne	s0,a5,.L40
 400 004c 03A50900 		lw	a0,0(s3)
 401 0050 B3942401 		sll	s1,s1,s2
 402 0054 1305050A 		addi	a0,a0,160
 403 0058 97000000 		call	HW_get_32bit_reg
 403      E7800000 
 404 0060 33E4A400 		or	s0,s1,a0
 405 0064 63160A00 		bne	s4,zero,.L42
 406 0068 93C4F4FF 		not	s1,s1
 407 006c 33F4A400 		and	s0,s1,a0
 408              	.L42:
 409 0070 03A50900 		lw	a0,0(s3)
 410 0074 93050400 		mv	a1,s0
 411 0078 1305050A 		addi	a0,a0,160
 412 007c 97000000 		call	HW_set_32bit_reg
 412      E7800000 
 413 0084 03A50900 		lw	a0,0(s3)
 414 0088 1305050A 		addi	a0,a0,160
 415 008c 97000000 		call	HW_get_32bit_reg
 415      E7800000 
 416 0094 63048500 		beq	a0,s0,.L36
 417              	.L40:
 418              	 #APP
 419              	# 319 "../drivers/CoreGPIO/core_gpio.c" 1
 235              	            
 236              	    switch( this_gpio->apb_bus_width )
 237              	    {
 238              	        case GPIO_APB_32_BITS_BUS:
 239              	            {
 240              	                uint32_t outputs_state;
 241              	                
 242              	                outputs_state = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
 243              	                if ( 0 == value )
 244              	                {
 245              	                    outputs_state &= ~(1 << port_id);
 246              	                }
 247              	                else
 248              	                {
 249              	                    outputs_state |= 1 << port_id;
 250              	                }
 251              	                HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
 252              	                
 253              	                /*
 254              	                 * Verify that the output register was correctly written. Failure to read back
 255              	                 * the expected value may indicate that some of the GPIOs may not exist due to
 256              	                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
 257              	                 * It may also indicate that the base address or APB bus width passed as
 258              	                 * parameter to the GPIO_init() function do not match the hardware design.
 259              	                 */
 260              	                HAL_ASSERT( HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT ) == outputs_state );
 261              	            }
 262              	            break;
 263              	            
 264              	        case GPIO_APB_16_BITS_BUS:
 265              	            {
 266              	                uint16_t outputs_state;
 267              	                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id
 268              	                
 269              	                outputs_state = HW_get_16bit_reg( gpio_out_reg_addr );
 270              	                if ( 0 == value )
 271              	                {
 272              	                    outputs_state &= ~(1 << (port_id & 0x0F));
 273              	                }
 274              	                else
 275              	                {
 276              	                    outputs_state |= 1 << (port_id & 0x0F);
 277              	                }
 278              	                HW_set_16bit_reg( gpio_out_reg_addr, outputs_state );
 279              	                
 280              	                /*
 281              	                 * Verify that the output register was correctly written. Failure to read back
 282              	                 * the expected value may indicate that some of the GPIOs may not exist due to
 283              	                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
 284              	                 * It may also indicate that the base address or APB bus width passed as
 285              	                 * parameter to the GPIO_init() function do not match the hardware design.
 286              	                 */
 287              	                HAL_ASSERT( HW_get_16bit_reg( gpio_out_reg_addr ) == outputs_state );
 288              	            }
 289              	            break;
 290              	            
 291              	        case GPIO_APB_8_BITS_BUS:
 292              	            {
 293              	                uint8_t outputs_state;
 294              	                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id
 295              	                
 296              	                outputs_state = HW_get_8bit_reg( gpio_out_reg_addr );
 297              	                if ( 0 == value )
 298              	                {
 299              	                    outputs_state &= ~(1 << (port_id & 0x07));
 300              	                }
 301              	                else
 302              	                {
 303              	                    outputs_state |= 1 << (port_id & 0x07);
 304              	                }
 305              	                HW_set_8bit_reg( gpio_out_reg_addr, outputs_state );
 306              	                
 307              	                /*
 308              	                 * Verify that the output register was correctly written. Failure to read back
 309              	                 * the expected value may indicate that some of the GPIOs may not exist due to
 310              	                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
 311              	                 * It may also indicate that the base address or APB bus width passed as
 312              	                 * parameter to the GPIO_init() function do not match the hardware design.
 313              	                 */
 314              	                HAL_ASSERT( HW_get_8bit_reg( gpio_out_reg_addr ) == outputs_state );
 315              	            }
 316              	            break;
 317              	            
 318              	        default:
 319 0098 73001000 	            HAL_ASSERT(0);
 320              	            break;
 420              		ebreak
 421              	# 0 "" 2
 422              	 #NO_APP
 423              	.L36:
 424 009c 8320C101 		lw	ra,28(sp)
 425 00a0 03248101 		lw	s0,24(sp)
 426 00a4 83244101 		lw	s1,20(sp)
 427 00a8 03290101 		lw	s2,16(sp)
 428 00ac 8329C100 		lw	s3,12(sp)
 429 00b0 032A8100 		lw	s4,8(sp)
 430 00b4 13010102 		addi	sp,sp,32
 431 00b8 67800000 		jr	ra
 432              	.L39:
 433 00bc 83A70900 		lw	a5,0(s3)
 434 00c0 93593900 		srli	s3,s2,3
 435 00c4 93992900 		slli	s3,s3,2
 436 00c8 9387070A 		addi	a5,a5,160
 437 00cc 13797900 		andi	s2,s2,7
 438 00d0 B389F900 		add	s3,s3,a5
 439 00d4 B3942401 		sll	s1,s1,s2
 440 00d8 13850900 		mv	a0,s3
 441 00dc 93948401 		slli	s1,s1,24
 442 00e0 97000000 		call	HW_get_8bit_reg
 442      E7800000 
 443 00e8 93D48441 		srai	s1,s1,24
 444 00ec 63040A0A 		beq	s4,zero,.L51
 445 00f0 B3E4A400 		or	s1,s1,a0
 446 00f4 93F4F40F 		andi	s1,s1,0xff
 447              	.L49:
 448 00f8 13850900 		mv	a0,s3
 449 00fc 93850400 		mv	a1,s1
 450 0100 97000000 		call	HW_set_8bit_reg
 450      E7800000 
 451 0108 13850900 		mv	a0,s3
 452 010c 97000000 		call	HW_get_8bit_reg
 452      E7800000 
 453 0114 E31295F8 		bne	a0,s1,.L40
 454 0118 6FF05FF8 		j	.L36
 455              	.L38:
 456 011c 83A70900 		lw	a5,0(s3)
 457 0120 93594900 		srli	s3,s2,4
 458 0124 93992900 		slli	s3,s3,2
 459 0128 9387070A 		addi	a5,a5,160
 460 012c 9374F900 		andi	s1,s2,15
 461 0130 B389F900 		add	s3,s3,a5
 462 0134 33149400 		sll	s0,s0,s1
 463 0138 13850900 		mv	a0,s3
 464 013c 13140401 		slli	s0,s0,16
 465 0140 97000000 		call	HW_get_16bit_reg
 465      E7800000 
 466 0148 13540441 		srai	s0,s0,16
 467 014c 630A0A02 		beq	s4,zero,.L52
 468 0150 3364A400 		or	s0,s0,a0
 469 0154 13140401 		slli	s0,s0,16
 470 0158 13540401 		srli	s0,s0,16
 471              	.L46:
 472 015c 13850900 		mv	a0,s3
 473 0160 93050400 		mv	a1,s0
 474 0164 97000000 		call	HW_set_16bit_reg
 474      E7800000 
 475 016c 13850900 		mv	a0,s3
 476 0170 97000000 		call	HW_get_16bit_reg
 476      E7800000 
 477 0178 E31085F2 		bne	a0,s0,.L40
 478 017c 6FF01FF2 		j	.L36
 479              	.L52:
 480 0180 1344F4FF 		not	s0,s0
 481 0184 3374A400 		and	s0,s0,a0
 482 0188 13140401 		slli	s0,s0,16
 483 018c 13540401 		srli	s0,s0,16
 484 0190 6FF0DFFC 		j	.L46
 485              	.L51:
 486 0194 93C4F4FF 		not	s1,s1
 487 0198 B3F4A400 		and	s1,s1,a0
 488 019c 93F4F40F 		andi	s1,s1,0xff
 489 01a0 6FF09FF5 		j	.L49
 491              		.section	.text.GPIO_drive_inout,"ax",@progbits
 492              		.align	2
 493              		.globl	GPIO_drive_inout
 495              	GPIO_drive_inout:
 496 0000 130101FF 		addi	sp,sp,-16
 497 0004 23248100 		sw	s0,8(sp)
 498 0008 23229100 		sw	s1,4(sp)
 499 000c 23261100 		sw	ra,12(sp)
 500 0010 9307F001 		li	a5,31
 501 0014 13840500 		mv	s0,a1
 502 0018 93040500 		mv	s1,a0
 503 001c 63F4B700 		bleu	a1,a5,.L54
 504              	 #APP
 505              	# 338 "../drivers/CoreGPIO/core_gpio.c" 1
 321              	    }
 322              	}
 323              	
 324              	/*-------------------------------------------------------------------------*//**
 325              	 * GPIO_drive_inout
 326              	 * See "core_gpio.h" for details of how to use this function.
 327              	 */
 328              	void GPIO_drive_inout
 329              	(
 330              	    gpio_instance_t *   this_gpio,
 331              	    gpio_id_t           port_id,
 332              	    gpio_inout_state_t  inout_state
 333              	)
 334              	{
 335              	    uint32_t config;
 336              	    uint32_t cfg_reg_addr = this_gpio->base_addr;
 337              	    
 338 0020 73001000 	    HAL_ASSERT( port_id < NB_OF_GPIO );
 339              	
 506              		ebreak
 507              	# 0 "" 2
 508              	 #NO_APP
 509              	.L54:
 510 0024 93071000 		li	a5,1
 511 0028 6304F602 		beq	a2,a5,.L55
 512 002c 6306060A 		beq	a2,zero,.L56
 513 0030 93072000 		li	a5,2
 514 0034 6306F606 		beq	a2,a5,.L57
 515              	 #APP
 516              	# 373 "../drivers/CoreGPIO/core_gpio.c" 1
 340              	    switch( inout_state )
 341              	    {
 342              	        case GPIO_DRIVE_HIGH:
 343              	            /* Set output high */
 344              	            GPIO_set_output( this_gpio, port_id, 1 );
 345              	            
 346              	            /* Enable output buffer */
 347              	            cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
 348              	            config = HW_get_8bit_reg( cfg_reg_addr );
 349              	            config |= OUTPUT_BUFFER_ENABLE_MASK;
 350              	            HW_set_8bit_reg( cfg_reg_addr, config );
 351              	            break;
 352              	            
 353              	        case GPIO_DRIVE_LOW:
 354              	            /* Set output low */
 355              	            GPIO_set_output( this_gpio, port_id, 0 );
 356              	            
 357              	            /* Enable output buffer */
 358              	            cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
 359              	            config = HW_get_8bit_reg( cfg_reg_addr );
 360              	            config |= OUTPUT_BUFFER_ENABLE_MASK;
 361              	            HW_set_8bit_reg( cfg_reg_addr, config );
 362              	            break;
 363              	            
 364              	        case GPIO_HIGH_Z:
 365              	            /* Disable output buffer */
 366              	            cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
 367              	            config = HW_get_8bit_reg( cfg_reg_addr );
 368              	            config &= ~OUTPUT_BUFFER_ENABLE_MASK;
 369              	            HW_set_8bit_reg( cfg_reg_addr, config );
 370              	            break;
 371              	            
 372              	        default:
 373 0038 73001000 	            HAL_ASSERT(0);
 374              	            break;
 517              		ebreak
 518              	# 0 "" 2
 519              	 #NO_APP
 520 003c 8320C100 		lw	ra,12(sp)
 521 0040 03248100 		lw	s0,8(sp)
 522 0044 83244100 		lw	s1,4(sp)
 523 0048 13010101 		addi	sp,sp,16
 524 004c 67800000 		jr	ra
 525              	.L55:
 526 0050 93050400 		mv	a1,s0
 527 0054 13061000 		li	a2,1
 528              	.L62:
 529 0058 13850400 		mv	a0,s1
 530 005c 97000000 		call	GPIO_set_output
 530      E7800000 
 531 0064 83A70400 		lw	a5,0(s1)
 532 0068 13142400 		slli	s0,s0,2
 533 006c 3304F400 		add	s0,s0,a5
 534 0070 13050400 		mv	a0,s0
 535 0074 97000000 		call	HW_get_8bit_reg
 535      E7800000 
 536 007c 93654500 		ori	a1,a0,4
 537 0080 13050400 		mv	a0,s0
 538 0084 03248100 		lw	s0,8(sp)
 539 0088 8320C100 		lw	ra,12(sp)
 540 008c 83244100 		lw	s1,4(sp)
 541 0090 93F5F50F 		andi	a1,a1,0xff
 542 0094 13010101 		addi	sp,sp,16
 543 0098 17030000 		tail	HW_set_8bit_reg
 543      67000300 
 544              	.L57:
 545 00a0 83A70400 		lw	a5,0(s1)
 546 00a4 13142400 		slli	s0,s0,2
 547 00a8 3304F400 		add	s0,s0,a5
 548 00ac 13050400 		mv	a0,s0
 549 00b0 97000000 		call	HW_get_8bit_reg
 549      E7800000 
 550 00b8 9375B5FF 		andi	a1,a0,-5
 551 00bc 13050400 		mv	a0,s0
 552 00c0 03248100 		lw	s0,8(sp)
 553 00c4 8320C100 		lw	ra,12(sp)
 554 00c8 83244100 		lw	s1,4(sp)
 555 00cc 13010101 		addi	sp,sp,16
 556 00d0 17030000 		tail	HW_set_8bit_reg
 556      67000300 
 557              	.L56:
 558 00d8 93050400 		mv	a1,s0
 559 00dc 13060000 		li	a2,0
 560 00e0 6FF09FF7 		j	.L62
 562              		.section	.text.GPIO_enable_irq,"ax",@progbits
 563              		.align	2
 564              		.globl	GPIO_enable_irq
 566              	GPIO_enable_irq:
 567 0000 9307F001 		li	a5,31
 568 0004 63E4B704 		bgtu	a1,a5,.L68
 569 0008 83270500 		lw	a5,0(a0)
 570 000c 130101FF 		addi	sp,sp,-16
 571 0010 23248100 		sw	s0,8(sp)
 572 0014 13942500 		slli	s0,a1,2
 573 0018 3304F400 		add	s0,s0,a5
 574 001c 13050400 		mv	a0,s0
 575 0020 23261100 		sw	ra,12(sp)
 576 0024 97000000 		call	HW_get_8bit_reg
 576      E7800000 
 577 002c 93658500 		ori	a1,a0,8
 578 0030 13050400 		mv	a0,s0
 579 0034 03248100 		lw	s0,8(sp)
 580 0038 8320C100 		lw	ra,12(sp)
 581 003c 93F5F50F 		andi	a1,a1,0xff
 582 0040 13010101 		addi	sp,sp,16
 583 0044 17030000 		tail	HW_set_8bit_reg
 583      67000300 
 584              	.L68:
 585              	 #APP
 586              	# 391 "../drivers/CoreGPIO/core_gpio.c" 1
 375              	    }
 376              	}
 377              	
 378              	/*-------------------------------------------------------------------------*//**
 379              	 * GPIO_enable_irq
 380              	 * See "core_gpio.h" for details of how to use this function.
 381              	 */
 382              	void GPIO_enable_irq
 383              	(
 384              	    gpio_instance_t *   this_gpio,
 385              	    gpio_id_t           port_id
 386              	)
 387              	{
 388              	    uint32_t cfg_value;
 389              	    uint32_t cfg_reg_addr = this_gpio->base_addr;
 390              	   
 391 004c 73001000 	    HAL_ASSERT( port_id < NB_OF_GPIO );
 392              	    
 587              		ebreak
 588              	# 0 "" 2
 589              	 #NO_APP
 590 0050 67800000 		ret
 592              		.section	.text.GPIO_disable_irq,"ax",@progbits
 593              		.align	2
 594              		.globl	GPIO_disable_irq
 596              	GPIO_disable_irq:
 597 0000 9307F001 		li	a5,31
 598 0004 63E2B704 		bgtu	a1,a5,.L74
 599 0008 83270500 		lw	a5,0(a0)
 600 000c 130101FF 		addi	sp,sp,-16
 601 0010 23248100 		sw	s0,8(sp)
 602 0014 13942500 		slli	s0,a1,2
 603 0018 3304F400 		add	s0,s0,a5
 604 001c 13050400 		mv	a0,s0
 605 0020 23261100 		sw	ra,12(sp)
 606 0024 97000000 		call	HW_get_8bit_reg
 606      E7800000 
 607 002c 937575FF 		andi	a1,a0,-9
 608 0030 13050400 		mv	a0,s0
 609 0034 03248100 		lw	s0,8(sp)
 610 0038 8320C100 		lw	ra,12(sp)
 611 003c 13010101 		addi	sp,sp,16
 612 0040 17030000 		tail	HW_set_8bit_reg
 612      67000300 
 613              	.L74:
 614              	 #APP
 615              	# 415 "../drivers/CoreGPIO/core_gpio.c" 1
 393              	    if ( port_id < NB_OF_GPIO )
 394              	    {
 395              	        cfg_reg_addr += (port_id * 4);
 396              	        cfg_value = HW_get_8bit_reg( cfg_reg_addr );
 397              	        cfg_value |= GPIO_INT_ENABLE_MASK;
 398              	        HW_set_8bit_reg( cfg_reg_addr, cfg_value );
 399              	    }
 400              	}
 401              	
 402              	/*-------------------------------------------------------------------------*//**
 403              	 * GPIO_disable_irq
 404              	 * See "core_gpio.h" for details of how to use this function.
 405              	 */
 406              	void GPIO_disable_irq
 407              	(
 408              	    gpio_instance_t *   this_gpio,
 409              	    gpio_id_t           port_id
 410              	)
 411              	{
 412              	    uint32_t cfg_value;
 413              	    uint32_t cfg_reg_addr = this_gpio->base_addr;
 414              	   
 415 0048 73001000 	    HAL_ASSERT( port_id < NB_OF_GPIO );
 416              	    
 616              		ebreak
 617              	# 0 "" 2
 618              	 #NO_APP
 619 004c 67800000 		ret
 621              		.section	.text.GPIO_clear_irq,"ax",@progbits
 622              		.align	2
 623              		.globl	GPIO_clear_irq
 625              	GPIO_clear_irq:
 626 0000 83274500 		lw	a5,4(a0)
 627 0004 130101FF 		addi	sp,sp,-16
 628 0008 23248100 		sw	s0,8(sp)
 629 000c 23229100 		sw	s1,4(sp)
 630 0010 13071000 		li	a4,1
 631 0014 23261100 		sw	ra,12(sp)
 632 0018 13040500 		mv	s0,a0
 633 001c B314B700 		sll	s1,a4,a1
 634 0020 638AE702 		beq	a5,a4,.L76
 635 0024 63800708 		beq	a5,zero,.L77
 636 0028 13072000 		li	a4,2
 637 002c 6390E706 		bne	a5,a4,.L78
 638 0030 03250500 		lw	a0,0(a0)
 639 0034 03248100 		lw	s0,8(sp)
 640 0038 8320C100 		lw	ra,12(sp)
 641 003c 93850400 		mv	a1,s1
 642 0040 83244100 		lw	s1,4(sp)
 643 0044 13050508 		addi	a0,a0,128
 644 0048 13010101 		addi	sp,sp,16
 645 004c 17030000 		tail	HW_set_32bit_reg
 645      67000300 
 646              	.L76:
 647 0054 03250500 		lw	a0,0(a0)
 648 0058 93850400 		mv	a1,s1
 649 005c 13050508 		addi	a0,a0,128
 650 0060 97000000 		call	HW_set_16bit_reg
 650      E7800000 
 651 0068 03250400 		lw	a0,0(s0)
 652 006c 03248100 		lw	s0,8(sp)
 653 0070 8320C100 		lw	ra,12(sp)
 654 0074 93D50401 		srli	a1,s1,16
 655 0078 83244100 		lw	s1,4(sp)
 656 007c 13054508 		addi	a0,a0,132
 657 0080 13010101 		addi	sp,sp,16
 658 0084 17030000 		tail	HW_set_16bit_reg
 658      67000300 
 659              	.L78:
 660              	 #APP
 661              	# 457 "../drivers/CoreGPIO/core_gpio.c" 1
 417              	    if ( port_id < NB_OF_GPIO )
 418              	    {
 419              	        cfg_reg_addr += (port_id * 4);
 420              	        cfg_value = HW_get_8bit_reg( cfg_reg_addr );
 421              	        cfg_value &= ~GPIO_INT_ENABLE_MASK;
 422              	        HW_set_8bit_reg( cfg_reg_addr, cfg_value );
 423              	    }
 424              	}
 425              	
 426              	/*-------------------------------------------------------------------------*//**
 427              	 * GPIO_clear_irq
 428              	 * See "core_gpio.h" for details of how to use this function.
 429              	 */
 430              	void GPIO_clear_irq
 431              	(
 432              	    gpio_instance_t *   this_gpio,
 433              	    gpio_id_t           port_id
 434              	)
 435              	{
 436              	    uint32_t irq_clr_value = ((uint32_t)1) << ((uint32_t)port_id);
 437              	    
 438              	    switch( this_gpio->apb_bus_width )
 439              	    {
 440              	        case GPIO_APB_32_BITS_BUS:
 441              	            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, irq_clr_value );
 442              	            break;
 443              	            
 444              	        case GPIO_APB_16_BITS_BUS:
 445              	            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
 446              	            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 16 );
 447              	            break;
 448              	            
 449              	        case GPIO_APB_8_BITS_BUS:
 450              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
 451              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 8 );
 452              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, irq_clr_value >> 16 );
 453              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, irq_clr_value >> 24 );
 454              	            break;
 455              	            
 456              	        default:
 457 008c 73001000 	            HAL_ASSERT(0);
 458              	            break;
 662              		ebreak
 663              	# 0 "" 2
 664              	 #NO_APP
 665 0090 8320C100 		lw	ra,12(sp)
 666 0094 03248100 		lw	s0,8(sp)
 667 0098 83244100 		lw	s1,4(sp)
 668 009c 13010101 		addi	sp,sp,16
 669 00a0 67800000 		jr	ra
 670              	.L77:
 671 00a4 03250500 		lw	a0,0(a0)
 672 00a8 93850400 		mv	a1,s1
 673 00ac 13050508 		addi	a0,a0,128
 674 00b0 97000000 		call	HW_set_8bit_reg
 674      E7800000 
 675 00b8 03250400 		lw	a0,0(s0)
 676 00bc 93D58400 		srli	a1,s1,8
 677 00c0 13054508 		addi	a0,a0,132
 678 00c4 97000000 		call	HW_set_8bit_reg
 678      E7800000 
 679 00cc 03250400 		lw	a0,0(s0)
 680 00d0 93D50401 		srli	a1,s1,16
 681 00d4 13058508 		addi	a0,a0,136
 682 00d8 97000000 		call	HW_set_8bit_reg
 682      E7800000 
 683 00e0 03250400 		lw	a0,0(s0)
 684 00e4 03248100 		lw	s0,8(sp)
 685 00e8 8320C100 		lw	ra,12(sp)
 686 00ec 93D58401 		srli	a1,s1,24
 687 00f0 83244100 		lw	s1,4(sp)
 688 00f4 1305C508 		addi	a0,a0,140
 689 00f8 13010101 		addi	sp,sp,16
 690 00fc 17030000 		tail	HW_set_8bit_reg
 690      67000300 
 692              		.section	.text.GPIO_get_irq_sources,"ax",@progbits
 693              		.align	2
 694              		.globl	GPIO_get_irq_sources
 696              	GPIO_get_irq_sources:
 697 0000 83274500 		lw	a5,4(a0)
 698 0004 130101FF 		addi	sp,sp,-16
 699 0008 23248100 		sw	s0,8(sp)
 700 000c 23261100 		sw	ra,12(sp)
 701 0010 23229100 		sw	s1,4(sp)
 702 0014 23202101 		sw	s2,0(sp)
 703 0018 13071000 		li	a4,1
 704 001c 13040500 		mv	s0,a0
 705 0020 638AE702 		beq	a5,a4,.L81
 706 0024 638A0708 		beq	a5,zero,.L82
 707 0028 13072000 		li	a4,2
 708 002c 6396E706 		bne	a5,a4,.L83
 709 0030 03250500 		lw	a0,0(a0)
 710 0034 03248100 		lw	s0,8(sp)
 711 0038 8320C100 		lw	ra,12(sp)
 712 003c 83244100 		lw	s1,4(sp)
 713 0040 03290100 		lw	s2,0(sp)
 714 0044 13050508 		addi	a0,a0,128
 715 0048 13010101 		addi	sp,sp,16
 716 004c 17030000 		tail	HW_get_32bit_reg
 716      67000300 
 717              	.L81:
 718 0054 03250500 		lw	a0,0(a0)
 719 0058 13050508 		addi	a0,a0,128
 720 005c 97000000 		call	HW_get_16bit_reg
 720      E7800000 
 721 0064 93040500 		mv	s1,a0
 722 0068 03250400 		lw	a0,0(s0)
 723 006c 13054508 		addi	a0,a0,132
 724 0070 97000000 		call	HW_get_16bit_reg
 724      E7800000 
 725 0078 8320C100 		lw	ra,12(sp)
 726 007c 03248100 		lw	s0,8(sp)
 727 0080 13150501 		slli	a0,a0,16
 728 0084 33659500 		or	a0,a0,s1
 729 0088 03290100 		lw	s2,0(sp)
 730 008c 83244100 		lw	s1,4(sp)
 731 0090 13010101 		addi	sp,sp,16
 732 0094 67800000 		jr	ra
 733              	.L83:
 734              	 #APP
 735              	# 492 "../drivers/CoreGPIO/core_gpio.c" 1
 459              	    }
 460              	}
 461              	
 462              	/*-------------------------------------------------------------------------*//**
 463              	 * GPIO_get_irq_sources
 464              	 * See "core_gpio.h" for details of how to use this function.
 465              	 */
 466              	uint32_t GPIO_get_irq_sources
 467              	(
 468              	    gpio_instance_t *   this_gpio
 469              	)
 470              	{
 471              	    uint32_t intr_src = 0;
 472              	
 473              	    switch( this_gpio->apb_bus_width )
 474              	    {
 475              	        case GPIO_APB_32_BITS_BUS:
 476              	            intr_src = HAL_get_32bit_reg( this_gpio->base_addr, IRQ );
 477              	            break;
 478              	
 479              	        case GPIO_APB_16_BITS_BUS:
 480              	            intr_src |= HAL_get_16bit_reg( this_gpio->base_addr, IRQ0 );
 481              	            intr_src |= (HAL_get_16bit_reg( this_gpio->base_addr, IRQ1 ) << 16);
 482              	            break;
 483              	
 484              	        case GPIO_APB_8_BITS_BUS:
 485              	            intr_src |= HAL_get_16bit_reg( this_gpio->base_addr, IRQ0 );
 486              	            intr_src |= (HAL_get_16bit_reg( this_gpio->base_addr, IRQ1 ) << 8);
 487              	            intr_src |= (HAL_get_16bit_reg( this_gpio->base_addr, IRQ2 ) << 16);
 488              	            intr_src |= (HAL_get_16bit_reg( this_gpio->base_addr, IRQ3 ) << 24);
 489              	            break;
 490              	
 491              	        default:
 492 0098 73001000 	            HAL_ASSERT(0);
 493              	            break;
 736              		ebreak
 737              	# 0 "" 2
 738              	 #NO_APP
 739 009c 8320C100 		lw	ra,12(sp)
 740 00a0 03248100 		lw	s0,8(sp)
 741 00a4 83244100 		lw	s1,4(sp)
 742 00a8 03290100 		lw	s2,0(sp)
 743 00ac 13050000 		li	a0,0
 744 00b0 13010101 		addi	sp,sp,16
 745 00b4 67800000 		jr	ra
 746              	.L82:
 747 00b8 03250500 		lw	a0,0(a0)
 748 00bc 13050508 		addi	a0,a0,128
 749 00c0 97000000 		call	HW_get_16bit_reg
 749      E7800000 
 750 00c8 13090500 		mv	s2,a0
 751 00cc 03250400 		lw	a0,0(s0)
 752 00d0 13054508 		addi	a0,a0,132
 753 00d4 97000000 		call	HW_get_16bit_reg
 753      E7800000 
 754 00dc 93040500 		mv	s1,a0
 755 00e0 03250400 		lw	a0,0(s0)
 756 00e4 93948400 		slli	s1,s1,8
 757 00e8 13058508 		addi	a0,a0,136
 758 00ec 97000000 		call	HW_get_16bit_reg
 758      E7800000 
 759 00f4 83270400 		lw	a5,0(s0)
 760 00f8 13150501 		slli	a0,a0,16
 761 00fc B3E4A400 		or	s1,s1,a0
 762 0100 1385C708 		addi	a0,a5,140
 763 0104 97000000 		call	HW_get_16bit_reg
 763      E7800000 
 764 010c 8320C100 		lw	ra,12(sp)
 765 0110 03248100 		lw	s0,8(sp)
 766 0114 B3E42401 		or	s1,s1,s2
 767 0118 13158501 		slli	a0,a0,24
 768 011c 33659500 		or	a0,a0,s1
 769 0120 03290100 		lw	s2,0(sp)
 770 0124 83244100 		lw	s1,4(sp)
 771 0128 13010101 		addi	sp,sp,16
 772 012c 67800000 		jr	ra
 774              		.section	.text.GPIO_clear_all_irq_sources,"ax",@progbits
 775              		.align	2
 776              		.globl	GPIO_clear_all_irq_sources
 778              	GPIO_clear_all_irq_sources:
 779 0000 83274500 		lw	a5,4(a0)
 780 0004 130101FF 		addi	sp,sp,-16
 781 0008 23248100 		sw	s0,8(sp)
 782 000c 23229100 		sw	s1,4(sp)
 783 0010 23261100 		sw	ra,12(sp)
 784 0014 13071000 		li	a4,1
 785 0018 13040500 		mv	s0,a0
 786 001c 93840500 		mv	s1,a1
 787 0020 6388E702 		beq	a5,a4,.L87
 788 0024 638C0706 		beq	a5,zero,.L88
 789 0028 13072000 		li	a4,2
 790 002c 639CE704 		bne	a5,a4,.L89
 791 0030 03250500 		lw	a0,0(a0)
 792 0034 03248100 		lw	s0,8(sp)
 793 0038 8320C100 		lw	ra,12(sp)
 794 003c 83244100 		lw	s1,4(sp)
 795 0040 13050508 		addi	a0,a0,128
 796 0044 13010101 		addi	sp,sp,16
 797 0048 17030000 		tail	HW_set_32bit_reg
 797      67000300 
 798              	.L87:
 799 0050 03250500 		lw	a0,0(a0)
 800 0054 13050508 		addi	a0,a0,128
 801 0058 97000000 		call	HW_set_16bit_reg
 801      E7800000 
 802 0060 03250400 		lw	a0,0(s0)
 803 0064 03248100 		lw	s0,8(sp)
 804 0068 8320C100 		lw	ra,12(sp)
 805 006c 93D50401 		srli	a1,s1,16
 806 0070 83244100 		lw	s1,4(sp)
 807 0074 13054508 		addi	a0,a0,132
 808 0078 13010101 		addi	sp,sp,16
 809 007c 17030000 		tail	HW_set_16bit_reg
 809      67000300 
 810              	.L89:
 811              	 #APP
 812              	# 530 "../drivers/CoreGPIO/core_gpio.c" 1
 494              	    }
 495              	
 496              	    return intr_src;
 497              	}
 498              	
 499              	/*-------------------------------------------------------------------------*//**
 500              	 * GPIO_clear_all_irq_sources
 501              	 * See "core_gpio.h" for details of how to use this function.
 502              	 */
 503              	void GPIO_clear_all_irq_sources
 504              	(
 505              	    gpio_instance_t *   this_gpio,
 506              	    uint32_t            bitmask
 507              	)
 508              	{
 509              	    uint32_t irq_clr_value = bitmask;
 510              	
 511              	    switch( this_gpio->apb_bus_width )
 512              	    {
 513              	        case GPIO_APB_32_BITS_BUS:
 514              	            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, irq_clr_value );
 515              	            break;
 516              	
 517              	        case GPIO_APB_16_BITS_BUS:
 518              	            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
 519              	            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 16 );
 520              	            break;
 521              	
 522              	        case GPIO_APB_8_BITS_BUS:
 523              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
 524              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 8 );
 525              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, irq_clr_value >> 16 );
 526              	            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, irq_clr_value >> 24 );
 527              	            break;
 528              	
 529              	        default:
 530 0084 73001000 	            HAL_ASSERT(0);
 531              	            break;
 813              		ebreak
 814              	# 0 "" 2
 815              	 #NO_APP
 816 0088 8320C100 		lw	ra,12(sp)
 817 008c 03248100 		lw	s0,8(sp)
 818 0090 83244100 		lw	s1,4(sp)
 819 0094 13010101 		addi	sp,sp,16
 820 0098 67800000 		jr	ra
 821              	.L88:
 822 009c 03250500 		lw	a0,0(a0)
 823 00a0 13050508 		addi	a0,a0,128
 824 00a4 97000000 		call	HW_set_8bit_reg
 824      E7800000 
 825 00ac 03250400 		lw	a0,0(s0)
 826 00b0 93D58400 		srli	a1,s1,8
 827 00b4 13054508 		addi	a0,a0,132
 828 00b8 97000000 		call	HW_set_8bit_reg
 828      E7800000 
 829 00c0 03250400 		lw	a0,0(s0)
 830 00c4 93D50401 		srli	a1,s1,16
 831 00c8 13058508 		addi	a0,a0,136
 832 00cc 97000000 		call	HW_set_8bit_reg
 832      E7800000 
 833 00d4 03250400 		lw	a0,0(s0)
 834 00d8 03248100 		lw	s0,8(sp)
 835 00dc 8320C100 		lw	ra,12(sp)
 836 00e0 93D58401 		srli	a1,s1,24
 837 00e4 83244100 		lw	s1,4(sp)
 838 00e8 1305C508 		addi	a0,a0,140
 839 00ec 13010101 		addi	sp,sp,16
 840 00f0 17030000 		tail	HW_set_8bit_reg
 840      67000300 
 842              		.ident	"GCC: (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 8.3.0"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 core_gpio.c
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:11     .text.GPIO_init:0000000000000000 GPIO_init
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:97     .text.GPIO_config:0000000000000000 GPIO_config
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:137    .text.GPIO_get_inputs:0000000000000000 GPIO_get_inputs
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:219    .text.GPIO_get_outputs:0000000000000000 GPIO_get_outputs
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:301    .text.GPIO_set_outputs:0000000000000000 GPIO_set_outputs
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:375    .text.GPIO_set_output:0000000000000000 GPIO_set_output
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:495    .text.GPIO_drive_inout:0000000000000000 GPIO_drive_inout
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:566    .text.GPIO_enable_irq:0000000000000000 GPIO_enable_irq
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:596    .text.GPIO_disable_irq:0000000000000000 GPIO_disable_irq
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:625    .text.GPIO_clear_irq:0000000000000000 GPIO_clear_irq
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:696    .text.GPIO_get_irq_sources:0000000000000000 GPIO_get_irq_sources
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:778    .text.GPIO_clear_all_irq_sources:0000000000000000 GPIO_clear_all_irq_sources
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:22     .text.GPIO_init:0000000000000028 .L2
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:43     .text.GPIO_init:0000000000000080 .L3
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:70     .text.GPIO_init:00000000000000dc .L4
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:58     .text.GPIO_init:00000000000000c0 .L5
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:125    .text.GPIO_config:0000000000000060 .L16
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:119    .text.GPIO_config:000000000000004c .L9
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:158    .text.GPIO_get_inputs:0000000000000054 .L18
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:187    .text.GPIO_get_inputs:00000000000000b8 .L19
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:174    .text.GPIO_get_inputs:0000000000000098 .L20
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:240    .text.GPIO_get_outputs:0000000000000054 .L24
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:269    .text.GPIO_get_outputs:00000000000000b8 .L25
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:256    .text.GPIO_get_outputs:0000000000000098 .L26
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:332    .text.GPIO_set_outputs:0000000000000068 .L30
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:350    .text.GPIO_set_outputs:00000000000000a0 .L31
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:343    .text.GPIO_set_outputs:0000000000000098 .L32
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:326    .text.GPIO_set_outputs:0000000000000054 .L29
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:317    .text.GPIO_set_outputs:0000000000000040 .L33
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:393    .text.GPIO_set_output:0000000000000034 .L37
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:455    .text.GPIO_set_output:000000000000011c .L38
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:432    .text.GPIO_set_output:00000000000000bc .L39
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:417    .text.GPIO_set_output:0000000000000098 .L40
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:408    .text.GPIO_set_output:0000000000000070 .L42
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:423    .text.GPIO_set_output:000000000000009c .L36
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:485    .text.GPIO_set_output:0000000000000194 .L51
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:479    .text.GPIO_set_output:0000000000000180 .L52
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:471    .text.GPIO_set_output:000000000000015c .L46
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:447    .text.GPIO_set_output:00000000000000f8 .L49
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:509    .text.GPIO_drive_inout:0000000000000024 .L54
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:525    .text.GPIO_drive_inout:0000000000000050 .L55
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:557    .text.GPIO_drive_inout:00000000000000d8 .L56
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:544    .text.GPIO_drive_inout:00000000000000a0 .L57
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:528    .text.GPIO_drive_inout:0000000000000058 .L62
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:584    .text.GPIO_enable_irq:000000000000004c .L68
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:613    .text.GPIO_disable_irq:0000000000000048 .L74
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:646    .text.GPIO_clear_irq:0000000000000054 .L76
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:670    .text.GPIO_clear_irq:00000000000000a4 .L77
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:659    .text.GPIO_clear_irq:000000000000008c .L78
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:717    .text.GPIO_get_irq_sources:0000000000000054 .L81
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:746    .text.GPIO_get_irq_sources:00000000000000b8 .L82
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:733    .text.GPIO_get_irq_sources:0000000000000098 .L83
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:798    .text.GPIO_clear_all_irq_sources:0000000000000050 .L87
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:821    .text.GPIO_clear_all_irq_sources:000000000000009c .L88
C:\Users\i68629\AppData\Local\Temp\cca2BgU2.s:810    .text.GPIO_clear_all_irq_sources:0000000000000084 .L89

UNDEFINED SYMBOLS
HW_set_8bit_reg
HW_set_32bit_reg
HW_set_16bit_reg
HW_get_32bit_reg
HW_get_16bit_reg
HW_get_8bit_reg
