main.o: ../main.c \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_hal.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_regs.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_plic.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_assert.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_subsys.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application/hw_platform.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\drivers\CoreUARTapb/core_uart_apb.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hal.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/cpu_types.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hw_reg_access.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hal_assert.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\drivers\CoreGPIO/core_gpio.h \
 ../hw_platform.h \
 C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hw_reg_access.h

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_hal.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_regs.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_plic.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_assert.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\miv_rv32_hal/miv_rv32_subsys.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application/hw_platform.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\drivers\CoreUARTapb/core_uart_apb.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hal.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/cpu_types.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hw_reg_access.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hal_assert.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\drivers\CoreGPIO/core_gpio.h:

../hw_platform.h:

C:\2024\Microchip_projects\Design_Updates_v2025.2\RTG4_AN4947_MIV_2025.1\rtg4_an4947_df\FW\miv-rv32im-ddr-application\hal/hw_reg_access.h:
