# Import source files
file copy -force "./src/softconsole/miv-rv32im-bootloader.hex" "./$Prjname/miv-rv32im-bootloader.hex"
import_files -hdl_source {./src/hdl/reset_synchronizer.v}

#build_design_hierarchy 
# Create, configure and generate core components
source ./src/components/COREAHBTOAPB3_C0.tcl 
source ./src/components/COREJTAGDEBUG_C0.tcl 
source ./src/components/MIV_ESS_C0.tcl 
source ./src/components/COREUPROMIF_APB_C0.tcl 
source ./src/components/CoreAHBLite_C0.tcl 
source ./src/components/CoreAPB3_C0.tcl 
source ./src/components/MIV_RV32_C0.tcl 
source ./src/components/RTG4FCCCECALIB_C0.tcl 
source ./src/components/RTG4FCCC_C0.tcl 
source ./src/components/RTG4FDDRC_INIT_C0.tcl 
source ./src/components/RTG4UPROM_C0.tcl 

file copy -force "./src/hdl/miv_rv32_subsys_pkg.v" "./$Prjname/component/Microsemi/MiV/MIV_RV32/$MIV_RV32ver/pkg/miv_rv32_subsys_pkg.v"

#Downgrade the DRC check
smartdesign -memory_map_drc_change_error_to_warning true \

# Generate SmartDesign Components

build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
