# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_0_IN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_1_IN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_SDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_RX} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CLK_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CLK} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_0_OUT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_DQS_TMATCH_1_OUT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FDDR_WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_SCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_SDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_SS} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_TX} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_ADDR} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DM_RDQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {FDDR_DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1}

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add CoreAHBLite_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBLite_C0} -instance_name {CoreAHBLite_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBLite_C0_0:REMAP_M0} -value {GND}



# Add COREAHBTOAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_C0} -instance_name {COREAHBTOAPB3_C0_0}



# Add CoreAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0}



# Add COREJTAGDEBUG_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREJTAGDEBUG_C0} -instance_name {COREJTAGDEBUG_C0_0}



# Add COREUPROMIF_APB_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREUPROMIF_APB_C0} -instance_name {COREUPROMIF_APB_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUPROMIF_APB_C0_0:RDATA}



# Add MIV_ESS_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_C0} -instance_name {MIV_ESS_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:SPI_IRQ}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_IN} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_INT}



# Add MIV_RV32_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_RESETN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:JTAG_TDO_DR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_IRQ} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:TIME_COUNT_OUT}



# Add RCOSC_50MHZ_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}



# Add reset_synchronizer_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}



# Add reset_synchronizer_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_1}



# Add RTG4FCCC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_C0} -instance_name {RTG4FCCC_C0_0}



# Add RTG4FCCCECALIB_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCCECALIB_C0} -instance_name {RTG4FCCCECALIB_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {RTG4FCCCECALIB_C0_0:READY_VDDPLL} -value {VCC}



# Add RTG4FDDRC_INIT_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FDDRC_INIT_C0} -instance_name {RTG4FDDRC_INIT_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RTG4FDDRC_INIT_C0_0:ECC_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RTG4FDDRC_INIT_C0_0:FIC_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RTG4FDDRC_INIT_C0_0:IO_CALIB_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RTG4FDDRC_INIT_C0_0:PLL_LOCKLOST_INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RTG4FDDRC_INIT_C0_0:PLL_LOCK_INT}



# Add RTG4UPROM_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4UPROM_C0} -instance_name {RTG4UPROM_C0_0}



# Add SYSRESET_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "INIT_DONE" "RTG4FDDRC_INIT_C0_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "AND2_1:A" "RTG4FCCCECALIB_C0_0:CCC_0_LOCK" "RTG4FDDRC_INIT_C0_0:CLK_BASE_PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "RTG4FCCCECALIB_C0_0:CCC_0_PLL_POWERDOWN_N" "RTG4FCCCECALIB_C0_0:PLL_RST_N" "SYSRESET_0:POWER_ON_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "reset_synchronizer_1:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_C0_0:HCLK" "COREUPROMIF_APB_C0_0:PCLK" "CoreAHBLite_C0_0:HCLK" "MIV_ESS_C0_0:PCLK" "MIV_RV32_C0_0:CLK" "RTG4FCCCECALIB_C0_0:CCC_0_GL0" "RTG4FDDRC_INIT_C0_0:CLK_BASE" "RTG4FDDRC_INIT_C0_0:INIT_CLK_50MHZ" "reset_synchronizer_0:clock" "reset_synchronizer_1:clock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_C0_0:HRESETN" "COREUPROMIF_APB_C0_0:PRESETN" "CoreAHBLite_C0_0:HRESETN" "MIV_ESS_C0_0:PRESETN" "MIV_RV32_C0_0:RESETN" "reset_synchronizer_0:reset_sync" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TCK_0" "MIV_RV32_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDI_0" "MIV_RV32_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDO_0" "MIV_RV32_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TMS_0" "MIV_RV32_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TRSTN_0" "MIV_RV32_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUPROMIF_APB_C0_0:UCLK" "RTG4FCCCECALIB_C0_0:CCC_0_GL1" "RTG4UPROM_C0_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUPROMIF_APB_C0_0:UPROM_BUSY" "RTG4UPROM_C0_0:BUSY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUPROMIF_APB_C0_0:UPROM_RDEN" "RTG4UPROM_C0_0:RDEN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVRST_N" "SYSRESET_0:DEVRST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CAS_N" "RTG4FDDRC_INIT_C0_0:FDDR_CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CKE" "RTG4FDDRC_INIT_C0_0:FDDR_CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CLK" "RTG4FDDRC_INIT_C0_0:FDDR_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CLK_N" "RTG4FDDRC_INIT_C0_0:FDDR_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_CS_N" "RTG4FDDRC_INIT_C0_0:FDDR_CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_0_IN" "RTG4FDDRC_INIT_C0_0:FDDR_DQS_TMATCH_0_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_0_OUT" "RTG4FDDRC_INIT_C0_0:FDDR_DQS_TMATCH_0_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_1_IN" "RTG4FDDRC_INIT_C0_0:FDDR_DQS_TMATCH_1_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_TMATCH_1_OUT" "RTG4FDDRC_INIT_C0_0:FDDR_DQS_TMATCH_1_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_ODT" "RTG4FDDRC_INIT_C0_0:FDDR_ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_RAS_N" "RTG4FDDRC_INIT_C0_0:FDDR_RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_RESET_N" "RTG4FDDRC_INIT_C0_0:FDDR_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_WE_N" "RTG4FDDRC_INIT_C0_0:FDDR_WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:SPI_SCK" "SPI_SCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:SPI_SDI" "SPI_SDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:SPI_SDO" "SPI_SDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:SPI_SS" "SPI_SS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_RX" "UART_RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_TX" "UART_TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCCECALIB_C0_0:CCC_0_RCOSC_50MHZ" "RTG4FCCC_C0_0:RCOSC_50MHZ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FCCCECALIB_C0_0:CLK_50MHZ" "RTG4FCCC_C0_0:GL0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FDDRC_INIT_C0_0:CORE_RESET_N" "RTG4FDDRC_INIT_C0_0:INIT_RESET_N" "reset_synchronizer_1:reset_sync" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUPROMIF_APB_C0_0:UPROM_ADDR" "RTG4UPROM_C0_0:ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUPROMIF_APB_C0_0:UPROM_DATAR" "RTG4UPROM_C0_0:DATAR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_ADDR" "RTG4FDDRC_INIT_C0_0:FDDR_ADDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_BA" "RTG4FDDRC_INIT_C0_0:FDDR_BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DM_RDQS" "RTG4FDDRC_INIT_C0_0:FDDR_DM_RDQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQ" "RTG4FDDRC_INIT_C0_0:FDDR_DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS" "RTG4FDDRC_INIT_C0_0:FDDR_DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FDDR_DQS_N" "RTG4FDDRC_INIT_C0_0:FDDR_DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "MIV_ESS_C0_0:GPIO_OUT" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_C0_0:AHBtarget" "CoreAHBLite_C0_0:AHBmslave1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_C0_0:APBinitiator" "CoreAPB3_C0_0:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUPROMIF_APB_C0_0:APB_bif" "CoreAPB3_C0_0:APBmslave1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBLite_C0_0:AHBmmaster0" "MIV_RV32_C0_0:AHBL_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBLite_C0_0:AHBmslave2" "RTG4FDDRC_INIT_C0_0:AHB0_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:APB_0_mINITIATOR" "MIV_RV32_C0_0:APB_INITIATOR" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
