------------------------------------------------------------------------
  
--© 2022 Microchip Technology Inc. and its subsidiaries
--  All rights reserved.
  
--  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
--  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
--  IN ADVANCE IN WRITING.
 
 -------------------------------------------------------------------------
--  Title : macc_cascaded.vhd
-- Created :  March 13, 2017
--  Description :Cascaded MACC with 
--  18x18-Bit Signed Multiplier with Registered l/Os
--  Hierarchy :top
                --Fabric_Logic
                    --macc_cascaded    <-- This module
  
 -------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity macc_cascaded is
  generic (
    WIDTH      : integer := 18);
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    DIN1       : in signed(WIDTH-1 downto 0);
    DIN2       : in signed(WIDTH-1 downto 0);
    DOUT       : out signed((WIDTH * 2)-1 downto 0));
end macc_cascaded;

ARCHITECTURE STRUCT OF macc_cascaded IS

type BUSARRAY is array (0 to 41) of signed (WIDTH-1 downto 0);
signal REG_ARRAY1 : BUSARRAY;
signal REG_ARRAY2 : BUSARRAY;

component sign18x18_mult
  generic (
    WIDTH      : integer := 18);
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    DIN1       : in signed(WIDTH-1 downto 0);
    DIN2       : in signed(WIDTH-1 downto 0);
    DOUT       : out signed((WIDTH * 2)-1 downto 0));
end component;

BEGIN

DOUT <= (REG_ARRAY1(41)& REG_ARRAY2(41));

F : for i in 0 to 41 generate
    begin
        F0 : if ( i = 0 ) generate  
             begin 
               U1 : sign18x18_mult
                 generic map( WIDTH => WIDTH)
                 port map   ( CLK   => CLK,
                              RST   => RST,
                              DIN1  => DIN1,
                              DIN2  => DIN2,
                              DOUT (17 downto 0)  => REG_ARRAY1(0),
                              DOUT (35 downto 18) => REG_ARRAY2(0));
             end generate F0;
        F1 : if ( i /= 0 ) generate 
             begin 
               U2 : sign18x18_mult
                 generic map( WIDTH => WIDTH)
                 port map   ( CLK   => CLK,
                              RST   => RST,
                              DIN1  => REG_ARRAY1(i-1),
                              DIN2  => REG_ARRAY2(i-1),
                              DOUT (17 downto 0)  => REG_ARRAY1(i),
                              DOUT (35 downto 18) => REG_ARRAY2(i)); 
             end generate F1;
    end generate F;     

END STRUCT;

