------------------------------------------------------------------------
  
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--  All rights reserved.
  
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--  IN ADVANCE IN WRITING.
 
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--  Title : shift_register.vhd
--  Created :  March 13, 2017
--  Description : 252-stage 16-bit shift registers
--  Hierarchy :top
                --Fabric_Logic
                    -- shift_register <-- This module
  
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_register is
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    DIN        : in std_logic_vector(15 downto 0);
    DOUT       : out std_logic_vector(15 downto 0));
end shift_register;

ARCHITECTURE STRUCT OF shift_register IS

type BUSARRAY is array (0 to 251) of std_logic_vector(15 downto 0);
signal REG_ARRAY : BUSARRAY;

component DFN1C0_16
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    DIN        : in std_logic_vector(15 downto 0);
    DOUT       : out std_logic_vector(15 downto 0));
end component;

BEGIN

DOUT <= REG_ARRAY(251);

F : for i in 0 to 251 generate
    begin
        F0 : if ( i = 0 ) generate  
             begin 
               U1 : DFN1C0_16
                    port map ( CLK  => CLK,
    						   RST  => RST,
                               DIN  => DIN,
                               DOUT => REG_ARRAY(0));
             end generate F0;
        F1 : if ( i /= 0 ) generate 
             begin 
               U2 : DFN1C0_16
                    port map ( CLK  => CLK,
    						   RST  => RST,
                               DIN  => REG_ARRAY(i-1),
                               DOUT => REG_ARRAY(i));  
             end generate F1;
    end generate F;         

END STRUCT;



