#Generate FPGA Array data
#run_tool -name {GENERATEPROGRAMMINGDATA} 
run_tool_wrapper "run_tool -name {GENERATEPROGRAMMINGDATA} 
"

# Configure and generate programming file data
## run_tool -name GENERATEPROGRAMMINGFILE
run_tool_wrapper "run_tool -name GENERATEPROGRAMMINGFILE
"
configure_tool \
         -name {GENERATEPROGRAMMINGFILE} \
         -params {program_envm:false} \
         -params {program_fabric:false} \
         -params {program_mode:selected_features} \
         -params {program_security:false} \
         -params {sanitize_envm:false} 

puts "Programmingfile generated successfully\n"

# Export STAPL file
export_bitstream_file \
         -file_name {top} \
         -export_dir ${PrjLocation}/designer/top/export \
         -format {STP DAT PPD} \
         -for_ihp 0 \
         -limit_SVF_file_size 0 \
         -limit_SVF_file_by_max_filesize_or_vectors {} \
         -svf_max_filesize {} \
         -svf_max_vectors {} \
         -force_rtg4_otp 0

puts "Exported bit stream successfully\n"

# Export Programming Job
# Programming job files can be imported in FlasPro Express standalone for programming the device
export_prog_job \
         -job_file_name {top} \
         -export_dir ${PrjLocation}/designer/top/export \
         -force_rtg4_otp 0 \
         -design_bitstream_format {STP} 
	
puts "Exported job file successfully\n"
puts "Full design flow passed execution\n"	
