------------------------------------------------------------------------
  
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--  All rights reserved.
  
--  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
--  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
--  IN ADVANCE IN WRITING.
 -------------------------------------------------------------------------
--  Title : CNT_UP.vhd
--  Created :  March 13, 2017
--  Description : N-bit Loadable Up Counter. Generic parameter for width is set to 8
-- (8-bit Loadable Up Counter)
--  Hierarchy :top
                --Fabric_Logic
                    --cnt_cascaded
                        -- CNT_UP   <-- This module
  
 -------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CNT_UP is
  generic (
    WIDTH      : integer := 8);
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    LD         : in std_logic;
    ENA        : in std_logic;
    DIN        : in std_logic_vector(WIDTH-1 downto 0);
    DOUT       : out std_logic_vector(WIDTH-1 downto 0));
end CNT_UP;

ARCHITECTURE STRUCT OF CNT_UP IS

signal CNTVAL : std_logic_vector(WIDTH-1 downto 0);

BEGIN

U : process (CLK, RST)
    begin
      if (RST = '0') then
          CNTVAL <= (others => '0');    
      elsif (CLK'event and CLK = '1') then
        if (LD = '0') then 
          CNTVAL <= DIN;
        elsif(ENA = '1') then
          CNTVAL <= CNTVAL + 1;
        end if;
      end if;            
end process;

DOUT <= CNTVAL;

END STRUCT;
