------------------------------------------------------------------------
  
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--  All rights reserved.
  
--  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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--  IN ADVANCE IN WRITING.
 
 
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--  Title : SIGN8x8_MULT.vhd
--  Created :  March 13, 2017
--  Description : 18x18-Bit Signed Multiplier with Registered l/Os
--  Hierarchy :top
                --Fabric_Logic
                    -- macc_cascaded
                        --SIGN8x8_MULT <-- This module
  
 -------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sign18x18_mult is
  generic (
    WIDTH      : integer := 18);
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    DIN1       : in signed(WIDTH-1 downto 0);
    DIN2       : in signed(WIDTH-1 downto 0);
    DOUT       : out signed((WIDTH * 2)-1 downto 0));
end sign18x18_mult;

ARCHITECTURE STRUCT OF sign18x18_mult IS

signal DIN1_REG : signed(WIDTH-1 downto 0);
signal DIN2_REG : signed(WIDTH-1 downto 0);
signal DOUT_REG : signed((WIDTH * 2)-1 downto 0);

BEGIN

U : process (CLK, RST)
    begin
      if (RST = '0') then
          DIN1_REG <= (others => '0');   
		  DIN2_REG <= (others => '0');  
          DOUT_REG <= (others => '0');   
      elsif (CLK'event and CLK = '1') then
          DIN1_REG <= DIN1;   
		  DIN2_REG <= DIN2;  
          DOUT_REG <= DIN1_REG * DIN2_REG ;
      end if;            
end process;

DOUT <= DOUT_REG;

END STRUCT;
