# Import source files
import_files -hdl_source {./src/hdl/cnt_cascaded.vhd}
import_files -hdl_source {./src/hdl/CNT_UP.vhd}
import_files -hdl_source {./src/hdl/DFN1C0_16.vhd}
import_files -hdl_source {./src/hdl/CNT_UP.vhd}
import_files -hdl_source {./src/hdl/Fabric_Logic.vhd}
import_files -hdl_source {./src/hdl/LSRAM1Kx18.vhd}
import_files -hdl_source {./src/hdl/lsram_cascaded.vhd}
import_files -hdl_source {./src/hdl/macc_cascaded.vhd}
import_files -hdl_source {./src/hdl/shift_register.vhd}
import_files -hdl_source {./src/hdl/SIGN8x8_MULT.vhd}
import_files -hdl_source {./src/hdl/uSRAM64x18.vhd}
import_files -hdl_source {./src/hdl/usram_cascaded.vhd}

build_design_hierarchy 
# Create, configure and generate core components
source ./src/components/RTG4FCCC_0.tcl
source ./src/components/RTG4FCCCECALIB_C0.tcl


# Generate SmartDesign Components

build_design_hierarchy 
source ./src/components/top.tcl



# Set top level module
build_design_hierarchy 
set_root -module {top::work}

save_project
puts "Design generated successfully\n"
