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--  All rights reserved.
  
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--  Title : DFN1C0_16.vhd
--  Created :  March 13, 2017
--  Description :16-bit register that can store input data (DIN) and output the stored data (DOUT) in a sequential manner 
--  Hierarchy :top
                --Fabric_Logic
                    --shift_register
                        -- DFN1C0_16   <-- This module
  
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LIBRARY IEEE;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DFN1C0_16 is
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    DIN        : in std_logic_vector(15 downto 0);
    DOUT       : out std_logic_vector(15 downto 0));
end DFN1C0_16;

ARCHITECTURE STRUCT OF DFN1C0_16 IS

type BUSARRAY is array (0 to 15) of std_logic;
signal REG_ARRAY : BUSARRAY;

component DFN1C0
  port(
    D          : in    STD_LOGIC;
    CLK        : in    STD_LOGIC;
    CLR        : in    STD_LOGIC;
    Q          : out   STD_LOGIC
  );
end component;

BEGIN

DOUT <= ( REG_ARRAY(15) & REG_ARRAY(14) & REG_ARRAY(13) & REG_ARRAY(12) &
          REG_ARRAY(11) & REG_ARRAY(10) & REG_ARRAY(9) & REG_ARRAY(8) &
          REG_ARRAY(7) & REG_ARRAY(6) & REG_ARRAY(5) & REG_ARRAY(4) &
          REG_ARRAY(3) & REG_ARRAY(2) & REG_ARRAY(1) & REG_ARRAY(0));


F : for i in 0 to 15 generate
    begin
      U1 : DFN1C0
           port map ( D   => DIN(i),
    		          CLK => CLK,
                      CLR => RST,
                      Q   => REG_ARRAY(i));
    end generate F;     

END STRUCT;


