------------------------------------------------------------------------
  
--© 2022 Microchip Technology Inc. and its subsidiaries
--  All rights reserved.
  
--  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
--  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
--  IN ADVANCE IN WRITING.
 
-------------------------------------------------------------------------
--  Title : cnt_cascaded.vhd
--  Created :  March 13, 2017
--  Description : N-stage Loadable Cascadable Up Counter.It is configured to be operated as 4464 stage 
-- - 8-bit Loadable Up Counter.
--  Hierarchy :top
                --Fabric_Logic
                    --cnt_cascaded <-- This module
  
 -------------------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt_cascaded is
  generic (
    WIDTH      : integer := 8);
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    LD         : in std_logic;
    ENA        : in std_logic;
    DIN        : in std_logic_vector(WIDTH-1 downto 0);
    DOUT       : out std_logic_vector(WIDTH-1 downto 0));
end cnt_cascaded;

ARCHITECTURE STRUCT OF cnt_cascaded IS

type BUSARRAY is array (0 to 4463) of std_logic_vector(WIDTH-1 downto 0);
signal REG_ARRAY : BUSARRAY;

component CNT_UP
  generic (
    WIDTH      : integer := 8);
  port (
    CLK        : in std_logic;
    RST        : in std_logic;
    LD         : in std_logic;
    ENA        : in std_logic;
    DIN        : in std_logic_vector(WIDTH-1 downto 0);
    DOUT       : out std_logic_vector(WIDTH-1 downto 0));
end component;

BEGIN

DOUT <= REG_ARRAY(4463);

F : for i in 0 to 4463 generate
    begin
        F0 : if ( i = 0 ) generate  
             begin 
               U1 : CNT_UP
                    generic map(WIDTH  => WIDTH)
                    port map ( CLK  => CLK,
    						   RST  => RST,
                               LD   => LD,
                               ENA  => ENA,
                               DIN  => DIN,
                               DOUT => REG_ARRAY(0));
             end generate F0;
        F1 : if ( i /= 0 ) generate 
             begin 
               U2 : CNT_UP
                    generic map(WIDTH  => WIDTH)
                    port map ( CLK  => CLK,
    						   RST  => RST,
                               LD   => LD,
                               ENA  => ENA,
                               DIN  => REG_ARRAY(i-1),
                               DOUT => REG_ARRAY(i));  
             end generate F1;
    end generate F;     

END STRUCT;

