------------------------------------------------------------------------
  
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--  All rights reserved.
  
--  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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--  IN ADVANCE IN WRITING.
 
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--  Title : usram_cascaded.vhd
--  Created :  March 13, 2017
--  Description : usram_cascaded
--  Hierarchy :top
                --Fabric_Logic
                    -- usram_cascaded <-- This module
  
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library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity usram_cascaded is 
   generic (width  : integer := 18;   
            depth  : integer := 64;   
            addr   : integer := 6);   
   port (Din       : in std_logic_vector (width-1 downto 0);
         CLK       : in std_logic;
         WE        : in std_logic;
         WAddr     : in std_logic_vector (addr-1 downto 0);
         RAddr     : in std_logic_vector (addr-1 downto 0);
         Dout      : out std_logic_vector (width-1 downto 0));
end usram_cascaded;

architecture behav of usram_cascaded is

type BUSARRAY is array (0 to 55) of std_logic_vector(width-1 downto 0);
signal REG_ARRAY : BUSARRAY;

component uSRAM64x18 
   generic (width  : integer := 18;   
            depth  : integer := 64;   
            addr   : integer := 6);   
   port (Din       : in std_logic_vector (width-1 downto 0);
         CLK       : in std_logic;
         WE        : in std_logic;
         WAddr     : in std_logic_vector (addr-1 downto 0);
         RAddr     : in std_logic_vector (addr-1 downto 0);
         Dout      : out std_logic_vector (width-1 downto 0));
end component;

begin

Dout <= REG_ARRAY(55);

F : for i in 0 to 55 generate
    begin
        F0 : if ( i = 0 ) generate  
             begin 
                U1 : uSRAM64x18 
                   generic map (width => width,   
                                depth => depth,   
                                addr  => addr)
                   port map    (Din   => Din,
                                CLK   => CLK,
                                WE    => WE,
                                WAddr => WAddr,
                                RAddr => RAddr,
                                Dout  => REG_ARRAY(0));
                   end generate F0;
        F1 : if ( i /= 0 ) generate 
             begin
                U2 : uSRAM64x18 
                   generic map (width => width,   
                                depth => depth,   
                                addr  => addr)
                   port map    (Din   => REG_ARRAY(i-1),
                                CLK   => CLK,
                                WE    => WE,
                                WAddr => WAddr,
                                RAddr => RAddr,
                                Dout  => REG_ARRAY(i)); 
             end generate F1;
    end generate F;     

end behav;
