------------------------------------------------------------------------
  
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--  All rights reserved.
  
--  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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--  Title : LSRAM1Kx18.vhd
--  Created :  March 13, 2017
--  Description :lsram
--  Hierarchy :top
                --Fabric_Logic
                    --lsram_cascaded   
                         --LSRAM1Kx18  <-- This module
  
 -------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity LSRAM1Kx18 is 
   generic (width  : integer := 18;   
            depth  : integer := 1024;   
            addr   : integer := 10);   
   port (Din       : in std_logic_vector (width-1 downto 0);
         CLK       : in std_logic;
         WE        : in std_logic;
         WAddr     : in std_logic_vector (addr-1 downto 0);
         RAddr     : in std_logic_vector (addr-1 downto 0);
         Dout      : out std_logic_vector (width-1 downto 0));
end LSRAM1Kx18;

architecture behav of LSRAM1Kx18 is
type MEM is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal ramTmp    : MEM;
signal RAddr_Reg : std_logic_vector(addr-1 downto 0);

attribute syn_ramstyle : string;
attribute syn_ramstyle of ramTmp : signal is "lsram";

begin

process (CLK)
  begin
    if (CLK'event and CLK='1') then
        RAddr_Reg <= RAddr;
      if (WE = '1') then
          ramTmp (conv_integer (WAddr)) <= Din;
      end if;
    end if;
end process;

Dout <= ramTmp(conv_integer(RAddr_Reg));

end behav;