
*******************************************
       Libero SoC and IP Core VERSIONS
*******************************************

This design was tested with the following: 
	Libero SoC Version: v12.6
	CCC Version: 2.0.201	
	COREUPROMIF_APB: 3.0.102
	RTG4UPROM : 2.1.100		

******************************************
     DESIGN FILE DIRECTORY STRUCTURE
******************************************

rtg4_ac454_df

    | 	
    |	   
    |---Libero_Project
    |      |
    |      |--Verilog
    |      |   |
    |      |   |--Libero_Project
    |      |
    |      |--VHDL
    |          |
    |          |--Libero_Project
    |
    |---Programming_Job
    |      |
    |      |---top.job
    |           
    |
    |---Source_Files
    |      |
    |      |--data.mem
    |      
    |---TCL_Scripts
    |     |---Verilog
    |     |---VHDL     
    |
    |---Readme.txt
    


Libero_Project
========
For reference, the final Libero SoC Verilog and VHDL project of this demo is given under this folder.
The designs are created for RTG4 Development Kit

Programming_Job
============================
This folder consists the programming file for RTG4 Development Kit 

Source_Files
============================
This folder contains the uPROM data storage memory client file

TCL_Scripts
============================
This folder consists the tcl scripts for this design.



