#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I52881 # Sat Dec 19 20:49:45 2020 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\CoreAPB3_C0\CoreAPB3_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4TPSRAM_C0\RTG4TPSRAM_C0_0\RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4TPSRAM_C0\RTG4TPSRAM_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\mux_blk.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RAM_APB_BLK\RAM_APB_BLK.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\ccc_comps.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CCCAPBIF.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Reset_Ctrl.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCC_C0\RTG4FCCC_C0_0\RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCC_C0\RTG4FCCC_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\COREUPROMIF_APB\3.0.102\rtl\vlog\core\coreupromif_apb.v" (library work) @W:CG1337 : coreupromif_apb.v(404) | Net UCLK_sync_pulse is not declared. @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\COREUPROMIF_APB_C0\COREUPROMIF_APB_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4UPROM\2.1.100\uprom_trans.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4UPROM_C0\RTG4UPROM_C0_0\UPROM_0_syn.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4UPROM_C0\RTG4UPROM_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4_uPROM\RTG4_uPROM.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : rtg4.v(129) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b011100 UPR_NIBBLE_POSN=4'b0110 FAMILY=32'b00000000000000000000000000011001 SYNC_RESET=32'b00000000000000000000000000000001 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z1 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z1 ....... @N:CG364 : CoreAPB3_C0.v(57) | Synthesizing module CoreAPB3_C0 in library work. Running optimization stage 1 on CoreAPB3_C0 ....... @N:CG364 : APB_master_wrp.v(21) | Synthesizing module APB_master_wrp in library work. DATA_WIDTH=32'b00000000000000000000000000100000 ADDR_WIDTH=32'b00000000000000000000000000010000 Idle=3'b000 Setup_0=3'b001 Access_0=3'b010 Access_1=3'b011 Generated name = APB_master_wrp_32s_16s_0_1_2_3 @N:CG179 : APB_master_wrp.v(107) | Removing redundant assignment. @N:CG179 : APB_master_wrp.v(108) | Removing redundant assignment. @N:CG179 : APB_master_wrp.v(117) | Removing redundant assignment. @N:CG179 : APB_master_wrp.v(118) | Removing redundant assignment. @N:CG179 : APB_master_wrp.v(212) | Removing redundant assignment. Running optimization stage 1 on APB_master_wrp_32s_16s_0_1_2_3 ....... @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWDATA[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(67) | Optimizing register bit PWRITE to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : APB_master_wrp.v(67) | Pruning unused register PWRITE. Make sure that there are no unused intermediate registers. @W:CL169 : APB_master_wrp.v(67) | Pruning unused register PWDATA[31:0]. Make sure that there are no unused intermediate registers. @N:CG364 : mux_blk.v(2) | Synthesizing module mux_blk in library work. Running optimization stage 1 on mux_blk ....... @N:CG364 : rtg4.v(712) | Synthesizing module RAM1K18_RT in library work. Running optimization stage 1 on RAM1K18_RT ....... @N:CG364 : rtg4.v(376) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : rtg4.v(380) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM.v(5) | Synthesizing module RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM in library work. Running optimization stage 1 on RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM ....... @N:CG364 : RTG4TPSRAM_C0.v(56) | Synthesizing module RTG4TPSRAM_C0 in library work. Running optimization stage 1 on RTG4TPSRAM_C0 ....... @N:CG364 : RAM_APB_BLK.v(9) | Synthesizing module RAM_APB_BLK in library work. Running optimization stage 1 on RAM_APB_BLK ....... @N:CG364 : rtg4.v(666) | Synthesizing module RCOSC_50MHZ in library work. Running optimization stage 1 on RCOSC_50MHZ ....... @N:CG364 : coreupromif_apb.v(20) | Synthesizing module COREUPROMIF_APB in library work. FAMILY=32'b00000000000000000000000000011001 NUM_OF_WORDS=14'b10100010100000 PCLK_ST_IDLE=4'b0000 PCLK_ST_WAIT_ADDR_SETUP=4'b0001 PCLK_ST_ADDR_SETUP=4'b0010 PCLK_ST_WAIT_DATA=4'b0011 PCLK_ST_DATA_REG=4'b0100 PCLK_ST_PRDATA_RETURN=4'b0101 UCLK_ST_IDLE=4'b0110 UCLK_WAIT=4'b0111 UCLK_WAIT_DATA1=4'b1000 UCLK_READ_DATA3=4'b1001 Generated name = COREUPROMIF_APB_Z2 Running optimization stage 1 on COREUPROMIF_APB_Z2 ....... @N:CG364 : COREUPROMIF_APB_C0.v(21) | Synthesizing module COREUPROMIF_APB_C0 in library work. Running optimization stage 1 on COREUPROMIF_APB_C0 ....... @N:CG364 : UPROM_0_syn.v(5) | Synthesizing module UPROM in library work. Running optimization stage 1 on UPROM ....... @N:CG364 : uprom_trans.v(1) | Synthesizing module RTG4UPROM_ADDR_TRANS in library work. Running optimization stage 1 on RTG4UPROM_ADDR_TRANS ....... @N:CG364 : uprom_trans.v(9) | Synthesizing module RTG4UPROM in library work. Running optimization stage 1 on RTG4UPROM ....... @N:CG364 : RTG4UPROM_C0.v(22) | Synthesizing module RTG4UPROM_C0 in library work. Running optimization stage 1 on RTG4UPROM_C0 ....... @N:CG364 : RTG4_uPROM.v(9) | Synthesizing module RTG4_uPROM in library work. Running optimization stage 1 on RTG4_uPROM ....... @N:CG364 : rtg4.v(353) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @W:CG1283 : RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v(18) | Type of parameter VCOFREQUENCY on the instance CCC_INST is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : ccc_comps.v(1) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v(5) | Synthesizing module RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC in library work. Running optimization stage 1 on RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC ....... @N:CG364 : RTG4FCCC_C0.v(145) | Synthesizing module RTG4FCCC_C0 in library work. Running optimization stage 1 on RTG4FCCC_C0 ....... @N:CG364 : rtg4.v(48) | Synthesizing module DFN1C0 in library work. Running optimization stage 1 on DFN1C0 ....... @N:CG364 : CorePLL_ELOCK_Ctrl_Fsm.v(29) | Synthesizing module ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm in library work. CCC_0_NEW_PLL_CR6=8'b00000000 CCC_0_NEW_FBDIV=8'b00000100 CCC_0_NEW_PLL_CR4=8'b00000101 CCC_0_ACTUAL_PLL_CR6=8'b00000000 CCC_0_ACTUAL_FBDIV=8'b00000010 CCC_0_ACTUAL_PLL_CR4=8'b00000101 CCC_1_NEW_PLL_CR6=8'b00000000 CCC_1_NEW_FBDIV=8'b00000000 CCC_1_NEW_PLL_CR4=8'b00000000 CCC_1_ACTUAL_PLL_CR6=8'b00000000 CCC_1_ACTUAL_FBDIV=8'b00000000 CCC_1_ACTUAL_PLL_CR4=8'b00000000 CCC_ENABLE=2'b01 CCC_0_ENABLE_AUTO_RESET=1'b1 CCC_1_ENABLE_AUTO_RESET=1'b0 FSM_WIDTH=32'b00000000000000000000000000001010 FSM_WIDTH_ODD=1'b0 IDLE=10'b0000000001 PWRON_DELAY=10'b0000000010 APB_REG_WRITE=10'b0000000100 APB_PREADY_WAIT=10'b0000001000 APB_WRITE_DONE=10'b0000010000 RESET_PLL=10'b0000100000 WAIT_150US=10'b0001000000 LOCK_WAIT=10'b0010000000 LOCK_COUNT=10'b0100000000 VCO_CONFIG_DONE=10'b1000000000 INIT_DELAY=32'b00000000000000000000000000011001 DELAY_1US=32'b00000000000000000000000000110010 DELAY_150US=32'b00000000000000000001110110000010 DELAY_CNT_WIDTH=32'b00000000000000000000000000001101 TOTAL_WRITE_REG=32'b00000000000000000000000000000011 APB_WRITE_REG_CNT_WIDTH=32'b00000000000000000000000000000010 CCC_CNT_WIDTH=32'b00000000000000000000000000000000 CCC_CNT_MAX=32'b00000000000000000000000000000000 FCC_PLL_CR6_REG_ADDR=6'b100000 FCC_FBDIV_CR_REG_ADDR=6'b000100 FCC_PLL_CR4_REG_ADDR=6'b011101 Generated name = ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3 Running optimization stage 1 on ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3 ....... @W:CL169 : CorePLL_ELOCK_Ctrl_Fsm.v(338) | Pruning unused register CCC_0_CONFIG_DONE. Make sure that there are no unused intermediate registers. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(397) | Optimizing register bit genblk1.CCC_0_RECALIB_EN to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(699) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PADDR[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(699) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PADDR[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(715) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(715) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(715) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(715) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CorePLL_ELOCK_Ctrl_Fsm.v(715) | Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : CorePLL_ELOCK_Ctrl_Fsm.v(715) | Pruning register bits 7 to 3 of genblk3.PLL_ELOCK_APB_M_PWDATA[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CorePLL_ELOCK_Ctrl_Fsm.v(699) | Pruning register bit 8 of genblk3.PLL_ELOCK_APB_M_PADDR[8:2]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CorePLL_ELOCK_Ctrl_Fsm.v(699) | Pruning register bit 3 of genblk3.PLL_ELOCK_APB_M_PADDR[8:2]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL169 : CorePLL_ELOCK_Ctrl_Fsm.v(397) | Pruning unused register genblk1.CCC_0_RECALIB_EN. Make sure that there are no unused intermediate registers. @N:CG364 : CorePLL_ELOCK_Reset_Ctrl.v(22) | Synthesizing module ACT_UNIQUE_CorePLL_ELOCK_Reset_Ctrl in library work. CCC_ENABLE=2'b01 Generated name = ACT_UNIQUE_CorePLL_ELOCK_Reset_Ctrl_1 Running optimization stage 1 on ACT_UNIQUE_CorePLL_ELOCK_Reset_Ctrl_1 ....... @N:CG364 : CorePLL_ELOCK.v(31) | Synthesizing module ACT_UNIQUE_COREPLL_ELOCK in library work. CCC_0_NEW_PLL_CR6=8'b00000000 CCC_0_NEW_FBDIV=8'b00000100 CCC_0_NEW_PLL_CR4=8'b00000101 CCC_0_ACTUAL_PLL_CR6=8'b00000000 CCC_0_ACTUAL_FBDIV=8'b00000010 CCC_0_ACTUAL_PLL_CR4=8'b00000101 CCC_0_ENABLE=1'b1 CCC_1_NEW_PLL_CR6=8'b00000000 CCC_1_NEW_FBDIV=8'b00000000 CCC_1_NEW_PLL_CR4=8'b00000000 CCC_1_ACTUAL_PLL_CR6=8'b00000000 CCC_1_ACTUAL_FBDIV=8'b00000000 CCC_1_ACTUAL_PLL_CR4=8'b00000000 CCC_1_ENABLE=1'b0 CCC_0_ENABLE_AUTO_RESET=1'b1 CCC_1_ENABLE_AUTO_RESET=1'b0 CCC_ENABLE=2'b01 Generated name = ACT_UNIQUE_COREPLL_ELOCK_Z4 Running optimization stage 1 on ACT_UNIQUE_COREPLL_ELOCK_Z4 ....... @N:CG364 : ccc_comps.v(312) | Synthesizing module BUFD_DELAY in library work. Running optimization stage 1 on BUFD_DELAY ....... @N:CG364 : ccc_comps.v(216) | Synthesizing module CCCAPB in library work. Running optimization stage 1 on CCCAPB ....... @N:CG364 : rtg4.v(141) | Synthesizing module OR2 in library work. Running optimization stage 1 on OR2 ....... @N:CG364 : rtg4.v(231) | Synthesizing module INV in library work. Running optimization stage 1 on INV ....... @N:CG364 : CCCAPBIF.v(5) | Synthesizing module RTG4CCCAPB_IF_C0_RTG4CCCAPB_IF_C0_0_RTG4CCCAPB_IF in library work. Running optimization stage 1 on RTG4CCCAPB_IF_C0_RTG4CCCAPB_IF_C0_0_RTG4CCCAPB_IF ....... @N:CG364 : ccc_comps.v(110) | Synthesizing module CCCDYN in library work. Running optimization stage 1 on CCCDYN ....... @N:CG364 : RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v(5) | Synthesizing module RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB in library work. @W:CG360 : RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v(22) | Removing wire \gnd_net_-1_-1, as there is no assignment to it. Running optimization stage 1 on RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB ....... @N:CG364 : RTG4FCCCECALIB_C0.v(274) | Synthesizing module RTG4FCCCECALIB_C0 in library work. Running optimization stage 1 on RTG4FCCCECALIB_C0 ....... @N:CG364 : rtg4.v(703) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on RTG4FCCCECALIB_C0 ....... Running optimization stage 2 on RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB ....... @W:CL156 : RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v(22) | *Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v(22) | *Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v(22) | *Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v(22) | *Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. Running optimization stage 2 on CCCDYN ....... Running optimization stage 2 on RTG4CCCAPB_IF_C0_RTG4CCCAPB_IF_C0_0_RTG4CCCAPB_IF ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on OR2 ....... Running optimization stage 2 on CCCAPB ....... Running optimization stage 2 on BUFD_DELAY ....... Running optimization stage 2 on ACT_UNIQUE_COREPLL_ELOCK_Z4 ....... Running optimization stage 2 on ACT_UNIQUE_CorePLL_ELOCK_Reset_Ctrl_1 ....... Running optimization stage 2 on ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3 ....... @N:CL201 : CorePLL_ELOCK_Ctrl_Fsm.v(236) | Trying to extract state machine for register PLL_ELOCK_CS. Extracted state machine for register PLL_ELOCK_CS State machine has 10 reachable states with original encodings of: 0000000001 0000000010 0000000100 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 @W:CL260 : CorePLL_ELOCK_Ctrl_Fsm.v(699) | Pruning register bit 6 of genblk3.PLL_ELOCK_APB_M_PADDR[7:4]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL159 : CorePLL_ELOCK_Ctrl_Fsm.v(58) | Input CCC_1_LOCK is unused. @N:CL159 : CorePLL_ELOCK_Ctrl_Fsm.v(61) | Input CCC_1_PLL_POWERDOWN_N is unused. Running optimization stage 2 on DFN1C0 ....... Running optimization stage 2 on RTG4FCCC_C0 ....... Running optimization stage 2 on RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on RTG4_uPROM ....... Running optimization stage 2 on RTG4UPROM_C0 ....... Running optimization stage 2 on RTG4UPROM ....... Running optimization stage 2 on RTG4UPROM_ADDR_TRANS ....... Running optimization stage 2 on UPROM ....... Running optimization stage 2 on COREUPROMIF_APB_C0 ....... Running optimization stage 2 on COREUPROMIF_APB_Z2 ....... @N:CL201 : coreupromif_apb.v(409) | Trying to extract state machine for register UCLK_currState. Extracted state machine for register UCLK_currState State machine has 4 reachable states with original encodings of: 0110 0111 1000 1001 @N:CL201 : coreupromif_apb.v(225) | Trying to extract state machine for register PCLK_currState. Extracted state machine for register PCLK_currState State machine has 6 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 @N:CL159 : coreupromif_apb.v(60) | Input UPROM_BUSY is unused. Running optimization stage 2 on RCOSC_50MHZ ....... Running optimization stage 2 on RAM_APB_BLK ....... Running optimization stage 2 on RTG4TPSRAM_C0 ....... Running optimization stage 2 on RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on RAM1K18_RT ....... Running optimization stage 2 on mux_blk ....... Running optimization stage 2 on APB_master_wrp_32s_16s_0_1_2_3 ....... @W:CL190 : APB_master_wrp.v(192) | Optimizing register bit raddr_int[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_master_wrp.v(192) | Optimizing register bit raddr_int[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : APB_master_wrp.v(192) | Pruning register bits 8 to 7 of raddr_int[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CL189 : APB_master_wrp.v(192) | Register bit raddr[8] is always 0. @N:CL189 : APB_master_wrp.v(192) | Register bit raddr[7] is always 0. @W:CL177 : APB_master_wrp.v(180) | Sharing sequential element init_done. Add a syn_preserve attribute to the element to prevent sharing. @W:CL279 : APB_master_wrp.v(192) | Pruning register bits 8 to 7 of raddr[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CL201 : APB_master_wrp.v(67) | Trying to extract state machine for register apb_fsm_state. Extracted state machine for register apb_fsm_state State machine has 3 reachable states with original encodings of: 000 001 010 @N:CL159 : APB_master_wrp.v(25) | Input PRDATA is unused. @N:CL159 : APB_master_wrp.v(29) | Input PSLVERR is unused. Running optimization stage 2 on CoreAPB3_C0 ....... Running optimization stage 2 on CoreAPB3_Z1 ....... @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Running optimization stage 2 on AND2 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime Process completed successfully. # Sat Dec 19 20:49:53 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 93MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sat Dec 19 20:49:53 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:07s realtime, 0h:00m:07s cputime Process completed successfully. # Sat Dec 19 20:49:53 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sat Dec 19 20:49:55 2020 ###########################################################] Premap Report # Sat Dec 19 20:49:56 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) Reading constraint file: C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(8) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) @N:FX1184 : | Applying syn_allowed_resources blockrams=209 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) @W:MT688 : synthesis.fdc(8) | No path from master pin (-source) to source of clock RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 due to black box RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - RCOSC_50MHZ_0/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 0 1 . RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 30.0 MHz 33.333 generated (from RCOSC_50MHZ_0/CLKOUT) default_clkgroup 221 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 56 =========================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RCOSC_50MHZ_0/CLKOUT 0 RCOSC_50MHZ_0.CLKOUT(RCOSC_50MHZ) - - - RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 221 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0.GL0(CCCDYN) RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_0_DFN1_0.CLK - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_0_GL0_INST.I(BUFG) System 0 - - - - RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock 56 RTG4FCCC_C0_0.RTG4FCCC_C0_0.CCC_INST.GL0(CCC) RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Reset_Ctrl_Inst.READY_VDDPLL_F1.C - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.CCCAPB_INSTANCE.APB_S_PCLK(CCCAPB) ================================================================================================================================================================================================================================================================================================================================================================ @W:MT530 : corepll_elock_ctrl_fsm.v(236) | Found inferred clock RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock which controls 56 sequential elements including RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[9:0]. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) Encoding state machine apb_fsm_state[2:0] (in view: work.APB_master_wrp_32s_16s_0_1_2_3(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 Encoding state machine PLL_ELOCK_CS[9:0] (in view: work.ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3(verilog)) original code -> new code 0000000001 -> 0000000001 0000000010 -> 0000000010 0000000100 -> 0000000100 0000001000 -> 0000001000 0000010000 -> 0000010000 0000100000 -> 0000100000 0001000000 -> 0001000000 0010000000 -> 0010000000 0100000000 -> 0100000000 1000000000 -> 1000000000 Encoding state machine PCLK_currState[5:0] (in view: work.COREUPROMIF_APB_Z2(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0011 -> 001000 0100 -> 010000 0101 -> 100000 Encoding state machine UCLK_currState[3:0] (in view: work.COREUPROMIF_APB_Z2(verilog)) original code -> new code 0110 -> 00 0111 -> 01 1000 -> 10 1001 -> 11 @N:MO225 : coreupromif_apb.v(409) | There are no possible illegal states for state machine UCLK_currState[3:0] (in view: work.COREUPROMIF_APB_Z2(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 189MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 101MB peak: 189MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Sat Dec 19 20:49:58 2020 ###########################################################] Map & Optimize Report # Sat Dec 19 20:49:58 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB) Available hyper_sources - for debug and ip models None Found @N:MF236 : uprom_trans.v(6) | Generating a type div divider Finished RTL optimizations (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 185MB peak: 187MB) Encoding state machine apb_fsm_state[2:0] (in view: work.APB_master_wrp_32s_16s_0_1_2_3(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 @N:MO231 : apb_master_wrp.v(67) | Found counter in view:work.APB_master_wrp_32s_16s_0_1_2_3(verilog) instance PADDR[15:2] @N:MO231 : apb_master_wrp.v(67) | Found counter in view:work.APB_master_wrp_32s_16s_0_1_2_3(verilog) instance waddr_int[8:0] @N:MO231 : apb_master_wrp.v(192) | Found counter in view:work.APB_master_wrp_32s_16s_0_1_2_3(verilog) instance raddr_int[6:0] Encoding state machine PLL_ELOCK_CS[9:0] (in view: work.ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3(verilog)) original code -> new code 0000000001 -> 0000000001 0000000010 -> 0000000010 0000000100 -> 0000000100 0000001000 -> 0000001000 0000010000 -> 0000010000 0000100000 -> 0000100000 0001000000 -> 0001000000 0010000000 -> 0010000000 0100000000 -> 0100000000 1000000000 -> 1000000000 @N:MO231 : corepll_elock_ctrl_fsm.v(610) | Found counter in view:work.ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3(verilog) instance DELAY_CNTR[13:0] @W:BN132 : corepll_elock_ctrl_fsm.v(699) | Removing instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PADDR[5] because it is equivalent to instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PADDR[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corepll_elock_ctrl_fsm.v(715) | Removing instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PWDATA[0] because it is equivalent to instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PADDR[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine PCLK_currState[5:0] (in view: work.COREUPROMIF_APB_Z2(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0011 -> 001000 0100 -> 010000 0101 -> 100000 Encoding state machine UCLK_currState[3:0] (in view: work.COREUPROMIF_APB_Z2(verilog)) original code -> new code 0110 -> 00 0111 -> 01 1000 -> 10 1001 -> 11 @N:MO225 : coreupromif_apb.v(409) | There are no possible illegal states for state machine UCLK_currState[3:0] (in view: work.COREUPROMIF_APB_Z2(verilog)); safe FSM implementation is not required. Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 186MB peak: 187MB) @N:BN362 : apb_master_wrp.v(67) | Removing sequential instance RAM_APB_BLK_0.APB_master_wrp_0.PENABLE (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 188MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 189MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 189MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 189MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 189MB peak: 190MB) Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 189MB peak: 190MB) Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 192MB peak: 192MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:04s -3.30ns 342 / 265 2 0h:00m:04s -3.30ns 341 / 265 3 0h:00m:04s -3.21ns 340 / 265 4 0h:00m:04s -3.21ns 340 / 265 5 0h:00m:04s -3.21ns 340 / 265 @N:FP130 : | Promoting Net AND2_0_Y on CLKINT I_179 @N:FP130 : | Promoting Net RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_sync_reset on CLKINT I_180 @N:FP130 : | Promoting Net RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.ARST_N_arst on CLKINT I_181 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 193MB peak: 193MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 193MB peak: 193MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 272 clock pin(s) of sequential element(s) 0 instances converted, 272 sequential instances remain driven by gated/generated clocks ========================================================================================================================== Gated/Generated Clocks ========================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 CCCDYN 217 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_0_DFN1_0 No gated clock conversion method for cell cell:ACG4.DFN1C0 ClockId0002 RTG4FCCC_C0_0.RTG4FCCC_C0_0.CCC_INST CCC 55 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.DELAY_CNTR[13] No gated clock conversion method for cell cell:ACG4.SLE ============================================================================================================================================================================================================================================================================ ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 193MB) Writing Analyst data base C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 192MB peak: 193MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 193MB peak: 193MB) Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 191MB peak: 193MB) @W:MT246 : rtg4fcccecalib_c0_rtg4fcccecalib_c0_0_rtg4fcccecalib.v(210) | Blackbox CCCDYN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : rtg4fccc_c0_rtg4fccc_c0_0_rtg4fccc.v(18) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock RCOSC_50MHZ_0/CLKOUT with period 20.00ns @N:MT615 : | Found clock RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 with period 33.33ns @W:MT420 : | Found inferred clock RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net RTG4FCCC_C0_0.RTG4FCCC_C0_0.GL0_net. ##### START OF TIMING REPORT #####[ # Timing report written on Sat Dec 19 20:50:05 2020 # Top view: top Requested Frequency: 30.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.513 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RCOSC_50MHZ_0/CLKOUT 50.0 MHz NA 20.000 NA NA declared default_clkgroup RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 30.0 MHz 39.4 MHz 33.333 25.407 7.926 generated (from RCOSC_50MHZ_0/CLKOUT) default_clkgroup RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock 100.0 MHz 105.4 MHz 10.000 9.487 0.513 inferred Inferred_clkgroup_0 System 100.0 MHz 226.4 MHz 10.000 4.416 5.584 system system_clkgroup ============================================================================================================================================================================================= Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 33.333 30.699 | No paths - | No paths - | No paths - System RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock | 10.000 5.584 | No paths - | No paths - | No paths - RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 33.333 7.927 | No paths - | No paths - | 16.667 14.867 RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock System | 10.000 4.127 | No paths - | No paths - | No paths - RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | Diff grp - | No paths - | No paths - | No paths - RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock | 10.000 0.513 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[1] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[1] 0.177 7.926 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[2] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[2] 0.177 7.941 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[3] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[3] 0.177 7.955 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[4] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[4] 0.177 7.968 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[5] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[5] 0.177 7.982 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[6] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[6] 0.177 7.997 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[7] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[7] 0.177 8.011 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[8] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[8] 0.177 8.024 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[9] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[9] 0.177 8.039 RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[10] RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 SLE Q COREUPROMIF_APB_C0_0_UPROM_ADDR[10] 0.177 8.053 ====================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[4] ADDR_TRANS[4] 28.557 7.926 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[6] ADDR_TRANS[6] 28.558 7.928 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[7] ADDR_TRANS[7] 28.558 7.928 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[5] ADDR_TRANS[5] 28.561 7.931 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[10] ADDR_TRANS[10] 28.568 7.938 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[12] ADDR_TRANS[12] 28.568 7.938 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[8] ADDR_TRANS[8] 28.569 7.939 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[9] ADDR_TRANS[9] 28.569 7.939 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[11] ADDR_TRANS[11] 28.569 7.939 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 UPROM ADDR[13] ADDR_TRANS[13] 28.581 7.950 ============================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 33.333 - Setup time: 4.776 + Clock delay at ending point: 0.000 (ideal) = Required time: 28.557 - Propagation time: 20.631 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.927 Number of logic level(s): 76 Starting point: RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[1] / Q Ending point: RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 / ADDR[4] The start point is clocked by RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 [rising] (rise=0.000 fall=16.667 period=33.333) on pin CLK The end point is clocked by RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 [rising] (rise=0.000 fall=16.667 period=33.333) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_UPROM_ADDR_1[1] SLE Q Out 0.177 0.177 f - COREUPROMIF_APB_C0_0_UPROM_ADDR[1] Net - - 0.075 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_0 ARI1 B In - 0.253 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_0 ARI1 FCO Out 0.520 0.773 f - ADDR_IN_P30_cry_0 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_1 ARI1 FCI In - 0.773 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_1 ARI1 FCO Out 0.014 0.787 f - ADDR_IN_P30_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_2 ARI1 FCI In - 0.787 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_2 ARI1 FCO Out 0.014 0.801 f - ADDR_IN_P30_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_3 ARI1 FCI In - 0.801 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_3 ARI1 FCO Out 0.014 0.815 f - ADDR_IN_P30_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_4 ARI1 FCI In - 0.815 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_4 ARI1 FCO Out 0.014 0.829 f - ADDR_IN_P30_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_5 ARI1 FCI In - 0.829 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_5 ARI1 FCO Out 0.014 0.843 f - ADDR_IN_P30_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_6 ARI1 FCI In - 0.843 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_6 ARI1 FCO Out 0.014 0.857 f - ADDR_IN_P30_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_7 ARI1 FCI In - 0.857 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_7 ARI1 FCO Out 0.014 0.871 f - ADDR_IN_P30_cry_7 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_8 ARI1 FCI In - 0.871 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_8 ARI1 FCO Out 0.014 0.885 f - ADDR_IN_P30_cry_8 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_9 ARI1 FCI In - 0.885 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_9 ARI1 FCO Out 0.014 0.899 f - ADDR_IN_P30_cry_9 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_10 ARI1 FCI In - 0.899 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_10 ARI1 FCO Out 0.014 0.913 f - ADDR_IN_P30_cry_10 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_11 ARI1 FCI In - 0.913 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_11 ARI1 FCO Out 0.014 0.927 f - ADDR_IN_P30_cry_11 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_12 ARI1 FCI In - 0.927 f - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_IN_P30_cry_12 ARI1 S Out 0.480 1.407 r - ADDR_IN_P30[13] Net - - 0.691 - 5 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un47_sum_cry_2 ARI1 C In - 2.098 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un47_sum_cry_2 ARI1 FCO Out 0.670 2.768 r - mult1_un47_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un47_sum_cry_3 ARI1 FCI In - 2.768 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un47_sum_cry_3 ARI1 S Out 0.480 3.248 r - mult1_un47_sum_cry_3_S Net - - 0.075 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_cry_4 ARI1 B In - 3.324 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_cry_4 ARI1 FCO Out 0.520 3.844 r - mult1_un54_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_cry_5 ARI1 FCI In - 3.844 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_cry_5 ARI1 FCO Out 0.014 3.857 r - mult1_un54_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_cry_6 ARI1 FCI In - 3.857 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_cry_6 ARI1 FCO Out 0.014 3.872 r - mult1_un54_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_s_7 ARI1 FCI In - 3.872 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un54_sum_s_7 ARI1 S Out 0.480 4.352 r - mult1_temp_b_9[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_1 ARI1 A In - 5.149 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_1 ARI1 FCO Out 0.480 5.629 r - mult1_un61_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_2 ARI1 FCI In - 5.629 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_2 ARI1 FCO Out 0.014 5.643 r - mult1_un61_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_3 ARI1 FCI In - 5.643 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_3 ARI1 FCO Out 0.014 5.657 r - mult1_un61_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_4 ARI1 FCI In - 5.657 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_4 ARI1 FCO Out 0.014 5.671 r - mult1_un61_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_5 ARI1 FCI In - 5.671 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_5 ARI1 FCO Out 0.014 5.685 r - mult1_un61_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_6 ARI1 FCI In - 5.685 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_cry_6 ARI1 FCO Out 0.014 5.699 r - mult1_un61_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_s_7 ARI1 FCI In - 5.699 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un61_sum_s_7 ARI1 S Out 0.480 6.179 r - mult1_temp_b_10[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_1 ARI1 A In - 6.976 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_1 ARI1 FCO Out 0.480 7.456 r - mult1_un68_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_2 ARI1 FCI In - 7.456 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_2 ARI1 FCO Out 0.014 7.470 r - mult1_un68_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_3 ARI1 FCI In - 7.470 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_3 ARI1 FCO Out 0.014 7.484 r - mult1_un68_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_4 ARI1 FCI In - 7.484 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_4 ARI1 FCO Out 0.014 7.498 r - mult1_un68_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_5 ARI1 FCI In - 7.498 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_5 ARI1 FCO Out 0.014 7.512 r - mult1_un68_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_6 ARI1 FCI In - 7.512 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_cry_6 ARI1 FCO Out 0.014 7.526 r - mult1_un68_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_s_7 ARI1 FCI In - 7.526 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un68_sum_s_7 ARI1 S Out 0.480 8.006 r - mult1_temp_b_11[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_1 ARI1 A In - 8.803 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_1 ARI1 FCO Out 0.480 9.283 r - mult1_un75_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_2 ARI1 FCI In - 9.283 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_2 ARI1 FCO Out 0.014 9.297 r - mult1_un75_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_3 ARI1 FCI In - 9.297 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_3 ARI1 FCO Out 0.014 9.311 r - mult1_un75_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_4 ARI1 FCI In - 9.311 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_4 ARI1 FCO Out 0.014 9.325 r - mult1_un75_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_5 ARI1 FCI In - 9.325 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_5 ARI1 FCO Out 0.014 9.339 r - mult1_un75_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_6 ARI1 FCI In - 9.339 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_cry_6 ARI1 FCO Out 0.014 9.353 r - mult1_un75_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_s_7 ARI1 FCI In - 9.353 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un75_sum_s_7 ARI1 S Out 0.480 9.834 r - mult1_temp_b_12[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_1 ARI1 A In - 10.631 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_1 ARI1 FCO Out 0.480 11.111 r - mult1_un82_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_2 ARI1 FCI In - 11.111 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_2 ARI1 FCO Out 0.014 11.125 r - mult1_un82_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_3 ARI1 FCI In - 11.125 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_3 ARI1 FCO Out 0.014 11.139 r - mult1_un82_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_4 ARI1 FCI In - 11.139 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_4 ARI1 FCO Out 0.014 11.153 r - mult1_un82_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_5 ARI1 FCI In - 11.153 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_5 ARI1 FCO Out 0.014 11.167 r - mult1_un82_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_6 ARI1 FCI In - 11.167 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_cry_6 ARI1 FCO Out 0.014 11.181 r - mult1_un82_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_s_7 ARI1 FCI In - 11.181 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un82_sum_s_7 ARI1 S Out 0.480 11.661 r - mult1_temp_b_13[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_1 ARI1 A In - 12.458 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_1 ARI1 FCO Out 0.480 12.938 r - mult1_un89_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_2 ARI1 FCI In - 12.938 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_2 ARI1 FCO Out 0.014 12.952 r - mult1_un89_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_3 ARI1 FCI In - 12.952 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_3 ARI1 FCO Out 0.014 12.966 r - mult1_un89_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_4 ARI1 FCI In - 12.966 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_4 ARI1 FCO Out 0.014 12.980 r - mult1_un89_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_5 ARI1 FCI In - 12.980 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_5 ARI1 FCO Out 0.014 12.994 r - mult1_un89_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_6 ARI1 FCI In - 12.994 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_cry_6 ARI1 FCO Out 0.014 13.008 r - mult1_un89_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_s_7 ARI1 FCI In - 13.008 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un89_sum_s_7 ARI1 S Out 0.480 13.488 r - mult1_temp_b_14[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_1 ARI1 A In - 14.285 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_1 ARI1 FCO Out 0.480 14.765 r - mult1_un96_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_2 ARI1 FCI In - 14.765 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_2 ARI1 FCO Out 0.014 14.779 r - mult1_un96_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_3 ARI1 FCI In - 14.779 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_3 ARI1 FCO Out 0.014 14.793 r - mult1_un96_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_4 ARI1 FCI In - 14.793 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_4 ARI1 FCO Out 0.014 14.807 r - mult1_un96_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_5 ARI1 FCI In - 14.807 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_5 ARI1 FCO Out 0.014 14.821 r - mult1_un96_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_6 ARI1 FCI In - 14.821 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_cry_6 ARI1 FCO Out 0.014 14.835 r - mult1_un96_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_s_7 ARI1 FCI In - 14.835 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un96_sum_s_7 ARI1 S Out 0.480 15.315 r - mult1_temp_b_15[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_1 ARI1 A In - 16.113 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_1 ARI1 FCO Out 0.480 16.593 r - mult1_un103_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_2 ARI1 FCI In - 16.593 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_2 ARI1 FCO Out 0.014 16.607 r - mult1_un103_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_3 ARI1 FCI In - 16.607 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_3 ARI1 FCO Out 0.014 16.621 r - mult1_un103_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_4 ARI1 FCI In - 16.621 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_4 ARI1 FCO Out 0.014 16.635 r - mult1_un103_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_5 ARI1 FCI In - 16.635 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_5 ARI1 FCO Out 0.014 16.649 r - mult1_un103_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_6 ARI1 FCI In - 16.649 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_cry_6 ARI1 FCO Out 0.014 16.663 r - mult1_un103_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_s_7 ARI1 FCI In - 16.663 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un103_sum_s_7 ARI1 S Out 0.480 17.143 r - mult1_temp_b_16[4] Net - - 0.797 - 9 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_1 ARI1 A In - 17.940 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_1 ARI1 FCO Out 0.480 18.420 r - mult1_un110_sum_cry_1 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_2 ARI1 FCI In - 18.420 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_2 ARI1 FCO Out 0.014 18.434 r - mult1_un110_sum_cry_2 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_3 ARI1 FCI In - 18.434 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_3 ARI1 FCO Out 0.014 18.448 r - mult1_un110_sum_cry_3 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_4 ARI1 FCI In - 18.448 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_4 ARI1 FCO Out 0.014 18.462 r - mult1_un110_sum_cry_4 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_5 ARI1 FCI In - 18.462 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_5 ARI1 FCO Out 0.014 18.476 r - mult1_un110_sum_cry_5 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_6 ARI1 FCI In - 18.476 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_cry_6 ARI1 FCO Out 0.014 18.490 r - mult1_un110_sum_cry_6 Net - - 0.000 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_s_7 ARI1 FCI In - 18.490 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.un5_ADDR_OUT.if_generate_plus\.mult1_un110_sum_s_7 ARI1 S Out 0.480 18.970 r - mult1_un110_sum_i[10] Net - - 0.826 - 11 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_OUT_m[4] CFG3 B In - 19.796 r - RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.RTG4UPROM_ADDR_TRANS_0.ADDR_OUT_m[4] CFG3 Y Out 0.158 19.954 r - ADDR_TRANS[4] Net - - 0.677 - 1 RTG4_uPROM_0.RTG4UPROM_C0_0.RTG4UPROM_C0_0.UPROM_0 UPROM ADDR[4] In - 20.631 r - ========================================================================================================================================================================================== Total path delay (propagation time + setup) of 25.407 is 16.684(65.7%) logic and 8.723(34.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q CCC_APB_INST_APB_S_PSEL_COREPLL_ELOCK_0_CCC_APB_PSEL_net 0.177 0.513 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3\.PLL_ELOCK_APB_M_PADDR[2] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q PLL_ELOCK_APB_M_PADDR[2] 0.177 4.127 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3\.PLL_ELOCK_APB_M_PADDR[7] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q PLL_ELOCK_APB_M_PADDR[7] 0.177 4.139 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3\.PLL_ELOCK_APB_M_PWDATA[1] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q PLL_ELOCK_APB_M_PWDATA[1] 0.177 4.145 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PENABLE RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q CCC_APB_INST_APB_S_PENABLE_COREPLL_ELOCK_0_CCC_APB_PENABLE_net 0.177 4.155 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3\.PLL_ELOCK_APB_M_PADDR[4] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q PLL_ELOCK_APB_M_PADDR[4] 0.177 4.158 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3\.PLL_ELOCK_APB_M_PWDATA[2] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q PLL_ELOCK_APB_M_PWDATA[2] 0.177 4.164 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.DELAY_CNTR[12] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q DELAY_CNTR[12] 0.173 5.245 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.DELAY_CNTR[10] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q DELAY_CNTR[10] 0.173 5.280 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.DELAY_CNTR[7] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE Q DELAY_CNTR[7] 0.173 5.290 ============================================================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[3] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE D N_177_i 8.877 0.513 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[2] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE D PLL_ELOCK_CS_ns[2] 8.877 0.576 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[4] RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE D PLL_ELOCK_CS_ns[4] 8.877 0.576 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PENABLE RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE D APB_WRITE_BEAT_COMP 8.877 0.968 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE D APB_WRITE_BEAT_COMP 8.877 0.968 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PENABLE RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE EN un1_APB_WRITE_BEAT_COMP_1 9.056 1.664 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock SLE EN N_226_i 9.056 1.664 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock CCCDYN APB_S_PADDR[5] APB_S_PADDR_OUT[5] 10.000 4.127 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock CCCDYN APB_S_PADDR[7] APB_S_PADDR_OUT[7] 10.000 4.139 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock CCCDYN APB_S_PWDATA[1] APB_S_PWDATA_OUT[1] 10.000 4.145 ============================================================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.123 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.877 - Propagation time: 8.364 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.513 Number of logic level(s): 9 Starting point: RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL / Q Ending point: RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[3] / D The start point is clocked by RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL SLE Q Out 0.177 0.177 f - CCC_APB_INST_APB_S_PSEL_COREPLL_ELOCK_0_CCC_APB_PSEL_net Net - - 0.684 - 2 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_1 BUFD_DELAY A In - 0.861 f - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_1 BUFD_DELAY Y Out 0.300 1.161 r - APB_S_PSEL_BUFD_1_output_net Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_2 BUFD_DELAY A In - 1.838 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_2 BUFD_DELAY Y Out 0.300 2.138 r - APB_S_PSEL_BUFD_2_output_net Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_3 BUFD_DELAY A In - 2.815 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_3 BUFD_DELAY Y Out 0.300 3.115 r - APB_S_PSEL_BUFD_3_output_net Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_4 BUFD_DELAY A In - 3.792 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_BUFD_4 BUFD_DELAY Y Out 0.300 4.092 r - apb_s_psel_B_input_net Net - - 0.684 - 2 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_CCC_1_Instance AND2 B In - 4.776 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PSEL_CCC_1_Instance AND2 Y Out 0.156 4.932 r - APB_S_PSEL_CCC_1 Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_CCC_1_Instance AND2 B In - 5.609 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_CCC_1_Instance AND2 Y Out 0.156 5.766 r - apb_s_pready_or_B_input_net Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_OR_Instance OR2 B In - 6.442 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_OR_Instance OR2 Y Out 0.156 6.599 r - CCC_APB_INST_APB_S_PREADY_COREPLL_ELOCK_0_CCC_APB_PREADY_net Net - - 0.515 - 3 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.APB_WRITE_BEAT_COMP CFG2 A In - 7.114 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.APB_WRITE_BEAT_COMP CFG2 Y Out 0.104 7.218 f - APB_WRITE_BEAT_COMP Net - - 0.691 - 5 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS_RNO[3] CFG4 D In - 7.909 f - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS_RNO[3] CFG4 Y Out 0.379 8.288 f - N_177_i Net - - 0.075 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[3] SLE D In - 8.364 f - ============================================================================================================================================================================= Total path delay (propagation time + setup) of 9.487 is 3.453(36.4%) logic and 6.034(63.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 System CCCDYN APB_S_PREADY CCC_APB_INST_CCC_0_APB_S_PREADY_CCC_INST_0_APB_S_PREADY_net 0.000 5.584 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 System CCCDYN LOCK ccc_0_lock_0_dfn1_0_clr_net 0.000 8.200 ================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[3] System SLE D N_177_i 8.877 5.584 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[2] System SLE D PLL_ELOCK_CS_ns[2] 8.877 5.664 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[4] System SLE D PLL_ELOCK_CS_ns[4] 8.877 5.664 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PENABLE System SLE D APB_WRITE_BEAT_COMP 8.877 6.038 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL System SLE D APB_WRITE_BEAT_COMP 8.877 6.038 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PENABLE System SLE EN un1_APB_WRITE_BEAT_COMP_1 9.056 6.735 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_APB_M_PSEL System SLE EN N_226_i 9.056 6.735 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk1\.CCC0_LOCK_F1 System SLE D ccc_0_lock_0_dfn1_0_clr_net 8.877 8.200 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_0_DFN1_0 System DFN1C0 D ccc_0_lock_0_dfn1_0_d_net 32.210 30.699 ==================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.123 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.877 - Propagation time: 3.293 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 5.584 Number of logic level(s): 4 Starting point: RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 / APB_S_PREADY Ending point: RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[3] / D The start point is clocked by System [rising] The end point is clocked by RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0 CCCDYN APB_S_PREADY Out 0.000 0.000 r - CCC_APB_INST_CCC_0_APB_S_PREADY_CCC_INST_0_APB_S_PREADY_net Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_CCC_0_Instance AND2 A In - 0.677 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_CCC_0_Instance AND2 Y Out 0.087 0.764 r - apb_s_pready_or_A_input_net Net - - 0.677 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_OR_Instance OR2 A In - 1.441 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_APB_INST.APB_S_PREADY_OR_Instance OR2 Y Out 0.087 1.528 r - CCC_APB_INST_APB_S_PREADY_COREPLL_ELOCK_0_CCC_APB_PREADY_net Net - - 0.515 - 3 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.APB_WRITE_BEAT_COMP CFG2 A In - 2.043 r - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.APB_WRITE_BEAT_COMP CFG2 Y Out 0.104 2.147 f - APB_WRITE_BEAT_COMP Net - - 0.691 - 5 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS_RNO[3] CFG4 D In - 2.839 f - RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS_RNO[3] CFG4 Y Out 0.379 3.218 f - N_177_i Net - - 0.075 - 1 RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.PLL_ELOCK_CS[3] SLE D In - 3.293 f - ================================================================================================================================================================================ Total path delay (propagation time + setup) of 4.416 is 1.781(40.3%) logic and 2.635(59.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(9) | Timing constraint (from [get_cells { RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.*CCC_0_LOCK_EN }] to [get_pins { RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_0_DFN1_0.D }]) (false path) was not applied to the design because no matching path was synchronous None Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 192MB peak: 193MB) Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 192MB peak: 193MB) --------------------------------------- Resource Usage Report for top Mapping to part: rt4g150cg1657-1 Cell usage: AND2 6 uses BUFD_DELAY 57 uses CCC 1 use CCCAPB 1 use CCCDYN 1 use CLKINT 5 uses DFN1C0 3 uses INV 1 use OR2 1 use RCOSC_50MHZ 1 use SYSRESET 1 use UPROM 1 use CFG1 4 uses CFG2 33 uses CFG3 88 uses CFG4 43 uses Carry cells: ARI1 156 uses - used for arithmetic functions Sequential Cells: SLE 266 uses DSP Blocks: 0 of 462 (0%) I/O ports: 131 I/O primitives: 128 INBUF 56 uses OUTBUF 72 uses Global Clock Buffers: 5 RAM/ROM usage summary Total Block RAMs (RAM1K18_RT) : 1 of 209 (0%) Total LUTs: 324 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18_RT Interface Logic : SLEs = 0; LUTs = 0; RAM1K18_RT Interface Logic : SLEs = 36; LUTs = 36; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 266 + 0 + 36 + 0 = 302; Total number of LUTs after P&R: 324 + 0 + 36 + 0 = 360; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 67MB peak: 193MB) Process took 0h:00m:07s realtime, 0h:00m:07s cputime # Sat Dec 19 20:50:06 2020 ###########################################################]