@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: FX1184 |Applying syn_allowed_resources blockrams=209 on top level netlist top 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\synthesis\top.sap.
@N: MO225 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_verilog\libero_project\component\actel\directcore\coreupromif_apb\3.0.102\rtl\vlog\core\coreupromif_apb.v":409:0:409:5|There are no possible illegal states for state machine UCLK_currState[3:0] (in view: work.COREUPROMIF_APB_Z2(verilog)); safe FSM implementation is not required.
