@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_verilog\libero_project\component\actel\sgcore\rtg4fcccecalib\2.1.010\corepll_elock_ctrl_fsm.v":699:6:699:11|Removing instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PADDR[5] because it is equivalent to instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PADDR[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_verilog\libero_project\component\actel\sgcore\rtg4fcccecalib\2.1.010\corepll_elock_ctrl_fsm.v":715:6:715:11|Removing instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PWDATA[0] because it is equivalent to instance RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.genblk3.PLL_ELOCK_APB_M_PADDR[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT246 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_verilog\libero_project\component\work\rtg4fcccecalib_c0\rtg4fcccecalib_c0_0\rtg4fcccecalib_c0_rtg4fcccecalib_c0_0_rtg4fcccecalib.v":210:12:210:21|Blackbox CCCDYN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_verilog\libero_project\component\work\rtg4fccc_c0\rtg4fccc_c0_0\rtg4fccc_c0_rtg4fccc_c0_0_rtg4fccc.v":18:38:18:45|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net RTG4FCCC_C0_0.RTG4FCCC_C0_0.GL0_net.
@W: MT447 :"c:/wfh_tasks/rtg4_v12.6_updates/ac454_sram_verilog/libero_project/designer/top/synthesis.fdc":9:0:9:0|Timing constraint (from [get_cells { RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.CorePLL_ELOCK_Ctrl_Fsm_Inst.*CCC_0_LOCK_EN }] to [get_pins { RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_0_DFN1_0.D }]) (false path) was not applied to the design because no matching path was synchronous 
