@W: CG1337 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\COREUPROMIF_APB\3.0.102\rtl\vlog\core\coreupromif_apb.v":404:7:404:21|Net UCLK_sync_pulse is not declared.
@W: CG360 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWDATA[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Optimizing register bit PWRITE to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Pruning unused register PWRITE. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Pruning unused register PWDATA[31:0]. Make sure that there are no unused intermediate registers.
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCC_C0\RTG4FCCC_C0_0\RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v":18:38:18:45|Type of parameter VCOFREQUENCY on the instance CCC_INST is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":338:2:338:7|Pruning unused register CCC_0_CONFIG_DONE. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":397:6:397:11|Optimizing register bit genblk1.CCC_0_RECALIB_EN to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":699:6:699:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PADDR[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":699:6:699:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PADDR[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":715:6:715:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":715:6:715:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":715:6:715:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":715:6:715:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":715:6:715:11|Optimizing register bit genblk3.PLL_ELOCK_APB_M_PWDATA[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":715:6:715:11|Pruning register bits 7 to 3 of genblk3.PLL_ELOCK_APB_M_PWDATA[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":699:6:699:11|Pruning register bit 8 of genblk3.PLL_ELOCK_APB_M_PADDR[8:2]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":699:6:699:11|Pruning register bit 3 of genblk3.PLL_ELOCK_APB_M_PADDR[8:2]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":397:6:397:11|Pruning unused register genblk1.CCC_0_RECALIB_EN. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v":22:27:22:40|Removing wire \gnd_net_-1_-1, as there is no assignment to it.
@W: CL156 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v":22:27:22:40|*Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v":22:27:22:40|*Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v":22:27:22:40|*Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v":22:27:22:40|*Input \gnd_net_-1_-1 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL260 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":699:6:699:11|Pruning register bit 6 of genblk3.PLL_ELOCK_APB_M_PADDR[7:4]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":192:0:192:5|Optimizing register bit raddr_int[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":192:0:192:5|Optimizing register bit raddr_int[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":192:0:192:5|Pruning register bits 8 to 7 of raddr_int[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL177 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":180:0:180:5|Sharing sequential element init_done. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL279 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":192:0:192:5|Pruning register bits 8 to 7 of raddr[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

