@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":129:7:129:10|Synthesizing module AND2 in library work.
@N: CG775 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3 in library COREAPB3_LIB.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\CoreAPB3_C0\CoreAPB3_C0.v":57:7:57:17|Synthesizing module CoreAPB3_C0 in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":21:7:21:20|Synthesizing module APB_master_wrp in library work.
@N: CG179 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":107:41:107:45|Removing redundant assignment.
@N: CG179 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":108:45:108:53|Removing redundant assignment.
@N: CG179 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":117:41:117:45|Removing redundant assignment.
@N: CG179 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":118:45:118:53|Removing redundant assignment.
@N: CG179 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":212:21:212:29|Removing redundant assignment.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\mux_blk.v":2:7:2:13|Synthesizing module mux_blk in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":712:7:712:16|Synthesizing module RAM1K18_RT in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":376:7:376:9|Synthesizing module GND in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":380:7:380:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4TPSRAM_C0\RTG4TPSRAM_C0_0\RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM.v":5:7:5:46|Synthesizing module RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4TPSRAM_C0\RTG4TPSRAM_C0.v":56:7:56:19|Synthesizing module RTG4TPSRAM_C0 in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RAM_APB_BLK\RAM_APB_BLK.v":9:7:9:17|Synthesizing module RAM_APB_BLK in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":666:7:666:17|Synthesizing module RCOSC_50MHZ in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\COREUPROMIF_APB\3.0.102\rtl\vlog\core\coreupromif_apb.v":20:7:20:21|Synthesizing module COREUPROMIF_APB in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\COREUPROMIF_APB_C0\COREUPROMIF_APB_C0.v":21:7:21:24|Synthesizing module COREUPROMIF_APB_C0 in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4UPROM_C0\RTG4UPROM_C0_0\UPROM_0_syn.v":5:7:5:11|Synthesizing module UPROM in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4UPROM\2.1.100\uprom_trans.v":1:7:1:26|Synthesizing module RTG4UPROM_ADDR_TRANS in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4UPROM\2.1.100\uprom_trans.v":9:7:9:15|Synthesizing module RTG4UPROM in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4UPROM_C0\RTG4UPROM_C0.v":22:7:22:18|Synthesizing module RTG4UPROM_C0 in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4_uPROM\RTG4_uPROM.v":9:7:9:16|Synthesizing module RTG4_uPROM in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":353:7:353:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\ccc_comps.v":1:7:1:9|Synthesizing module CCC in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCC_C0\RTG4FCCC_C0_0\RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v":5:7:5:40|Synthesizing module RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCC_C0\RTG4FCCC_C0.v":145:7:145:17|Synthesizing module RTG4FCCC_C0 in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":48:7:48:12|Synthesizing module DFN1C0 in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":29:7:29:39|Synthesizing module ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Reset_Ctrl.v":22:7:22:41|Synthesizing module ACT_UNIQUE_CorePLL_ELOCK_Reset_Ctrl in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK.v":31:7:31:30|Synthesizing module ACT_UNIQUE_COREPLL_ELOCK in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\ccc_comps.v":312:7:312:16|Synthesizing module BUFD_DELAY in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\ccc_comps.v":216:7:216:12|Synthesizing module CCCAPB in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":141:7:141:9|Synthesizing module OR2 in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":231:7:231:9|Synthesizing module INV in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CCCAPBIF.v":5:7:5:55|Synthesizing module RTG4CCCAPB_IF_C0_RTG4CCCAPB_IF_C0_0_RTG4CCCAPB_IF in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\ccc_comps.v":110:7:110:12|Synthesizing module CCCDYN in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0_0\RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v":5:7:5:58|Synthesizing module RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\RTG4FCCCECALIB_C0\RTG4FCCCECALIB_C0.v":274:7:274:23|Synthesizing module RTG4FCCCECALIB_C0 in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\rtg4.v":703:7:703:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\work\top\top.v":9:7:9:9|Synthesizing module top in library work.
@N: CL201 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":236:0:236:5|Trying to extract state machine for register PLL_ELOCK_CS.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":58:19:58:28|Input CCC_1_LOCK is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\SgCore\RTG4FCCCECALIB\2.1.010\CorePLL_ELOCK_Ctrl_Fsm.v":61:19:61:39|Input CCC_1_PLL_POWERDOWN_N is unused.
@N: CL201 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\COREUPROMIF_APB\3.0.102\rtl\vlog\core\coreupromif_apb.v":409:0:409:5|Trying to extract state machine for register UCLK_currState.
@N: CL201 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\COREUPROMIF_APB\3.0.102\rtl\vlog\core\coreupromif_apb.v":225:0:225:5|Trying to extract state machine for register PCLK_currState.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\COREUPROMIF_APB\3.0.102\rtl\vlog\core\coreupromif_apb.v":60:17:60:26|Input UPROM_BUSY is unused.
@N: CL189 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":192:0:192:5|Register bit raddr[8] is always 0.
@N: CL189 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":192:0:192:5|Register bit raddr[7] is always 0.
@N: CL201 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":67:0:67:5|Trying to extract state machine for register apb_fsm_state.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":25:32:25:37|Input PRDATA is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\hdl\APB_master_wrp.v":29:32:29:38|Input PSLVERR is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":72:36:72:40|Input IADDR is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":73:13:73:19|Input PRESETN is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":74:13:74:16|Input PCLK is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":105:18:105:25|Input PRDATAS1 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":106:18:106:25|Input PRDATAS2 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":107:18:107:25|Input PRDATAS3 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":108:18:108:25|Input PRDATAS4 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":109:18:109:25|Input PRDATAS5 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":110:18:110:25|Input PRDATAS6 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":111:18:111:25|Input PRDATAS7 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":112:18:112:25|Input PRDATAS8 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":113:18:113:25|Input PRDATAS9 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":114:18:114:26|Input PRDATAS10 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":115:18:115:26|Input PRDATAS11 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":116:18:116:26|Input PRDATAS12 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":117:18:117:26|Input PRDATAS13 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":118:18:118:26|Input PRDATAS14 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":119:18:119:26|Input PRDATAS15 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":122:13:122:20|Input PREADYS1 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":123:13:123:20|Input PREADYS2 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":124:13:124:20|Input PREADYS3 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":125:13:125:20|Input PREADYS4 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":126:13:126:20|Input PREADYS5 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":127:13:127:20|Input PREADYS6 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":128:13:128:20|Input PREADYS7 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":129:13:129:20|Input PREADYS8 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":130:13:130:20|Input PREADYS9 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":131:13:131:21|Input PREADYS10 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":132:13:132:21|Input PREADYS11 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":133:13:133:21|Input PREADYS12 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":134:13:134:21|Input PREADYS13 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":135:13:135:21|Input PREADYS14 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":136:13:136:21|Input PREADYS15 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":139:13:139:21|Input PSLVERRS1 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":140:13:140:21|Input PSLVERRS2 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":141:13:141:21|Input PSLVERRS3 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":142:13:142:21|Input PSLVERRS4 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":143:13:143:21|Input PSLVERRS5 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":144:13:144:21|Input PSLVERRS6 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":145:13:145:21|Input PSLVERRS7 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":146:13:146:21|Input PSLVERRS8 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":147:13:147:21|Input PSLVERRS9 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":148:13:148:22|Input PSLVERRS10 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":149:13:149:22|Input PSLVERRS11 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":150:13:150:22|Input PSLVERRS12 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":151:13:151:22|Input PSLVERRS13 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":152:13:152:22|Input PSLVERRS14 is unused.
@N: CL159 :"C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":153:13:153:22|Input PSLVERRS15 is unused.
@N|Running in 64-bit mode

