#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project\synthesis\run_options.txt
#--  Written on Sat Dec 19 20:49:45 2020


#project files
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/CoreAPB3_C0/CoreAPB3_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/hdl/APB_master_wrp.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4TPSRAM_C0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4TPSRAM_C0/RTG4TPSRAM_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/hdl/mux_blk.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RAM_APB_BLK/RAM_APB_BLK.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/ccc_comps.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CCCAPBIF.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CorePLL_ELOCK_Reset_Ctrl.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CorePLL_ELOCK_Ctrl_Fsm.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CorePLL_ELOCK.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCCECALIB_C0/RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCCECALIB_C0/RTG4FCCCECALIB_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCC_C0/RTG4FCCC_C0_0/RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCC_C0/RTG4FCCC_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/DirectCore/COREUPROMIF_APB/3.0.102/rtl/vlog/core/coreupromif_apb.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/COREUPROMIF_APB_C0/COREUPROMIF_APB_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4UPROM/2.1.100/uprom_trans.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4UPROM_C0/RTG4UPROM_C0_0/UPROM_0_syn.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4UPROM_C0/RTG4UPROM_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4_uPROM/RTG4_uPROM.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology RTG4
set_option -part RT4G150
set_option -package CG1657
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip RTG4
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
