SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Sat Dec 19 20:53:31 2020
| Design | top |
| Family | RTG4 |
| Die | RT4G150 |
| Package | 1657 CG |
| Radiation Exposure | 0 |
| Temperature Range | -55 - 125 C |
| Voltage Range | 1.14 - 1.26 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST |
| Scenario for Timing Analysis | timing_analysis |
*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| RCOSC_50MHZ_0/CLKOUT | 20.000 | 50.000 | 10.653 | WORST |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 33.333 | 30.000 | 8.196 | WORST |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | N/A | N/A |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | 5.923 | 13.118 | 13.713 | 26.831 | 0.959 | 6.882 | WORST |
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PENABLE:EN | 5.434 | 13.573 | 13.224 | 26.797 | 0.959 | 6.427 | WORST |
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:APB_S_PSEL | 5.509 | 13.648 | 13.299 | 26.947 | 1.160 | 6.352 | WORST |
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[2]:D | 5.737 | 13.947 | 13.527 | 27.474 | 0.282 | 6.053 | WORST |
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/genblk3.PLL_ELOCK_APB_M_PADDR[2]:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:APB_S_PADDR[5] | 4.716 | 14.044 | 12.508 | 26.552 | 1.555 | 5.956 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | ||||||||
| data required time | 26.831 | |||||||
| data arrival time | - | 13.713 | ||||||
| slack | 13.118 | |||||||
| Data arrival time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | 0.000 | 0.000 | ||||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 1.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 2.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 4.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 5.729 | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.812 | 6.541 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | 7.102 | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.688 | 7.790 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:Q | cell | ADLIB:SLE_RT | + | 0.207 | 7.997 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PSEL_COREPLL_ELOCK_0_CCC_APB_PSEL_net | + | 0.707 | 8.704 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 9.122 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1_output_net | + | 0.248 | 9.370 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 9.788 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2_output_net | + | 0.255 | 10.043 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 10.461 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3_output_net | + | 0.251 | 10.712 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 11.130 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_1_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_psel_B_input_net | + | 0.346 | 11.476 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_1_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 11.546 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_1_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_1 | + | 0.098 | 11.644 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_1_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 11.714 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_pready_or_B_input_net | + | 0.223 | 11.937 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:Y | cell | ADLIB:CFG2 | + | 0.156 | 12.093 | 3 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PREADY_COREPLL_ELOCK_0_CCC_APB_PREADY_net | + | 0.540 | 12.633 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:Y | cell | ADLIB:CFG3 | + | 0.070 | 12.703 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/N_226_i | + | 1.010 | 13.713 | f | ||
| data arrival time | 13.713 | |||||||
| Data required time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 21.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 22.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 24.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 25.729 | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.812 | 26.541 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | 27.102 | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.688 | 27.790 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | Library setup time | ADLIB:SLE_RT | - | 0.959 | 26.831 | |||
| data required time | 26.831 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | 8.478 | 10.653 | 16.224 | 26.877 | 0.879 | 9.347 | -0.010 | WORST |
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[1]:ALn | 8.478 | 10.653 | 16.224 | 26.877 | 0.879 | 9.347 | -0.010 | WORST |
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[0]:ALn | 8.478 | 10.653 | 16.224 | 26.877 | 0.879 | 9.347 | -0.010 | WORST |
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_EN_F1:ALn | 8.478 | 10.653 | 16.224 | 26.877 | 0.879 | 9.347 | -0.010 | WORST |
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/ACTUAL_VCO_CONFIG_DONE:ALn | 8.476 | 10.653 | 16.222 | 26.875 | 0.879 | 9.347 | -0.008 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | ||||||||
| data required time | 26.877 | |||||||
| data arrival time | - | 16.224 | ||||||
| slack | 10.653 | |||||||
| Data arrival time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | 0.000 | 0.000 | ||||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 1.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 2.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 4.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 5.729 | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.793 | 6.522 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.561 | 7.083 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.663 | 7.746 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:Q | cell | ADLIB:SLE_RT | + | 0.201 | 7.947 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_Z | + | 4.429 | 12.376 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:Y | cell | ADLIB:GBR | + | 0.506 | 12.882 | 6 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset:A[1] | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst | + | 1.083 | 13.965 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset:Y | cell | ADLIB:RGRESET | + | 0.374 | 14.339 | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst_rgreset | + | 1.885 | 16.224 | r | ||
| data arrival time | 16.224 | |||||||
| Data required time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 21.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 22.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 24.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 25.729 | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.812 | 26.541 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | 27.102 | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.654 | 27.756 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | Library recovery time | ADLIB:SLE_RT | - | 0.879 | 26.877 | |||
| data required time | 26.877 | |||||||
| Operating Conditions | WORST |
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:CLK
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[8]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | 20.397 | 8.196 | 28.171 | 36.367 | 4.726 | 25.137 | WORST |
| Path 2 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[9]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | 20.370 | 8.223 | 28.144 | 36.367 | 4.726 | 25.110 | WORST |
| Path 3 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[7]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | 20.363 | 8.230 | 28.137 | 36.367 | 4.726 | 25.103 | WORST |
| Path 4 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[2]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | 20.358 | 8.238 | 28.129 | 36.367 | 4.726 | 25.095 | WORST |
| Path 5 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[5]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | 20.338 | 8.258 | 28.109 | 36.367 | 4.726 | 25.075 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[8]:CLK | ||||||||
| To: RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | ||||||||
| data required time | 36.367 | |||||||
| data arrival time | - | 28.171 | ||||||
| slack | 8.196 | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.770 | 2.770 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 4.798 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 5.668 | 8 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB5:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.856 | 6.524 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB5:YR | cell | ADLIB:RGB | + | 0.565 | 7.089 | 26 | r | |
| RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[8]:CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB5_rgbr_net_1 | + | 0.685 | 7.774 | r | ||
| RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[8]:Q | cell | ADLIB:SLE_RT | + | 0.207 | 7.981 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_7:B | net | RTG4_uPROM_0/COREUPROMIF_APB_C0_0_UPROM_ADDR[8] | + | 0.110 | 8.091 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_7:P | cell | ADLIB:ARI1_CC | + | 0.620 | 8.711 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_0_CC_1:P[1] | net | NET_CC_CONFIG387 | + | 0.000 | 8.711 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_0_CC_1:CC[7] | cell | ADLIB:CC_CONFIG | + | 0.731 | 9.442 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_12_FCINST1:CC | net | NET_CC_CONFIG407 | + | 0.000 | 9.442 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_12_FCINST1:CO | cell | ADLIB:FCEND_BUFF_CC | + | 0.096 | 9.538 | 2 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_2:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/CO3 | + | 0.500 | 10.038 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_2:P | cell | ADLIB:ARI1_CC | + | 0.497 | 10.535 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_0_CC_0:P[8] | net | NET_CC_CONFIG32 | + | 0.000 | 10.535 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_0_CC_0:CC[9] | cell | ADLIB:CC_CONFIG | + | 0.659 | 11.194 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_3:CC | net | NET_CC_CONFIG37 | + | 0.000 | 11.194 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_3:S | cell | ADLIB:ARI1_CC | + | 0.090 | 11.284 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_4:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_un47_sum_cry_3_S | + | 0.564 | 11.848 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_4:P | cell | ADLIB:ARI1_CC | + | 0.337 | 12.185 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_0_CC_0:P[8] | net | NET_CC_CONFIG14 | + | 0.000 | 12.185 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_0_CC_0:CC[11] | cell | ADLIB:CC_CONFIG | + | 0.725 | 12.910 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_s_7:CC | net | NET_CC_CONFIG25 | + | 0.000 | 12.910 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.090 | 13.000 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_6:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_9[4] | + | 0.777 | 13.777 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_6:P | cell | ADLIB:ARI1_CC | + | 0.337 | 14.114 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_0_CC_1:P[2] | net | NET_CC_CONFIG427 | + | 0.000 | 14.114 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_0_CC_1:CC[3] | cell | ADLIB:CC_CONFIG | + | 0.656 | 14.770 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_s_7:CC | net | NET_CC_CONFIG432 | + | 0.000 | 14.770 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.090 | 14.860 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_2:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_10[4] | + | 0.548 | 15.408 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_2:P | cell | ADLIB:ARI1_CC | + | 0.300 | 15.708 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_0_CC_1:P[1] | net | NET_CC_CONFIG219 | + | 0.000 | 15.708 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_0_CC_1:CC[6] | cell | ADLIB:CC_CONFIG | + | 0.638 | 16.346 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_s_7:CC | net | NET_CC_CONFIG236 | + | 0.000 | 16.346 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.112 | 16.458 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_11[4] | + | 0.593 | 17.051 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 17.351 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG262 | + | 0.000 | 17.351 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_0_CC_0:CC[10] | cell | ADLIB:CC_CONFIG | + | 0.720 | 18.071 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_4:CC | net | NET_CC_CONFIG273 | + | 0.000 | 18.071 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_4:S | cell | ADLIB:ARI1_CC | + | 0.127 | 18.198 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_5:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_un75_sum_cry_4_S | + | 0.540 | 18.738 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_5:P | cell | ADLIB:ARI1_CC | + | 0.350 | 19.088 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_0_CC_0:P[8] | net | NET_CC_CONFIG172 | + | 0.000 | 19.088 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_0_CC_0:CC[10] | cell | ADLIB:CC_CONFIG | + | 0.689 | 19.777 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_s_7:CC | net | NET_CC_CONFIG180 | + | 0.000 | 19.777 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.090 | 19.867 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_13[4] | + | 0.374 | 20.241 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 20.541 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_0_CC_0:P[1] | net | NET_CC_CONFIG286 | + | 0.000 | 20.541 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_0_CC_0:CC[7] | cell | ADLIB:CC_CONFIG | + | 0.731 | 21.272 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_s_7:CC | net | NET_CC_CONFIG306 | + | 0.000 | 21.272 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.112 | 21.384 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_3:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_14[4] | + | 0.584 | 21.968 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_3:P | cell | ADLIB:ARI1_CC | + | 0.300 | 22.268 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG50 | + | 0.000 | 22.268 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_0_CC_0:CC[11] | cell | ADLIB:CC_CONFIG | + | 0.756 | 23.024 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_s_7:CC | net | NET_CC_CONFIG64 | + | 0.000 | 23.024 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.090 | 23.114 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_15[4] | + | 0.360 | 23.474 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 23.774 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_0_CC_0:P[2] | net | NET_CC_CONFIG344 | + | 0.000 | 23.774 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_0_CC_0:CC[8] | cell | ADLIB:CC_CONFIG | + | 0.708 | 24.482 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_s_7:CC | net | NET_CC_CONFIG364 | + | 0.000 | 24.482 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.096 | 24.578 | 9 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_0_cry_1:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_16[4] | + | 0.613 | 25.191 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_0_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.350 | 25.541 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_0_cry_0_CC_0:P[7] | net | NET_CC_CONFIG311 | + | 0.000 | 25.541 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_0_cry_0_CC_0:CC[11] | cell | ADLIB:CC_CONFIG | + | 0.756 | 26.297 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_0_cry_5:CC | net | NET_CC_CONFIG325 | + | 0.000 | 26.297 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_0_cry_5:S | cell | ADLIB:ARI1_CC | + | 0.127 | 26.424 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m[8]:C | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_TRANS0[8] | + | 0.538 | 26.962 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m[8]:Y | cell | ADLIB:CFG3 | + | 0.156 | 27.118 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_1:C | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/ADDR_TRANS[8] | + | 0.695 | 27.813 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_1:IPC | cell | ADLIB:IP_INTERFACE | + | 0.000 | 27.813 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/ADDR_net[8] | + | 0.358 | 28.171 | f | ||
| data arrival time | 28.171 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | Clock Constraint | 33.333 | 33.333 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 33.333 | r | |||
| Clock generation | + | 2.770 | 36.103 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 38.131 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 39.001 | 8 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB7:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.857 | 39.858 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB7:YR | cell | ADLIB:RGB | + | 0.565 | 40.423 | 32 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_5:CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB7_rgbr_net_1 | + | 0.688 | 41.111 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_5:IPCLK | cell | ADLIB:IP_INTERFACE_C | + | 0.000 | 41.111 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:CLK | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/CLK_net | + | -0.018 | 41.093 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[8] | Library setup time | ADLIB:UPROM_IP | - | 4.726 | 36.367 | |||
| data required time | 36.367 | |||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | External Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | wdata_user[32] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[14] | 9.522 | 9.522 | 1.788 | 3.932 | WORST | ||
| Path 2 | wdata_user[31] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[13] | 9.586 | 9.586 | 1.684 | 3.892 | WORST | ||
| Path 3 | wdata_user[10] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:B_DIN[10] | 9.567 | 9.567 | 1.640 | 3.829 | WORST | ||
| Path 4 | raddr_user[6] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_ADDR[8] | 9.637 | 9.637 | 1.416 | 3.672 | WORST | ||
| Path 5 | wdata_user[12] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:B_DIN[12] | 9.447 | 9.447 | 1.569 | 3.638 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: wdata_user[32] | ||||||||
| To: RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[14] | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 9.522 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| wdata_user[32] | 0.000 | 0.000 | r | |||||
| wdata_user_ibuf[32]/U0/U_IOPAD:PAD | net | wdata_user[32] | + | 0.000 | 0.000 | r | ||
| wdata_user_ibuf[32]/U0/U_IOPAD:Y | cell | ADLIB:IOPAD_IN | + | 0.840 | 0.840 | 1 | r | |
| wdata_user_ibuf[32]/U0/U_IOINFF:A | net | wdata_user_ibuf[32]/U0/YIN1 | + | 0.087 | 0.927 | r | ||
| wdata_user_ibuf[32]/U0/U_IOINFF:Y | cell | ADLIB:IOINFF_BYPASS | + | 0.092 | 1.019 | 1 | r | |
| RAM_APB_BLK_0/mux_blk_0/wdata[32]:B | net | wdata_user_c[32] | + | 7.534 | 8.553 | r | ||
| RAM_APB_BLK_0/mux_blk_0/wdata[32]:Y | cell | ADLIB:CFG3 | + | 0.291 | 8.844 | 1 | r | |
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[14] | net | RAM_APB_BLK_0/mux_blk_0_wdata[32] | + | 0.678 | 9.522 | r | ||
| data arrival time | 9.522 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | N/C | N/C | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 2.631 | N/C | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 1.927 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.827 | N/C | 8 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.802 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.533 | N/C | 2 | r | |
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:B_CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.658 | N/C | r | ||
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[14] | Library setup time | ADLIB:RAM1K18_RT_IP | - | 1.788 | N/C | |||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | RD[32] | 14.067 | 21.836 | 21.836 | WORST | ||
| Path 2 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[32] | 13.012 | 20.781 | 20.781 | WORST | ||
| Path 3 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[9] | 12.592 | 20.361 | 20.361 | WORST | ||
| Path 4 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[27] | 12.241 | 20.010 | 20.010 | WORST | ||
| Path 5 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | RD[16] | 11.990 | 19.759 | 19.759 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | ||||||||
| To: RD[32] | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 21.836 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.770 | 2.770 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 4.798 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 5.668 | 8 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.844 | 6.512 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | 7.073 | 2 | r | |
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.696 | 7.769 | r | ||
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DOUT[14] | cell | ADLIB:RAM1K18_RT_IP | + | 5.360 | 13.129 | 2 | f | |
| RD_obuf[32]/U0/U_IOOUTFF:A | net | RD_c[32] | + | 6.336 | 19.465 | f | ||
| RD_obuf[32]/U0/U_IOOUTFF:Y | cell | ADLIB:IOOUTFF_BYPASS | + | 0.144 | 19.609 | 1 | f | |
| RD_obuf[32]/U0/U_IOPAD:D | net | RD_obuf[32]/U0/DOUT | + | 0.106 | 19.715 | f | ||
| RD_obuf[32]/U0/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.121 | 21.836 | 0 | f | |
| RD[32] | net | RD[32] | + | 0.000 | 21.836 | f | ||
| data arrival time | 21.836 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | N/C | N/C | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 2.770 | N/C | |||||
| RD[32] | N/C | f | ||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[24]:ALn | 12.670 | 19.757 | 20.415 | 40.172 | 0.879 | 13.576 | 0.027 | WORST |
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[1]:ALn | 12.670 | 19.757 | 20.415 | 40.172 | 0.879 | 13.576 | 0.027 | WORST |
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[15]:ALn | 12.670 | 19.757 | 20.415 | 40.172 | 0.879 | 13.576 | 0.027 | WORST |
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[13]:ALn | 12.670 | 19.757 | 20.415 | 40.172 | 0.879 | 13.576 | 0.027 | WORST |
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[10]:ALn | 12.670 | 19.757 | 20.415 | 40.172 | 0.879 | 13.576 | 0.027 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | ||||||||
| To: RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[24]:ALn | ||||||||
| data required time | 40.172 | |||||||
| data arrival time | - | 20.415 | ||||||
| slack | 19.757 | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.770 | 2.770 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 4.798 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 5.668 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_Y | + | 0.824 | 6.492 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.561 | 7.053 | 3 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | net | RTG4FCCCECALIB_C0_0_CCC_0_GL0 | + | 0.692 | 7.745 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:Q | cell | ADLIB:SLE_RT | + | 0.201 | 7.946 | 1 | r | |
| AND2_0:B | net | RTG4FCCCECALIB_C0_0_CCC_0_LOCK | + | 0.087 | 8.033 | r | ||
| AND2_0:Y | cell | ADLIB:CFG2 | + | 0.360 | 8.393 | 1 | r | |
| AND2_0_greset:A | net | AND2_0_Z_greset | + | 8.116 | 16.509 | r | ||
| AND2_0_greset:Y | cell | ADLIB:GRESET | + | 0.000 | 16.509 | 154 | r | |
| RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[24]:ALn | net | AND2_0_Z | + | 3.906 | 20.415 | r | ||
| data arrival time | 20.415 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | Clock Constraint | 33.333 | 33.333 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 33.333 | r | |||
| Clock generation | + | 2.770 | 36.103 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 38.131 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 39.001 | 8 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB4:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.855 | 39.856 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB4:YL | cell | ADLIB:RGB | + | 0.561 | 40.417 | 22 | r | |
| RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[24]:CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB4_rgbl_net_1 | + | 0.634 | 41.051 | r | ||
| RAM_APB_BLK_0/APB_master_wrp_0/mem_data_out[24]:ALn | Library recovery time | ADLIB:SLE_RT | - | 0.879 | 40.172 | |||
| data required time | 40.172 | |||||||
| Operating Conditions | WORST |
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | 5.923 | 10.997 | 0.959 | 6.882 | WORST | ||
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PENABLE:EN | 5.434 | 10.508 | 0.959 | 6.427 | WORST | ||
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:APB_S_PSEL | 5.509 | 10.583 | 1.160 | 6.352 | WORST | ||
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[2]:D | 5.737 | 10.811 | 0.282 | 6.053 | WORST | ||
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/genblk3.PLL_ELOCK_APB_M_PADDR[2]:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:APB_S_PADDR[5] | 4.716 | 9.792 | 1.555 | 5.956 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 10.997 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 2.143 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 3.013 | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.812 | 3.825 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | 4.386 | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.688 | 5.074 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:Q | cell | ADLIB:SLE_RT | + | 0.207 | 5.281 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PSEL_COREPLL_ELOCK_0_CCC_APB_PSEL_net | + | 0.707 | 5.988 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 6.406 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1_output_net | + | 0.248 | 6.654 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 7.072 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2_output_net | + | 0.255 | 7.327 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 7.745 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3_output_net | + | 0.251 | 7.996 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 8.414 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_1_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_psel_B_input_net | + | 0.346 | 8.760 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_1_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 8.830 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_1_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_1 | + | 0.098 | 8.928 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_1_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 8.998 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_pready_or_B_input_net | + | 0.223 | 9.221 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:Y | cell | ADLIB:CFG2 | + | 0.156 | 9.377 | 3 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PREADY_COREPLL_ELOCK_0_CCC_APB_PREADY_net | + | 0.540 | 9.917 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:Y | cell | ADLIB:CFG3 | + | 0.070 | 9.987 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/N_226_i | + | 1.010 | 10.997 | f | ||
| data arrival time | 10.997 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | N/C | N/C | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | N/C | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.812 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | N/C | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.688 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | Library setup time | ADLIB:SLE_RT | - | 0.959 | N/C | |||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | 8.478 | 13.508 | 0.879 | 9.347 | -0.010 | WORST | ||
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[1]:ALn | 8.478 | 13.508 | 0.879 | 9.347 | -0.010 | WORST | ||
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[0]:ALn | 8.478 | 13.508 | 0.879 | 9.347 | -0.010 | WORST | ||
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_EN_F1:ALn | 8.478 | 13.508 | 0.879 | 9.347 | -0.010 | WORST | ||
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/ACTUAL_VCO_CONFIG_DONE:ALn | 8.476 | 13.506 | 0.879 | 9.347 | -0.008 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 13.508 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 2.143 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 3.013 | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.793 | 3.806 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.561 | 4.367 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.663 | 5.030 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:Q | cell | ADLIB:SLE_RT | + | 0.201 | 5.231 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_Z | + | 4.429 | 9.660 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:Y | cell | ADLIB:GBR | + | 0.506 | 10.166 | 6 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset:A[1] | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst | + | 1.083 | 11.249 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset:Y | cell | ADLIB:RGRESET | + | 0.374 | 11.623 | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst_rgreset | + | 1.885 | 13.508 | r | ||
| data arrival time | 13.508 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | N/C | N/C | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | N/C | 5 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.812 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.561 | N/C | 23 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1 | + | 0.654 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/APB_WRITE_REG_COUNT[2]:ALn | Library recovery time | ADLIB:SLE_RT | - | 0.879 | N/C | |||
| Operating Conditions | WORST |
No Path
No Path
No Path
No Path