Global Net Report
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Sat Dec 19 20:50:50 2020
Global Nets Information
|
From |
GB Location |
Net Name |
Fanout |
| 1 |
GBR[8] |
(740, 153) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 |
214 |
| 2 |
GRESET |
(708, 155) |
AND2_0_Z |
154 |
| 3 |
GBR[7] |
(739, 153) |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset_Z |
57 |
| 4 |
GBL[23] |
(731, 154) |
RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y |
56 |
| 5 |
GBL[11] |
(731, 153) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst |
50 |
| 6 |
GBL[8] |
(728, 153) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_Y |
3 |
I/O to GB Connections
(none)
Fabric to GB Connections
|
From |
From Location |
To |
Net Name |
Net Type |
Fanout |
| 1 |
AND2_0:Y |
(90, 282) |
GRESET |
AND2_0_Z_greset |
ROUTED |
1 |
| 2 |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset:Q |
(1432, 10) |
GBR[7] |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset_0 |
ROUTED |
1 |
| 3 |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:Q |
(193, 253) |
GBL[11] |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_Z |
ROUTED |
1 |
CCC to GB Connections
|
From |
From Location |
Pin Swapped for Back Annotation Only |
To |
Net Name |
Net Type |
Fanout |
| 1 |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 |
CCC-NW0 (0, 311) |
None |
GBR[8] |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net |
HARDWIRED |
2 |
| 2 |
RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 |
CCC-SE0 (1524, 2) |
GL0 => GL3 |
GBL[23] |
RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net |
HARDWIRED |
1 |
| 3 |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 |
CCC-NW0 (0, 311) |
None |
GBL[8] |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net |
HARDWIRED |
2 |
CCC Input Connections
|
From |
From Location |
To (Pin Swapped for Back Annotation Only) |
CCC Location |
Net Name |
Net Type |
Fanout |
| 1 |
RCOSC_50MHZ_0:CLKOUT |
(1530, 2) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:RCOSC_50MHZ |
CCC-NW0 (0, 311) |
RCOSC_50MHZ_0_CLKOUT |
HARDWIRED |
2 |
| 2 |
RCOSC_50MHZ_0:CLKOUT |
(1530, 2) |
RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ |
CCC-SE0 (1524, 2) |
RCOSC_50MHZ_0_CLKOUT |
HARDWIRED |
2 |
Local Nets to RGB Connections
(none)
Local Reset Nets to RGRESET Connections
|
From |
From Location |
Net Name |
Fanout |
|
RGRESET Location |
Local Fanout |
| 1 |
SYSRESET_0:POWER_ON_RESET_N |
(1490, 2) |
SYSRESET_0_POWER_ON_RESET_N |
5 |
1 |
(362, 253) |
1 |
|
|
|
|
|
2 |
(362, 265) |
4 |
Global Reset Nets to RGRESET Connections
|
From |
From Location |
Net Name |
Fanout |
|
RGRESET Location |
Local Fanout |
| 1 |
GRESET |
(708, 155) |
AND2_0_Z |
154 |
1 |
(1166, 4) |
48 |
|
|
|
|
|
2 |
(1166, 10) |
44 |
|
|
|
|
|
3 |
(1166, 13) |
44 |
|
|
|
|
|
4 |
(1166, 16) |
6 |
|
|
|
|
|
5 |
(1166, 19) |
12 |
| 2 |
GBR[7] |
(739, 153) |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset_Z |
57 |
1 |
(1166, 1) |
31 |
|
|
|
|
|
2 |
(1166, 7) |
26 |
| 3 |
GBL[11] |
(731, 153) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst |
50 |
1 |
(362, 274) |
27 |
|
|
|
|
|
2 |
(362, 277) |
23 |
Global Nets to RGB Connections
|
From |
From Location |
Net Name |
Fanout |
|
RGB Location |
Local Fanout |
| 1 |
GBR[8] |
(740, 153) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 |
214 |
1 |
(1166, 3) |
48 |
|
|
|
|
|
2 |
(1166, 9) |
44 |
|
|
|
|
|
3 |
(1166, 12) |
44 |
|
|
|
|
|
4 |
(1166, 15) |
6 |
|
|
|
|
|
5 |
(1166, 18) |
12 |
|
|
|
|
|
6 |
(1166, 30) |
2 |
|
|
|
|
|
7 |
(1167, 0) |
32 |
|
|
|
|
|
8 |
(1167, 6) |
26 |
| 2 |
GBL[23] |
(731, 154) |
RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y |
56 |
1 |
(369, 252) |
1 |
|
|
|
|
|
2 |
(369, 264) |
4 |
|
|
|
|
|
3 |
(369, 273) |
27 |
|
|
|
|
|
4 |
(369, 276) |
23 |
|
|
|
|
|
5 |
(369, 309) |
1 |
| 3 |
GBL[8] |
(728, 153) |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_Y |
3 |
|
(362, 282) |
3 |
Warning: Local Clock and Reset Nets
The following clocks or resets are driven by fabric-generated or local nets and are not single event transient (SET) mitigated:
|
From |
From Location |
I/O Bank |
To |
To Location |
Net Name |
Fanout |
| 1 |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset:Q |
(1432, 10) |
- |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset_RNILE96:An |
GBR[7] |
RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_sync_reset_0 |
1 |
| 2 |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:Q |
(193, 253) |
- |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:An |
GBL[11] |
RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_Z |
1 |
Microchip recommends the use of dedicated global clocks with built-in single event transient (SET) mitigation.
The following local resets are not driven by three separate logic cones and are not radiation protected:
|
From |
From Location |
To |
Net Name |
Fanout |
| 1 |
SYSRESET_0:POWER_ON_RESET_N |
(1490, 2) |
RGRESET |
SYSRESET_0_POWER_ON_RESET_N |
5 |
For radiation protection, Microchip recommends that each of the three inputs of every RGRESET be driven by three separate logic cones replicating the paths from the source registers.