Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date      :  Sat Dec 19 20:48:10 2020
Project   :  C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project
Component :  RTG4FCCC_C0
Family    :  RTG4


HDL source files for all Synthesis and Simulation tools:
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCC_C0/RTG4FCCC_C0_0/RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCC/2.0.201/AutoReset_PLL.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCC/2.0.201/Hardened_Counter_Parameterized.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCC_C0/RTG4FCCC_C0.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCC/2.0.201/ccc_comps.v

