Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date      :  Sat Dec 19 20:48:18 2020
Project   :  C:\WFH_Tasks\RTG4_v12.6_Updates\AC454_SRAM_Verilog\Libero_Project
Component :  RTG4FCCCECALIB_C0
Family    :  RTG4


HDL source files for all Synthesis and Simulation tools:
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCCECALIB_C0/RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_RTG4FCCCECALIB_C0_0_RTG4FCCCECALIB.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CorePLL_ELOCK.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CorePLL_ELOCK_Ctrl_Fsm.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CorePLL_ELOCK_Reset_Ctrl.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/CCCAPBIF.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/mux2.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/mux2to1_eight_bit.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/mux2to1_seven_bit.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/work/RTG4FCCCECALIB_C0/RTG4FCCCECALIB_C0.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    C:/WFH_Tasks/RTG4_v12.6_Updates/AC454_SRAM_Verilog/Libero_Project/component/Actel/SgCore/RTG4FCCCECALIB/2.1.010/ccc_comps.v

