| Project Settings |
|---|
| Project Name | top_syn | Device Name | synthesis: Microchip RTG4 : RT4G150 |
| Implementation Name | synthesis | Top Module | top |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 10000 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
118 |
63 |
0 |
- |
00m:21s |
- |
17-12-2020
11:03:15 |
| (premap) | Complete |
7 |
4 |
0 |
0m:04s |
0m:04s |
189MB |
17-12-2020
11:03:23 |
| (fpga_mapper) | Complete |
19 |
7 |
0 |
0m:13s |
0m:15s |
193MB |
17-12-2020
11:03:39 |
| Multi-srs Generator |
Complete | | | | | | | 17-12-2020
11:03:17 |
| Area Summary |
|---|
| |
| Carry Cells | 156 |
Sequential Cells | 266 |
| DSP Blocks
(dsp_used) | 0 |
I/O Cells | 128 |
| Global Clock Buffers | 5 |
RAM1K18_RT
(v_ram) | 1 |
| LUTs
(total_luts) | 325 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| RCOSC_50MHZ_0/CLKOUT | 50.0 MHz | NA | NA |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 30.0 MHz | 39.4 MHz | 7.926 |
| RTG4FCCC_C0_RTG4FCCC_C0_0_RTG4FCCC|GL0_net_inferred_clock | 100.0 MHz | 105.4 MHz | 0.513 |
| System | 100.0 MHz | 226.4 MHz | 5.584 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 2 |
| |
|