@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF236 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\component\actel\sgcore\rtg4uprom\2.1.100\uprom_trans.v":6:39:6:54|Generating a type div divider 
@N: MO231 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\hdl\apb_master_wrp.vhd":100:6:100:7|Found counter in view:work.work_apb_master_wrp_trans_32_16_1_DATA_WIDTHADDR_WIDTH(trans) instance PADDR_xhdl0[15:2] 
@N: MO231 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\hdl\apb_master_wrp.vhd":100:6:100:7|Found counter in view:work.work_apb_master_wrp_trans_32_16_1_DATA_WIDTHADDR_WIDTH(trans) instance waddr_int[8:0] 
@N: MO231 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\hdl\apb_master_wrp.vhd":207:6:207:7|Found counter in view:work.work_apb_master_wrp_trans_32_16_1_DATA_WIDTHADDR_WIDTH(trans) instance raddr_int[6:0] 
@N: MO231 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\component\actel\sgcore\rtg4fcccecalib\2.1.010\corepll_elock_ctrl_fsm.v":610:0:610:5|Found counter in view:work.ACT_UNIQUE_CorePLL_ELOCK_Ctrl_Fsm_Z3_layer0(verilog) instance DELAY_CNTR[13:0] 
@N: MO225 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\component\actel\directcore\coreupromif_apb\3.0.102\rtl\vlog\core\coreupromif_apb.v":409:0:409:5|There are no possible illegal states for state machine UCLK_currState[3:0] (in view: work.COREUPROMIF_APB_Z2_layer0(verilog)); safe FSM implementation is not required.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\ac454_sram_vhdl\libero_project\hdl\apb_master_wrp.vhd":100:6:100:7|Removing sequential instance RAM_APB_BLK_0.APB_master_wrp_0.PENABLE (in view: work.top(verilog)) because it does not drive other instances.
@N: FP130 |Promoting Net AND2_0_Y on CLKINT  I_179 
@N: FP130 |Promoting Net RTG4_uPROM_0.COREUPROMIF_APB_C0_0.COREUPROMIF_APB_C0_0.UCLK_sync_reset on CLKINT  I_180 
@N: FP130 |Promoting Net RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.COREPLL_ELOCK_0.ARST_N_arst on CLKINT  I_181 
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock RCOSC_50MHZ_0/CLKOUT with period 20.00ns 
@N: MT615 |Found clock RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 with period 33.33ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
