SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Thu Dec 17 11:10:13 2020
| Design | top |
| Family | RTG4 |
| Die | RT4G150 |
| Package | 1657 CG |
| Radiation Exposure | 0 |
| Temperature Range | -55 - 125 C |
| Voltage Range | 1.14 - 1.26 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST |
| Scenario for Timing Analysis | timing_analysis |
*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| RCOSC_50MHZ_0/CLKOUT | 20.000 | 50.000 | 11.797 | WORST |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 33.333 | 30.000 | 8.330 | WORST |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | N/A | N/A |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | 6.418 | 12.623 | 14.223 | 26.846 | 0.959 | 7.377 | WORST |
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PENABLE:EN | 6.187 | 12.819 | 13.992 | 26.811 | 0.959 | 7.181 | WORST |
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:APB_S_PSEL | 5.601 | 13.541 | 13.406 | 26.947 | 1.160 | 6.459 | WORST |
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[3]:D | 5.889 | 13.647 | 13.694 | 27.341 | 0.429 | 6.353 | WORST |
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[2]:D | 5.884 | 13.799 | 13.689 | 27.488 | 0.282 | 6.201 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | ||||||||
| data required time | 26.846 | |||||||
| data arrival time | - | 14.223 | ||||||
| slack | 12.623 | |||||||
| Data arrival time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | 0.000 | 0.000 | ||||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 1.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 2.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 4.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 5.729 | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.815 | 6.544 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.561 | 7.105 | 20 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.700 | 7.805 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:Q | cell | ADLIB:SLE_RT | + | 0.207 | 8.012 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PSEL_COREPLL_ELOCK_0_CCC_APB_PSEL_net | + | 0.812 | 8.824 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 9.242 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1_output_net | + | 0.268 | 9.510 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 9.928 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2_output_net | + | 0.260 | 10.188 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 10.606 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3_output_net | + | 0.255 | 10.861 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 11.279 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_0_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_psel_B_input_net | + | 0.564 | 11.843 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_0_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 11.913 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_0_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PSEL_CCC_0_CCC_INST_0_APB_S_PSEL_net | + | 0.220 | 12.133 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_0_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 12.203 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_pready_or_A_input_net | + | 0.221 | 12.424 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:Y | cell | ADLIB:CFG2 | + | 0.156 | 12.580 | 3 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PREADY_COREPLL_ELOCK_0_CCC_APB_PREADY_net | + | 0.638 | 13.218 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:Y | cell | ADLIB:CFG3 | + | 0.070 | 13.288 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/N_226_i | + | 0.935 | 14.223 | f | ||
| data arrival time | 14.223 | |||||||
| Data required time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 21.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 22.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 24.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 25.729 | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.815 | 26.544 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.561 | 27.105 | 20 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.700 | 27.805 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | Library setup time | ADLIB:SLE_RT | - | 0.959 | 26.846 | |||
| data required time | 26.846 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | 7.286 | 11.797 | 15.096 | 26.893 | 0.879 | 8.203 | 0.038 | WORST |
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[7]:ALn | 7.286 | 11.797 | 15.096 | 26.893 | 0.879 | 8.203 | 0.038 | WORST |
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[5]:ALn | 7.286 | 11.797 | 15.096 | 26.893 | 0.879 | 8.203 | 0.038 | WORST |
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/CCC_CNT[0]:ALn | 7.286 | 11.797 | 15.096 | 26.893 | 0.879 | 8.203 | 0.038 | WORST |
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/ACTUAL_VCO_CONFIG_DONE:ALn | 7.286 | 11.797 | 15.096 | 26.893 | 0.879 | 8.203 | 0.038 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | ||||||||
| data required time | 26.893 | |||||||
| data arrival time | - | 15.096 | ||||||
| slack | 11.797 | |||||||
| Data arrival time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | 0.000 | 0.000 | ||||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 1.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 2.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 4.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 5.729 | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB5:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.828 | 6.557 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB5:YL | cell | ADLIB:RGB | + | 0.561 | 7.118 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB5_rgbl_net_1 | + | 0.692 | 7.810 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:Q | cell | ADLIB:SLE_RT | + | 0.201 | 8.011 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_Z | + | 3.231 | 11.242 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:Y | cell | ADLIB:GBR | + | 0.506 | 11.748 | 12 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset_1:A[1] | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst | + | 1.089 | 12.837 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset_1:Y | cell | ADLIB:RGRESET | + | 0.374 | 13.211 | 9 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6/U0_rgreset_1_rgreset_net_1 | + | 1.885 | 15.096 | r | ||
| data arrival time | 15.096 | |||||||
| Data required time calculation | ||||||||
| RCOSC_50MHZ_0/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| RCOSC_50MHZ_0:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:RCOSC_50MHZ | net | RCOSC_50MHZ_0_CLKOUT | + | 1.291 | 21.291 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | cell | ADLIB:CCC_IP | + | 1.425 | 22.716 | 1 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 24.859 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 25.729 | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB1:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.819 | 26.548 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB1:YL | cell | ADLIB:RGB | + | 0.561 | 27.109 | 9 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 | + | 0.663 | 27.772 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | Library recovery time | ADLIB:SLE_RT | - | 0.879 | 26.893 | |||
| data required time | 26.893 | |||||||
| Operating Conditions | WORST |
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:CLK
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[11]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[5] | 20.248 | 8.330 | 28.031 | 36.361 | 4.734 | 25.003 | WORST |
| Path 2 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[5]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[5] | 20.248 | 8.333 | 28.028 | 36.361 | 4.734 | 25.000 | WORST |
| Path 3 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[11]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[10] | 20.250 | 8.335 | 28.033 | 36.368 | 4.727 | 24.998 | WORST |
| Path 4 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[5]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[10] | 20.250 | 8.338 | 28.030 | 36.368 | 4.727 | 24.995 | WORST |
| Path 5 | RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[12]:CLK | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[5] | 20.220 | 8.358 | 28.003 | 36.361 | 4.734 | 24.975 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[11]:CLK | ||||||||
| To: RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[5] | ||||||||
| data required time | 36.361 | |||||||
| data arrival time | - | 28.031 | ||||||
| slack | 8.330 | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.770 | 2.770 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 4.798 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 5.668 | 11 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB6:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.853 | 6.521 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB6:YR | cell | ADLIB:RGB | + | 0.565 | 7.086 | 21 | r | |
| RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[11]:CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB6_rgbr_net_1 | + | 0.697 | 7.783 | r | ||
| RTG4_uPROM_0/COREUPROMIF_APB_C0_0/COREUPROMIF_APB_C0_0/UCLK_UPROM_ADDR_1[11]:Q | cell | ADLIB:SLE_RT | + | 0.207 | 7.990 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_10:B | net | RTG4_uPROM_0/COREUPROMIF_APB_C0_0_UPROM_ADDR[11] | + | 0.110 | 8.100 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_10:P | cell | ADLIB:ARI1_CC | + | 0.620 | 8.720 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_0_CC_1:P[1] | net | NET_CC_CONFIG351 | + | 0.000 | 8.720 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_0_CC_1:CC[3] | cell | ADLIB:CC_CONFIG | + | 0.688 | 9.408 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_12:CC | net | NET_CC_CONFIG359 | + | 0.000 | 9.408 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30_cry_12:S | cell | ADLIB:ARI1_CC | + | 0.127 | 9.535 | 5 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_1:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_IN_P30[13] | + | 0.324 | 9.859 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.497 | 10.356 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_0_CC_0:P[11] | net | NET_CC_CONFIG31 | + | 0.000 | 10.356 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_0_CC_0:CO | cell | ADLIB:CC_CONFIG | + | 0.309 | 10.665 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_0_CC_1:CI | net | CI_TO_CO27 | + | 0.000 | 10.665 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_0_CC_1:CC[2] | cell | ADLIB:CC_CONFIG | + | 0.218 | 10.883 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_3_FCINST1:CC | net | NET_CC_CONFIG42 | + | 0.000 | 10.883 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un47_sum_cry_3_FCINST1:CO | cell | ADLIB:FCEND_BUFF_CC | + | 0.096 | 10.979 | 3 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_5:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_un47_sum_cry_3 | + | 0.639 | 11.618 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_5:P | cell | ADLIB:ARI1_CC | + | 0.350 | 11.968 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_0_CC_1:P[2] | net | NET_CC_CONFIG18 | + | 0.000 | 11.968 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_cry_0_CC_1:CC[4] | cell | ADLIB:CC_CONFIG | + | 0.686 | 12.654 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_s_7:CC | net | NET_CC_CONFIG26 | + | 0.000 | 12.654 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un54_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.090 | 12.744 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_9[4] | + | 0.518 | 13.262 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 13.562 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG413 | + | 0.000 | 13.562 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_0_CC_0:CO | cell | ADLIB:CC_CONFIG | + | 0.505 | 14.067 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_0_CC_1:CI | net | CI_TO_CO409 | + | 0.000 | 14.067 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_cry_0_CC_1:CC[1] | cell | ADLIB:CC_CONFIG | + | 0.210 | 14.277 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_s_7:CC | net | NET_CC_CONFIG433 | + | 0.000 | 14.277 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un61_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.112 | 14.389 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_10[4] | + | 0.586 | 14.975 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 15.275 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_0_CC_0:P[1] | net | NET_CC_CONFIG171 | + | 0.000 | 15.275 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_0_CC_0:CC[4] | cell | ADLIB:CC_CONFIG | + | 0.718 | 15.993 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_4:CC | net | NET_CC_CONFIG182 | + | 0.000 | 15.993 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un68_sum_cry_4:S | cell | ADLIB:ARI1_CC | + | 0.127 | 16.120 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_5:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_un68_sum_cry_4_S | + | 0.523 | 16.643 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_5:P | cell | ADLIB:ARI1_CC | + | 0.350 | 16.993 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_0_CC_0:P[5] | net | NET_CC_CONFIG228 | + | 0.000 | 16.993 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_cry_0_CC_0:CC[7] | cell | ADLIB:CC_CONFIG | + | 0.537 | 17.530 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_s_7:CC | net | NET_CC_CONFIG236 | + | 0.000 | 17.530 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un75_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.112 | 17.642 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_3:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_12[4] | + | 0.357 | 17.999 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_3:P | cell | ADLIB:ARI1_CC | + | 0.300 | 18.299 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG123 | + | 0.000 | 18.299 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_cry_0_CC_0:CC[11] | cell | ADLIB:CC_CONFIG | + | 0.756 | 19.055 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_s_7:CC | net | NET_CC_CONFIG137 | + | 0.000 | 19.055 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un82_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.090 | 19.145 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_13[4] | + | 0.568 | 19.713 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 20.013 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG241 | + | 0.000 | 20.013 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_0_CC_0:CO | cell | ADLIB:CC_CONFIG | + | 0.505 | 20.518 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_0_CC_1:CI | net | CI_TO_CO237 | + | 0.000 | 20.518 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_cry_0_CC_1:CC[1] | cell | ADLIB:CC_CONFIG | + | 0.210 | 20.728 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_s_7:CC | net | NET_CC_CONFIG261 | + | 0.000 | 20.728 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un89_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.112 | 20.840 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_14[4] | + | 0.571 | 21.411 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 21.711 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG47 | + | 0.000 | 21.711 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_0_CC_0:CO | cell | ADLIB:CC_CONFIG | + | 0.505 | 22.216 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_0_CC_1:CI | net | CI_TO_CO43 | + | 0.000 | 22.216 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_cry_0_CC_1:CC[1] | cell | ADLIB:CC_CONFIG | + | 0.210 | 22.426 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_s_7:CC | net | NET_CC_CONFIG67 | + | 0.000 | 22.426 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un96_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.112 | 22.538 | 9 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_1:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_15[4] | + | 0.563 | 23.101 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_1:P | cell | ADLIB:ARI1_CC | + | 0.300 | 23.401 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_0_CC_0:P[7] | net | NET_CC_CONFIG299 | + | 0.000 | 23.401 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_0_CC_0:CO | cell | ADLIB:CC_CONFIG | + | 0.505 | 23.906 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_0_CC_1:CI | net | CI_TO_CO295 | + | 0.000 | 23.906 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_cry_0_CC_1:CC[1] | cell | ADLIB:CC_CONFIG | + | 0.210 | 24.116 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_s_7:CC | net | NET_CC_CONFIG319 | + | 0.000 | 24.116 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/un5_ADDR_OUT.if_generate_plus.mult1_un103_sum_s_7:S | cell | ADLIB:ARI1_CC | + | 0.096 | 24.212 | 9 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_4:B | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/mult1_temp_b_16[4] | + | 0.723 | 24.935 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_4:P | cell | ADLIB:ARI1_CC | + | 0.350 | 25.285 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_4_CC_0:P[2] | net | NET_CC_CONFIG138 | + | 0.000 | 25.285 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_4_CC_0:CC[3] | cell | ADLIB:CC_CONFIG | + | 0.656 | 25.941 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_5:CC | net | NET_CC_CONFIG143 | + | 0.000 | 25.941 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_5:S | cell | ADLIB:ARI1_CC | + | 0.127 | 26.068 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m[5]:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m_0_cry_5_S | + | 0.337 | 26.405 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/RTG4UPROM_ADDR_TRANS_0/ADDR_OUT_m[5]:Y | cell | ADLIB:CFG3 | + | 0.299 | 26.704 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_12:A | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/ADDR_TRANS[5] | + | 0.972 | 27.676 | f | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_12:IPA | cell | ADLIB:IP_INTERFACE | + | 0.000 | 27.676 | 1 | f | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[5] | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/ADDR_net[5] | + | 0.355 | 28.031 | f | ||
| data arrival time | 28.031 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | Clock Constraint | 33.333 | 33.333 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 33.333 | r | |||
| Clock generation | + | 2.770 | 36.103 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 38.131 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 39.001 | 11 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB10:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.857 | 39.858 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB10:YR | cell | ADLIB:RGB | + | 0.565 | 40.423 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_5:CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB10_rgbr_net_1 | + | 0.690 | 41.113 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/IP_INTERFACE_5:IPCLK | cell | ADLIB:IP_INTERFACE_C | + | 0.000 | 41.113 | 1 | r | |
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:CLK | net | RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/CLK_net | + | -0.018 | 41.095 | r | ||
| RTG4_uPROM_0/RTG4UPROM_C0_0/RTG4UPROM_C0_0/UPROM_0/INST_UPROM_IP:ADDR[5] | Library setup time | ADLIB:UPROM_IP | - | 4.734 | 36.361 | |||
| data required time | 36.361 | |||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | External Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | wdata_user[18] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[0] | 7.110 | 7.110 | 1.846 | 1.572 | WORST | ||
| Path 2 | wdata_user[8] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:B_DIN[8] | 6.947 | 6.947 | 1.555 | 1.118 | WORST | ||
| Path 3 | wdata_user[1] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:B_DIN[1] | 6.767 | 6.767 | 1.639 | 1.022 | WORST | ||
| Path 4 | raddr_user[6] | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_ADDR[8] | 6.749 | 6.749 | 1.416 | 0.785 | WORST | ||
| Path 5 | rd_enable_user | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_REN | 6.736 | 6.736 | 1.325 | 0.681 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: wdata_user[18] | ||||||||
| To: RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[0] | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 7.110 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| wdata_user[18] | 0.000 | 0.000 | r | |||||
| wdata_user_ibuf[18]/U0/U_IOPAD:PAD | net | wdata_user[18] | + | 0.000 | 0.000 | r | ||
| wdata_user_ibuf[18]/U0/U_IOPAD:Y | cell | ADLIB:IOPAD_IN | + | 0.840 | 0.840 | 1 | r | |
| wdata_user_ibuf[18]/U0/U_IOINFF:A | net | wdata_user_ibuf[18]/U0/YIN1 | + | 0.146 | 0.986 | r | ||
| wdata_user_ibuf[18]/U0/U_IOINFF:Y | cell | ADLIB:IOINFF_BYPASS | + | 0.092 | 1.078 | 1 | r | |
| RAM_APB_BLK_0/mux_blk_0/wdata[18]:B | net | wdata_user_c[18] | + | 5.044 | 6.122 | r | ||
| RAM_APB_BLK_0/mux_blk_0/wdata[18]:Y | cell | ADLIB:CFG3 | + | 0.136 | 6.258 | 1 | r | |
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[0] | net | RAM_APB_BLK_0/mux_blk_0_wdata[18] | + | 0.852 | 7.110 | r | ||
| data arrival time | 7.110 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | N/C | N/C | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 2.631 | N/C | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 1.927 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.827 | N/C | 11 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB2:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.802 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB2:YR | cell | ADLIB:RGB | + | 0.537 | N/C | 14 | r | |
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:B_CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB2_rgbr_net_1 | + | 0.660 | N/C | r | ||
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DIN[0] | Library setup time | ADLIB:RAM1K18_RT_IP | - | 1.846 | N/C | |||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[23] | 12.907 | 20.674 | 20.674 | WORST | ||
| Path 2 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[9] | 11.768 | 19.535 | 19.535 | WORST | ||
| Path 3 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | RD[14] | 11.560 | 19.327 | 19.327 | WORST | ||
| Path 4 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[14] | 11.501 | 19.268 | 19.268 | WORST | ||
| Path 5 | RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | rdata_user[12] | 11.432 | 19.199 | 19.199 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | ||||||||
| To: rdata_user[23] | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 20.674 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.770 | 2.770 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 4.798 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 5.668 | 11 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB2:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.844 | 6.512 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB2:YR | cell | ADLIB:RGB | + | 0.565 | 7.077 | 14 | r | |
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB2_rgbr_net_1 | + | 0.690 | 7.767 | r | ||
| RAM_APB_BLK_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_0/RTG4TPSRAM_C0_RTG4TPSRAM_C0_0_RTG4TPSRAM_R0C0/INST_RAM1K18_RT_IP:A_DOUT[5] | cell | ADLIB:RAM1K18_RT_IP | + | 5.277 | 13.044 | 2 | f | |
| rdata_user_obuf[23]/U0/U_IOOUTFF:A | net | RD_c[23] | + | 4.144 | 17.188 | f | ||
| rdata_user_obuf[23]/U0/U_IOOUTFF:Y | cell | ADLIB:IOOUTFF_BYPASS | + | 0.144 | 17.332 | 1 | f | |
| rdata_user_obuf[23]/U0/U_IOPAD:D | net | rdata_user_obuf[23]/U0/DOUT | + | 0.115 | 17.447 | f | ||
| rdata_user_obuf[23]/U0/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 3.227 | 20.674 | 0 | f | |
| rdata_user[23] | net | rdata_user[23] | + | 0.000 | 20.674 | f | ||
| data arrival time | 20.674 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | N/C | N/C | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 2.770 | N/C | |||||
| rdata_user[23] | N/C | f | ||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[6]:ALn | 13.038 | 19.393 | 20.797 | 40.190 | 0.879 | 13.940 | 0.023 | WORST |
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[4]:ALn | 13.038 | 19.393 | 20.797 | 40.190 | 0.879 | 13.940 | 0.023 | WORST |
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[3]:ALn | 13.038 | 19.393 | 20.797 | 40.190 | 0.879 | 13.940 | 0.023 | WORST |
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[2]:ALn | 13.038 | 19.393 | 20.797 | 40.190 | 0.879 | 13.940 | 0.023 | WORST |
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[0]:ALn | 13.038 | 19.393 | 20.797 | 40.190 | 0.879 | 13.940 | 0.023 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | ||||||||
| To: RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[6]:ALn | ||||||||
| data required time | 40.190 | |||||||
| data arrival time | - | 20.797 | ||||||
| slack | 19.393 | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.770 | 2.770 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 4.798 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 5.668 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_Y | + | 0.829 | 6.497 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.561 | 7.058 | 3 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:CLK | net | RTG4FCCCECALIB_C0_0_CCC_0_GL0 | + | 0.701 | 7.759 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_DFN1_2:Q | cell | ADLIB:SLE_RT | + | 0.201 | 7.960 | 1 | r | |
| AND2_0:B | net | RTG4FCCCECALIB_C0_0_CCC_0_LOCK | + | 0.084 | 8.044 | r | ||
| AND2_0:Y | cell | ADLIB:CFG2 | + | 0.360 | 8.404 | 1 | r | |
| AND2_0_greset:A | net | AND2_0_Z_greset | + | 8.487 | 16.891 | r | ||
| AND2_0_greset:Y | cell | ADLIB:GRESET | + | 0.000 | 16.891 | 154 | r | |
| RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[6]:ALn | net | AND2_0_Z | + | 3.906 | 20.797 | r | ||
| data arrival time | 20.797 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/GL0 | Clock Constraint | 33.333 | 33.333 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:GL0 | Clock source | + | 0.000 | 33.333 | r | |||
| Clock generation | + | 2.770 | 36.103 | |||||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/A_GL0_CCC_0_GL0_INST_CCC_INST_0_net | + | 2.028 | 38.131 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_GB0:Y | cell | ADLIB:GBR | + | 0.870 | 39.001 | 11 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB1:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_gbs_1 | + | 0.841 | 39.842 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB1:YR | cell | ADLIB:RGB | + | 0.565 | 40.407 | 24 | r | |
| RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[6]:CLK | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_0_GL0_INST/U0_RGB1_RGB1_rgbr_net_1 | + | 0.662 | 41.069 | r | ||
| RAM_APB_BLK_0/APB_master_wrp_0/raddr_1[6]:ALn | Library recovery time | ADLIB:SLE_RT | - | 0.879 | 40.190 | |||
| data required time | 40.190 | |||||||
| Operating Conditions | WORST |
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | 6.418 | 11.507 | 0.959 | 7.377 | WORST | ||
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PENABLE:EN | 6.187 | 11.276 | 0.959 | 7.181 | WORST | ||
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_INST_0/INST_CCCDYN_IP:APB_S_PSEL | 5.601 | 10.690 | 1.160 | 6.459 | WORST | ||
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[3]:D | 5.889 | 10.978 | 0.429 | 6.353 | WORST | ||
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[2]:D | 5.884 | 10.973 | 0.282 | 6.201 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 11.507 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 2.143 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 3.013 | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.815 | 3.828 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.561 | 4.389 | 20 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.700 | 5.089 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:Q | cell | ADLIB:SLE_RT | + | 0.207 | 5.296 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PSEL_COREPLL_ELOCK_0_CCC_APB_PSEL_net | + | 0.812 | 6.108 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 6.526 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_1_output_net | + | 0.268 | 6.794 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 7.212 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_2_output_net | + | 0.260 | 7.472 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 7.890 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_3_output_net | + | 0.255 | 8.145 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_BUFD_4:Y | cell | ADLIB:CFG1D_TEST | + | 0.418 | 8.563 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_0_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_psel_B_input_net | + | 0.564 | 9.127 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PSEL_CCC_0_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 9.197 | 2 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_0_Instance:B | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PSEL_CCC_0_CCC_INST_0_APB_S_PSEL_net | + | 0.220 | 9.417 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_CCC_0_Instance:Y | cell | ADLIB:CFG2 | + | 0.070 | 9.487 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/apb_s_pready_or_A_input_net | + | 0.221 | 9.708 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST/APB_S_PREADY_OR_Instance:Y | cell | ADLIB:CFG2 | + | 0.156 | 9.864 | 3 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:A | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/CCC_APB_INST_APB_S_PREADY_COREPLL_ELOCK_0_CCC_APB_PREADY_net | + | 0.638 | 10.502 | f | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL_RNO:Y | cell | ADLIB:CFG3 | + | 0.070 | 10.572 | 1 | f | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/N_226_i | + | 0.935 | 11.507 | f | ||
| data arrival time | 11.507 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | N/C | N/C | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | N/C | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.815 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.561 | N/C | 20 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.700 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_APB_M_PSEL:EN | Library setup time | ADLIB:SLE_RT | - | 0.959 | N/C | |||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | 7.286 | 12.380 | 0.879 | 8.203 | 0.038 | WORST | ||
| Path 2 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[7]:ALn | 7.286 | 12.380 | 0.879 | 8.203 | 0.038 | WORST | ||
| Path 3 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[5]:ALn | 7.286 | 12.380 | 0.879 | 8.203 | 0.038 | WORST | ||
| Path 4 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/CCC_CNT[0]:ALn | 7.286 | 12.380 | 0.879 | 8.203 | 0.038 | WORST | ||
| Path 5 | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/ACTUAL_VCO_CONFIG_DONE:ALn | 7.286 | 12.380 | 0.879 | 8.203 | 0.038 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | ||||||||
| To: RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 12.380 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | 0.000 | 0.000 | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | 2.143 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | 3.013 | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB5:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.828 | 3.841 | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB5:YL | cell | ADLIB:RGB | + | 0.561 | 4.402 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB5_rgbl_net_1 | + | 0.692 | 5.094 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep:Q | cell | ADLIB:SLE_RT | + | 0.201 | 5.295 | 1 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:An | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_Z | + | 3.231 | 8.526 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6:Y | cell | ADLIB:GBR | + | 0.506 | 9.032 | 12 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset_1:A[1] | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/ARST_N_arst | + | 1.089 | 10.121 | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6_rgreset_1:Y | cell | ADLIB:RGRESET | + | 0.374 | 10.495 | 9 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | net | RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Reset_Ctrl_Inst/ARST_N_rep_RNI5HI6/U0_rgreset_1_rgreset_net_1 | + | 1.885 | 12.380 | r | ||
| data arrival time | 12.380 | |||||||
| Data required time calculation | ||||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | N/C | N/C | ||||||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_net | + | 2.143 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST:Y | cell | ADLIB:GBR | + | 0.870 | N/C | 7 | r | |
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB1:An | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_Y | + | 0.819 | N/C | r | ||
| RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB1:YL | cell | ADLIB:RGB | + | 0.561 | N/C | 9 | r | |
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:CLK | net | RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 | + | 0.663 | N/C | r | ||
| RTG4FCCCECALIB_C0_0/RTG4FCCCECALIB_C0_0/COREPLL_ELOCK_0/CorePLL_ELOCK_Ctrl_Fsm_Inst/PLL_ELOCK_CS[8]:ALn | Library recovery time | ADLIB:SLE_RT | - | 0.879 | N/C | |||
| Operating Conditions | WORST |
No Path
No Path
No Path
No Path