#Build: Synplify Pro J-2015.03M-3, Build 048R, May 14 2015 #install: \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3 #OS: Windows 7 6.1 #Hostname: W764-CHAKRAVART #Implementation: synthesis Synopsys HDL Compiler, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\smartfusion2.v" @I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\hypermods.v" @I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\umr_capim.v" @I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\scemi_objects.v" @I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\scemi_pipes.svh" @I::"F:\Linting\cam_vita2k\hdl\Deserializer.v" @I::"F:\Linting\cam_vita2k\hdl\LVDS_RX_TOP.v" @I::"F:\Linting\cam_vita2k\hdl\RX_TOP.v" @I::"F:\Linting\cam_vita2k\hdl\vita_ramDualPort.v" @I::"F:\Linting\cam_vita2k\hdl\vita_data_decoder.v" @I::"F:\Linting\cam_vita2k\component\work\vita_reciever\FCCC_0\vita_reciever_FCCC_0_FCCC.v" @I::"F:\Linting\cam_vita2k\component\work\vita_reciever\vita_reciever.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module vita_reciever @N:CG364 : smartfusion2.v(542) | Synthesizing module DDR_IN @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : vita_reciever_FCCC_0_FCCC.v(5) | Synthesizing module vita_reciever_FCCC_0_FCCC @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF @N:CG364 : Deserializer.v(22) | Synthesizing module Deserializer @N:CG179 : Deserializer.v(301) | Removing redundant assignment @W:CG133 : Deserializer.v(64) | No assignment to input_rising_reg @W:CG133 : Deserializer.v(65) | No assignment to input_falling_reg @W:CG133 : Deserializer.v(66) | No assignment to input_rising_reg1 @W:CG133 : Deserializer.v(67) | No assignment to input_falling_reg1 @W:CG133 : Deserializer.v(70) | No assignment to input_rising_reg3 @W:CG133 : Deserializer.v(71) | No assignment to input_falling_reg3 @W:CL169 : Deserializer.v(91) | Pruning register input_falling_reg2 @W:CL265 : Deserializer.v(91) | Pruning bit 0 of Align_data_d2[10:0] -- not in use ... @N:CG364 : LVDS_RX_TOP.v(19) | Synthesizing module LVDS_RX_TOP @W:CG360 : LVDS_RX_TOP.v(46) | No assignment to wire deserializer_data_out @W:CG360 : LVDS_RX_TOP.v(47) | No assignment to wire rxsync_data_out @N:CG364 : RX_TOP.v(19) | Synthesizing module RX_TOP @N:CG364 : vita_ramDualPort.v(1) | Synthesizing module vita_ramDualPort DATA_WIDTH=32'b00000000000000000000000000001010 ADDRESS_WIDTH=32'b00000000000000000000000000000100 BUFF_DEPTH=32'b00000000000000000000000000010000 Generated name = vita_ramDualPort_10s_4s_16s @W:CG133 : vita_ramDualPort.v(11) | No assignment to q_a @N:CL134 : vita_ramDualPort.v(17) | Found RAM ram, depth=16, width=10 @N:CG364 : vita_data_decoder.v(28) | Synthesizing module vita_data_decoder @W:CG133 : vita_data_decoder.v(60) | No assignment to s_r_ChannelAd_i @W:CG133 : vita_data_decoder.v(61) | No assignment to s_r_ChannelBd_i @W:CG133 : vita_data_decoder.v(62) | No assignment to s_r_ChannelCd_i @W:CG133 : vita_data_decoder.v(63) | No assignment to s_r_ChannelDd_i @W:CG133 : vita_data_decoder.v(65) | No assignment to s_r_ChannelAd1_i @W:CG133 : vita_data_decoder.v(66) | No assignment to s_r_ChannelBd1_i @W:CG133 : vita_data_decoder.v(67) | No assignment to s_r_ChannelCd1_i @W:CG133 : vita_data_decoder.v(68) | No assignment to s_r_ChannelDd1_i @W:CG133 : vita_data_decoder.v(70) | No assignment to s_r_ChannelAd2_i @W:CG133 : vita_data_decoder.v(71) | No assignment to s_r_ChannelBd2_i @W:CG133 : vita_data_decoder.v(72) | No assignment to s_r_ChannelCd2_i @W:CG133 : vita_data_decoder.v(73) | No assignment to s_r_ChannelDd2_i @W:CG133 : vita_data_decoder.v(83) | No assignment to s_r_write_data_d @W:CL169 : vita_data_decoder.v(599) | Pruning register CFA_PixelOut_valid_o_d @W:CL169 : vita_data_decoder.v(599) | Pruning register CFA_PixelOut_valid_o_d1 @W:CL169 : vita_data_decoder.v(498) | Pruning register s_r_re @W:CL169 : vita_data_decoder.v(481) | Pruning register s_r_write_address_d[3:0] @W:CL169 : vita_data_decoder.v(481) | Pruning register s_r_we_d @W:CL169 : vita_data_decoder.v(359) | Pruning register s_read_address_sel @W:CL169 : vita_data_decoder.v(210) | Pruning register s_r_74clkframe_start_d @W:CL169 : vita_data_decoder.v(210) | Pruning register s_r_74clkframe_end_d @W:CL169 : vita_data_decoder.v(210) | Pruning register s_r_74clkline_end_d @W:CL169 : vita_data_decoder.v(144) | Pruning register s_r_pixel_valid @N:CG364 : vita_reciever.v(9) | Synthesizing module vita_reciever @N:CL201 : vita_data_decoder.v(359) | Trying to extract state machine for register s_r_write_address Extracted state machine for register s_r_write_address State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @A:CL153 : vita_ramDualPort.v(11) | *Unassigned bits of q_a[9:0] are referenced and tied to 0 -- simulation mismatch possible. @W:CL159 : LVDS_RX_TOP.v(20) | Input clk_x is unused @N:CL177 : Deserializer.v(91) | Sharing sequential element Align_data. @W:CL279 : Deserializer.v(91) | Pruning register bits 10 to 2 of Align_data[10:0] @N:CL201 : Deserializer.v(207) | Trying to extract state machine for register count Extracted state machine for register count State machine has 5 reachable states with original encodings of: 0000 0001 0010 0011 0100 @N:CL201 : Deserializer.v(112) | Trying to extract state machine for register STATE Extracted state machine for register STATE State machine has 7 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 @W:CL279 : Deserializer.v(91) | Pruning register bits 8 to 1 of Align_data_d2[10:1] @W:CL159 : Deserializer.v(23) | Input CLK180 is unused At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Aug 20 17:38:36 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Aug 20 17:38:36 2015 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Aug 20 17:38:36 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Aug 20 17:38:38 2015 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: vita_reciever_scck.rpt Printing clock summary report in "F:\Linting\cam_vita2k\synthesis\vita_reciever_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) syn_allowed_resources : blockrams=236 set on top level netlist vita_reciever Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------------------------------- System 100.0 MHz 10.000 system system_clkgroup vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 ================================================================================================================= @W:MT530 : deserializer.v(290) | Found inferred clock vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock which controls 346 sequential elements including RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.Data_out[9:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : vita_ramdualport.v(30) | Found inferred clock vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock which controls 51 sequential elements including vita_data_decoder_0.u0.q_b[9:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file F:\Linting\cam_vita2k\synthesis\vita_reciever.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Aug 20 17:38:39 2015 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Encoding state machine count[4:0] (view:work.Deserializer(verilog)) original code -> new code 0000 -> 00001 0001 -> 00010 0010 -> 00100 0011 -> 01000 0100 -> 10000 Encoding state machine STATE[6:0] (view:work.Deserializer(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0011 -> 0001000 0100 -> 0010000 0101 -> 0100000 0110 -> 1000000 Encoding state machine s_r_write_address[15:0] (view:work.vita_data_decoder(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @N:FX403 : vita_ramdualport.v(17) | Property "block_ram" or "no_rw_check" found for RAM u0.ram[9:0] with specified coding style. Inferring block RAM. @W:FX107 : vita_ramdualport.v(17) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : vita_ramdualport.v(17) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for u0.ram[9:0] (view:work.vita_data_decoder(verilog)). @A:BN291 : vita_ramdualport.v(30) | Boundary register u0.q_b[9:0] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N: : vita_data_decoder.v(317) | Found counter in view:work.vita_data_decoder(verilog) inst count[12:0] @W:MO160 : vita_data_decoder.v(577) | Register bit s_r_OutPixel_count[12] is always 0, optimizing ... @W:MO160 : vita_data_decoder.v(577) | Register bit s_r_OutPixel_count[11] is always 0, optimizing ... Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 3.84ns 393 / 375 @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[0] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[1] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[2] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[3] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[4] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[5] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[6] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[7] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[8] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[9] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs @N:FP130 : | Promoting Net LOCK_c on CLKINT I_75 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 140MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 140MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 2 non-gated/non-generated clock tree(s) driving 377 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ================================== Non-Gated/Non-Generated Clocks =================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ----------------------------------------------------------------------------------------------------- ClockId0001 FCCC_0.GL1_INST CLKINT 337 vita_data_decoder_0.s_r_we ClockId0002 FCCC_0.GL3_INST CLKINT 40 vita_data_decoder_0.count[12] ===================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 110MB peak: 140MB) Writing Analyst data base F:\Linting\cam_vita2k\synthesis\synwork\vita_reciever_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 140MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-3 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 140MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 140MB) @W:MT246 : vita_reciever.v(261) | Blackbox DDR_IN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : vita_reciever_fccc_0_fccc.v(35) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL3_net" @W:MT420 : | Found inferred clock vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL1_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Aug 20 17:38:42 2015 # Top view: vita_reciever Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 5.151 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------- vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 210.3 MHz 10.000 4.755 5.245 inferred Inferred_clkgroup_0 vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz 206.2 MHz 10.000 4.849 5.151 inferred Inferred_clkgroup_1 System 100.0 MHz 837.9 MHz 10.000 1.193 8.807 system system_clkgroup ======================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ System vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock | 10.000 8.807 | No paths - | No paths - | No paths - vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock | 10.000 5.245 | No paths - | No paths - | No paths - vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock | 10.000 5.151 | No paths - | No paths - | No paths - ========================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.Align_data_d1[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data_d1[0] 0.094 5.245 RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.Align_data_d1[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data_d1[0] 0.094 5.245 RX_TOP_0.u_LVDS_RX_TOP_D.u_deserializer_0.Align_data_d1[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data_d1[0] 0.094 5.245 RX_TOP_0.u_LVDS_RX_TOP_A.u_deserializer_0.Align_data_d1[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data_d1[0] 0.094 5.245 RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.Align_data_d1[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data_d1[0] 0.094 5.245 RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.Align_data[1] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data[1] 0.094 5.270 RX_TOP_0.u_LVDS_RX_TOP_D.u_deserializer_0.Align_data[1] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data[1] 0.094 5.270 RX_TOP_0.u_LVDS_RX_TOP_A.u_deserializer_0.Align_data[1] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data[1] 0.094 5.270 RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.Align_data[1] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data[1] 0.094 5.270 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.Align_data[1] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE Q Align_data[1] 0.094 5.270 =========================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.STATE[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D N_129_i_0 9.778 5.245 RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.STATE[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D N_129_i_0 9.778 5.245 RX_TOP_0.u_LVDS_RX_TOP_A.u_deserializer_0.STATE[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D N_129_i_0 9.778 5.245 RX_TOP_0.u_LVDS_RX_TOP_D.u_deserializer_0.STATE[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D N_129_i_0 9.778 5.245 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D N_129_i_0 9.778 5.245 vita_data_decoder_0.s_r_write_data[0] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D s_r_write_data_24[0] 9.778 6.127 vita_data_decoder_0.s_r_write_data[1] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D s_r_write_data_24[1] 9.778 6.127 vita_data_decoder_0.s_r_write_data[2] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D s_r_write_data_24[2] 9.778 6.127 vita_data_decoder_0.s_r_write_data[3] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D s_r_write_data_24[3] 9.778 6.127 vita_data_decoder_0.s_r_write_data[4] vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock SLE D s_r_write_data_24[4] 9.778 6.127 ======================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 4.533 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 5.245 Number of logic level(s): 5 Starting point: RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.Align_data_d1[0] / Q Ending point: RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE[0] / D The start point is clocked by vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK The end point is clocked by vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.Align_data_d1[0] SLE Q Out 0.094 0.094 - Align_data_d1[0] Net - - 1.176 - 11 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_a3_3_1[0] CFG4 B In - 1.270 - RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_a3_3_1[0] CFG4 Y Out 0.143 1.413 - STATE_ns_i_a3_3_1[0] Net - - 0.483 - 1 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_0[0] CFG4 D In - 1.896 - RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_0[0] CFG4 Y Out 0.408 2.304 - STATE_ns_i_0[0] Net - - 0.483 - 1 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_1[0] CFG4 D In - 2.788 - RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_1[0] CFG4 Y Out 0.408 3.196 - STATE_ns_i_1[0] Net - - 0.483 - 1 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_3[0] CFG4 B In - 3.679 - RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_ns_i_3[0] CFG4 Y Out 0.143 3.822 - STATE_ns_i_3[0] Net - - 0.483 - 1 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_RNO[0] CFG3 A In - 4.305 - RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE_RNO[0] CFG3 Y Out 0.090 4.395 - N_129_i_0 Net - - 0.138 - 1 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.STATE[0] SLE D In - 4.533 - ============================================================================================================================= Total path delay (propagation time + setup) of 4.755 is 1.508(31.7%) logic and 3.246(68.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- vita_data_decoder_0.s_r_OutPixel_count[4] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[4] 0.094 5.151 vita_data_decoder_0.s_r_OutPixel_count[0] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[0] 0.094 5.218 vita_data_decoder_0.s_r_OutPixel_count[5] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[5] 0.094 5.377 vita_data_decoder_0.s_r_OutPixel_count[6] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[6] 0.094 5.416 vita_data_decoder_0.s_r_OutPixel_count[1] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[1] 0.094 5.444 vita_data_decoder_0.s_r_OutPixel_count[2] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[2] 0.094 5.483 vita_data_decoder_0.s_r_OutPixel_count[7] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[7] 0.094 5.483 vita_data_decoder_0.s_r_OutPixel_count[3] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_OutPixel_count[3] 0.094 5.550 vita_data_decoder_0.count[2] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q count[2] 0.094 6.242 vita_data_decoder_0.s_r_74clkline_start_d vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE Q s_r_74clkline_start_d 0.094 6.295 =============================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- vita_data_decoder_0.s_r_read_address[3] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_read_address_4[3] 9.778 5.151 vita_data_decoder_0.s_r_read_address[0] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_read_address_4[0] 9.778 5.266 vita_data_decoder_0.s_r_read_address[1] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_read_address_4[1] 9.778 5.266 vita_data_decoder_0.s_r_read_address[2] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_read_address_4[2] 9.778 5.266 vita_data_decoder_0.s_r_OutPixel_count[10] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_OutPixel_count_4[10] 9.778 5.912 vita_data_decoder_0.s_r_OutPixel_count[9] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_OutPixel_count_4[9] 9.778 5.925 vita_data_decoder_0.s_r_OutPixel_count[8] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_OutPixel_count_4[8] 9.778 5.937 vita_data_decoder_0.s_r_OutPixel_count[7] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_OutPixel_count_4[7] 9.778 5.950 vita_data_decoder_0.s_r_OutPixel_count[6] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_OutPixel_count_4[6] 9.778 5.963 vita_data_decoder_0.s_r_OutPixel_count[5] vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock SLE D s_r_OutPixel_count_4[5] 9.778 5.975 ==================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 4.627 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 5.151 Number of logic level(s): 5 Starting point: vita_data_decoder_0.s_r_OutPixel_count[4] / Q Ending point: vita_data_decoder_0.s_r_read_address[3] / D The start point is clocked by vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock [rising] on pin CLK The end point is clocked by vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- vita_data_decoder_0.s_r_OutPixel_count[4] SLE Q Out 0.094 0.094 - s_r_OutPixel_count[4] Net - - 0.587 - 2 vita_data_decoder_0.un23lto7_5 CFG4 D In - 0.681 - vita_data_decoder_0.un23lto7_5 CFG4 Y Out 0.408 1.089 - un23lto7_5 Net - - 0.483 - 1 vita_data_decoder_0.un23lto7 CFG2 B In - 1.572 - vita_data_decoder_0.un23lto7 CFG2 Y Out 0.143 1.715 - un23lt8 Net - - 0.548 - 2 vita_data_decoder_0.un23lto7_RNIJVFC1 ARI1 B In - 2.263 - vita_data_decoder_0.un23lto7_RNIJVFC1 ARI1 Y Out 0.143 2.406 - un23lto7_RNIJVFC1_Y Net - - 0.982 - 4 vita_data_decoder_0.un1_s_r_read_address_1.CO1 CFG3 B In - 3.388 - vita_data_decoder_0.un1_s_r_read_address_1.CO1 CFG3 Y Out 0.143 3.531 - CO1 Net - - 0.548 - 2 vita_data_decoder_0.s_r_read_address_4[3] CFG4 D In - 4.079 - vita_data_decoder_0.s_r_read_address_4[3] CFG4 Y Out 0.411 4.489 - s_r_read_address_4[3] Net - - 0.138 - 1 vita_data_decoder_0.s_r_read_address[3] SLE D In - 4.627 - ============================================================================================================= Total path delay (propagation time + setup) of 4.849 is 1.564(32.3%) logic and 3.285(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------- DDR_IN_0 System DDR_IN QF DDR_IN_0_QF_0 0.000 8.807 DDR_IN_0 System DDR_IN QR DDR_IN_0_QR 0.000 8.807 DDR_IN_1 System DDR_IN QF DDR_IN_1_QF 0.000 8.807 DDR_IN_1 System DDR_IN QR DDR_IN_1_QR 0.000 8.807 DDR_IN_2 System DDR_IN QF DDR_IN_2_QF 0.000 8.807 DDR_IN_2 System DDR_IN QR DDR_IN_2_QR 0.000 8.807 DDR_IN_3 System DDR_IN QF DDR_IN_3_QF 0.000 8.807 DDR_IN_3 System DDR_IN QR DDR_IN_3_QR 0.000 8.807 DDR_IN_4 System DDR_IN QF DDR_IN_4_QF 0.000 8.807 DDR_IN_4 System DDR_IN QR DDR_IN_4_QR 0.000 8.807 ================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------- RX_TOP_0.u_LVDS_RX_TOP_A.u_deserializer_0.Align_data[0] System SLE D DDR_IN_4_QF 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.Align_data[0] System SLE D DDR_IN_0_QF_0 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.Align_data[0] System SLE D DDR_IN_1_QF 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_D.u_deserializer_0.Align_data[0] System SLE D DDR_IN_2_QF 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.Align_data[0] System SLE D DDR_IN_3_QF 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_A.u_deserializer_0.input_rising_reg2 System SLE D DDR_IN_4_QR 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.input_rising_reg2 System SLE D DDR_IN_0_QR 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_C.u_deserializer_0.input_rising_reg2 System SLE D DDR_IN_1_QR 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_D.u_deserializer_0.input_rising_reg2 System SLE D DDR_IN_2_QR 9.778 8.807 RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.input_rising_reg2 System SLE D DDR_IN_3_QR 9.778 8.807 =================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 8.807 Number of logic level(s): 0 Starting point: DDR_IN_0 / QF Ending point: RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.Align_data[0] / D The start point is clocked by System [rising] The end point is clocked by vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ DDR_IN_0 DDR_IN QF Out 0.000 0.000 - DDR_IN_0_QF_0 Net - - 0.971 - 1 RX_TOP_0.u_LVDS_RX_TOP_B.u_deserializer_0.Align_data[0] SLE D In - 0.971 - ======================================================================================================================== Total path delay (propagation time + setup) of 1.193 is 0.222(18.6%) logic and 0.971(81.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 140MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 140MB) --------------------------------------- Resource Usage Report for vita_reciever Mapping to part: m2s150tfc1152-1 Cell usage: CCC 1 use CLKINT 3 uses DDR_IN 5 uses CFG1 1 use CFG2 74 uses CFG3 96 uses CFG4 185 uses Carry primitives used for arithmetic functions: ARI1 26 uses Sequential Cells: SLE 375 uses DSP Blocks: 0 I/O ports: 38 I/O primitives: 32 INBUF 1 use INBUF_DIFF 6 uses OUTBUF 25 uses Global Clock Buffers: 3 RAM/ROM usage summary Block Rams (RAM64x18) : 1 Total LUTs: 382 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 36; LUTs = 36; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 375 + 36 + 0 + 0 = 411; Total number of LUTs after P&R: 382 + 36 + 0 + 0 = 418; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 140MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Thu Aug 20 17:38:42 2015 ###########################################################]