Project Settings Project Name AR0330_CAM_TOP_syn Implementation Name synthesis Top Module AR0330_CAM_TOP Retiming 0 Resource Sharing 0 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 428 2946 0 - 0m:03s - 12/6/2016 10:37:36 AM (premap) Complete 227 104 0 0m:05s 0m:05s 213MB 12/6/2016 10:37:45 AM (fpga_mapper) Complete 1178 3935 0 01m:40s 01m:41s 340MB 12/6/2016 10:39:27 AM Multi-srs Generator Complete 0m:02s 12/6/2016 10:37:40 AM Area Summary Carry Cells 3846 Sequential Cells 9917 DSP Blocks (MACC) (dsp_used) 46 I/O Cells 163 Global Clock Buffers 18 Block Rams (RAM1K18) (v_ram) 89 LUTs (total_luts) 12172 Timing Summary Clock Name Req Freq Est Freq Slack AR0330_CAM_TOP_Audio_CCC_FCCC|GL0_net_inferred_clock 100.0 MHz 369.5 MHz 7.293 AR0330_CAM_TOP_FCCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 123.9 MHz 1.927 AR0330_CAM_TOP_FCCC_0_FCCC|GL2_net_inferred_clock 100.0 MHz 342.2 MHz 7.077 AR0330_CAM_TOP_FCCC_1_FCCC|GL0_net_inferred_clock 100.0 MHz 166.5 MHz 3.993 AUDIO_SCK_IN 1.5 MHz 121.6 MHz 321.408 CLK_GEN|_CLKOUT_inferred_clock 100.0 MHz 121.6 MHz 0.887 Image_Pix_Clock_i 66.0 MHz NA NA MSS_TOP_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 163.6 MHz 3.886 MSS_TOP_sb_CCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 149.6 MHz 3.315 MSS_TOP_sb_CCC_0_FCCC|GL2_net_inferred_clock 100.0 MHz 136.1 MHz 2.655 MSS_TOP_sb_CCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz NA NA MSS_TOP_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 428.6 MHz 7.667 MSS_TOP_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 109.6 MHz 0.875 System 100.0 MHz 1029.4 MHz 9.029 Optimizations Summary Combined Clock Conversion 13 / 1