#Build: Synplify Pro J-2015.03M-3, Build 048R, May 14 2015 #install: C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3 #OS: Windows 7 6.1 #Hostname: W764L-SUDEEPS #Implementation: synthesis Synopsys HDL Compiler, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\hypermods.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\scemi_pipes.svh" @I::"D:\SVN_Video_repository\Releases\camera\New_IPs\cam_vita2k_displayCtrl_with_new_cam_v12\cam_vita2k\hdl\bus_cdc_synchornizer.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module bus_cdc_synchornizer @N:CG364 : bus_cdc_synchornizer.v(27) | Synthesizing module bus_cdc_synchornizer At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 02 18:27:53 2016 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 02 18:27:53 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 02 18:27:53 2016 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 02 18:27:55 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: bus_cdc_synchornizer_scck.rpt Printing clock summary report in "D:\SVN_Video_repository\Releases\camera\New_IPs\cam_vita2k_displayCtrl_with_new_cam_v12\cam_vita2k\synthesis\bus_cdc_synchornizer_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) syn_allowed_resources : blockrams=236 set on top level netlist bus_cdc_synchornizer Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------------------------- bus_cdc_synchornizer|DEST_CLOCK_I 100.0 MHz 10.000 inferred Inferred_clkgroup_1 bus_cdc_synchornizer|SOURCE_CLOCK_I 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ==================================================================================================== @W:MT530 : bus_cdc_synchornizer.v(43) | Found inferred clock bus_cdc_synchornizer|SOURCE_CLOCK_I which controls 32 sequential elements including input_bus_reg[31:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : bus_cdc_synchornizer.v(51) | Found inferred clock bus_cdc_synchornizer|DEST_CLOCK_I which controls 64 sequential elements including gray_bus_reg2[31:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\SVN_Video_repository\Releases\camera\New_IPs\cam_vita2k_displayCtrl_with_new_cam_v12\cam_vita2k\synthesis\bus_cdc_synchornizer.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 134MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 02 18:27:55 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 134MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 134MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 134MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 9.09ns 63 / 96 @N:FP130 : | Promoting Net DEST_CLOCK_I_c on CLKINT I_1 @N:FP130 : | Promoting Net SOURCE_CLOCK_I_c on CLKINT I_2 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 134MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 2 non-gated/non-generated clock tree(s) driving 96 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================ Non-Gated/Non-Generated Clocks ============================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ----------------------------------------------------------------------------------------- ClockId0001 DEST_CLOCK_I port 64 gray_bus_reg1[10] ClockId0002 SOURCE_CLOCK_I port 32 input_bus_reg[10] ========================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 134MB) Writing Analyst data base D:\SVN_Video_repository\Releases\camera\New_IPs\cam_vita2k_displayCtrl_with_new_cam_v12\cam_vita2k\synthesis\synwork\bus_cdc_synchornizer_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 134MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-3 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) @W:MT420 : | Found inferred clock bus_cdc_synchornizer|SOURCE_CLOCK_I with period 10.00ns. Please declare a user-defined clock on object "p:SOURCE_CLOCK_I" @W:MT420 : | Found inferred clock bus_cdc_synchornizer|DEST_CLOCK_I with period 10.00ns. Please declare a user-defined clock on object "p:DEST_CLOCK_I" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Wed Mar 02 18:27:56 2016 # Top view: bus_cdc_synchornizer Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 9.106 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------- bus_cdc_synchornizer|DEST_CLOCK_I 100.0 MHz 1118.7 MHz 10.000 0.894 9.106 inferred Inferred_clkgroup_1 bus_cdc_synchornizer|SOURCE_CLOCK_I 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 =========================================================================================================================================== @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------- bus_cdc_synchornizer|SOURCE_CLOCK_I bus_cdc_synchornizer|DEST_CLOCK_I | Diff grp - | No paths - | No paths - | No paths - bus_cdc_synchornizer|DEST_CLOCK_I bus_cdc_synchornizer|DEST_CLOCK_I | 10.000 9.106 | No paths - | No paths - | No paths - ============================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: bus_cdc_synchornizer|DEST_CLOCK_I ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ gray_bus_reg1[0] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[0] 0.076 9.106 gray_bus_reg1[1] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[1] 0.076 9.106 gray_bus_reg1[2] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[2] 0.076 9.106 gray_bus_reg1[3] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[3] 0.076 9.106 gray_bus_reg1[4] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[4] 0.076 9.106 gray_bus_reg1[5] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[5] 0.076 9.106 gray_bus_reg1[6] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[6] 0.076 9.106 gray_bus_reg1[7] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[7] 0.076 9.106 gray_bus_reg1[8] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[8] 0.076 9.106 gray_bus_reg1[9] bus_cdc_synchornizer|DEST_CLOCK_I SLE Q gray_bus_reg1[9] 0.076 9.106 ================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- gray_bus_reg2[0] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[0] 9.778 9.106 gray_bus_reg2[1] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[1] 9.778 9.106 gray_bus_reg2[2] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[2] 9.778 9.106 gray_bus_reg2[3] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[3] 9.778 9.106 gray_bus_reg2[4] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[4] 9.778 9.106 gray_bus_reg2[5] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[5] 9.778 9.106 gray_bus_reg2[6] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[6] 9.778 9.106 gray_bus_reg2[7] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[7] 9.778 9.106 gray_bus_reg2[8] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[8] 9.778 9.106 gray_bus_reg2[9] bus_cdc_synchornizer|DEST_CLOCK_I SLE D gray_bus_reg1[9] 9.778 9.106 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 0.672 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 9.106 Number of logic level(s): 0 Starting point: gray_bus_reg1[0] / Q Ending point: gray_bus_reg2[0] / D The start point is clocked by bus_cdc_synchornizer|DEST_CLOCK_I [rising] on pin CLK The end point is clocked by bus_cdc_synchornizer|DEST_CLOCK_I [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------- gray_bus_reg1[0] SLE Q Out 0.076 0.076 - gray_bus_reg1[0] Net - - 0.596 - 1 gray_bus_reg2[0] SLE D In - 0.672 - =============================================================================== Total path delay (propagation time + setup) of 0.894 is 0.298(33.3%) logic and 0.596(66.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) --------------------------------------- Resource Usage Report for bus_cdc_synchornizer Mapping to part: m2s150tfc1152-1 Cell usage: CLKINT 2 uses CFG2 40 uses CFG3 12 uses CFG4 11 uses Sequential Cells: SLE 96 uses DSP Blocks: 0 I/O ports: 66 I/O primitives: 66 INBUF 34 uses OUTBUF 32 uses Global Clock Buffers: 2 Total LUTs: 63 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 96 + 0 + 0 + 0 = 96; Total number of LUTs after P&R: 63 + 0 + 0 + 0 = 63; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 134MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 02 18:27:56 2016 ###########################################################]