@W: MT530 :"f:\linting\cam_vita2k\hdl\deserializer.v":290:1:290:6|Found inferred clock vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock which controls 346 sequential elements including RX_TOP_0.u_LVDS_RX_TOP_E.u_deserializer_0.Data_out[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\linting\cam_vita2k\hdl\vita_ramdualport.v":30:1:30:6|Found inferred clock vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock which controls 51 sequential elements including vita_data_decoder_0.u0.q_b[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
