@W: FX107 :"f:\linting\cam_vita2k\hdl\vita_ramdualport.v":17:1:17:6|No read/write conflict check. Possible simulation mismatch!
@W: MO160 :"f:\linting\cam_vita2k\hdl\vita_data_decoder.v":577:1:577:6|Register bit s_r_OutPixel_count[12] is always 0, optimizing ...
@W: MO160 :"f:\linting\cam_vita2k\hdl\vita_data_decoder.v":577:1:577:6|Register bit s_r_OutPixel_count[11] is always 0, optimizing ...
@W: MT246 :"f:\linting\cam_vita2k\component\work\vita_reciever\vita_reciever.v":261:7:261:14|Blackbox DDR_IN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"f:\linting\cam_vita2k\component\work\vita_reciever\fccc_0\vita_reciever_fccc_0_fccc.v":35:36:35:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock vita_reciever_FCCC_0_FCCC|GL3_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL3_net"
@W: MT420 |Found inferred clock vita_reciever_FCCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL1_net"
