@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: FX403 :"f:\linting\cam_vita2k\hdl\vita_ramdualport.v":17:1:17:6|Property "block_ram" or "no_rw_check" found for RAM u0.ram[9:0] with specified coding style. Inferring block RAM.
@N: MF707 :"f:\linting\cam_vita2k\hdl\vita_ramdualport.v":17:1:17:6|Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for u0.ram[9:0] (view:work.vita_data_decoder(verilog)).
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[0] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[1] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[2] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[3] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[4] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[5] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[6] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[7] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[8] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance vita_data_decoder_0.u0.ram_ram_0_0_R[9] of view:ACG4.SLE(PRIM) in hierarchy view:work.vita_reciever(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net LOCK_c on CLKINT  I_75 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
