@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\cam_vita2k_displayctrl_with_new_cam_v12\cam_vita2k\hdl\bus_cdc_synchornizer.v":43:2:43:7|Found inferred clock bus_cdc_synchornizer|SOURCE_CLOCK_I which controls 32 sequential elements including input_bus_reg[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\cam_vita2k_displayctrl_with_new_cam_v12\cam_vita2k\hdl\bus_cdc_synchornizer.v":51:2:51:7|Found inferred clock bus_cdc_synchornizer|DEST_CLOCK_I which controls 64 sequential elements including gray_bus_reg2[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
