@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\hdl\video_timing_generator.v":197:2:197:7|Removing sequential instance display_controller_0.video_timing_generator_0.disp_cont_busy_o,  because it is equivalent to instance display_controller_0.video_timing_generator_0.start_ddr_read
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[0],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[0]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[1],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[1]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[2],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[2]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[3],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[3]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[4],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[4]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[5],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[5]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[6],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[6]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_regY1[7],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[8]
@W: BN132 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\display_enhancements\1.0.0\rtl\display_enhancements.v":388:2:388:7|Removing sequential instance Display_Enhancements_0.contrast_i_reg1[8],  because it is equivalent to instance Display_Enhancements_0.contrast_i_reg1[7]
@W: MT462 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\work\ar0331_cam_top\ar0331_cam_top.v":598:6:598:12|Net BIBUF_0_Y appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\work\ar0331_cam_top\ar0331_cam_top.v":620:6:620:12|Net BIBUF_2_Y appears to be an unidentified clock source. Assuming default frequency. 
@W: MT532 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\work\vga_display_mss_mss\vga_display_mss_mss.v":1810:0:1810:13|Found signal identified as System clock which controls 0 sequential elements including vga_display_mss_top_0.vga_display_mss_0.vga_display_mss_MSS_0.MSS_ADLIB_INST.  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\hdl\bus_cdc_synchornizer.v":51:2:51:7|Found inferred clock vga_display_mss_CCC_0_FCCC|GL2_net_inferred_clock which controls 9383 sequential elements including AR0331_PRL_IF_0.bus_cdc_synchornizer_1.gray_bus_reg2[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\microsemi\solutioncore\ddr_memory_arbiter\1.0.0\rtl\axi_buffer.v":70:2:70:7|Found inferred clock vga_display_mss_CCC_0_FCCC|GL1_net_inferred_clock which controls 18 sequential elements including video_dma_0.video_dma_0.write_channel1_top_0.axi_buffer_0.rd_addr_reg[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock vga_display_mss_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including vga_display_mss_top_0.vga_display_mss_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\hdl\apb_wrapper.v":87:4:87:9|Found inferred clock vga_display_mss_CCC_0_FCCC|GL0_net_inferred_clock which controls 158 sequential elements including APB_WRAPPER_0.sin_value[9:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock vga_display_mss_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including vga_display_mss_top_0.vga_display_mss_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\hdl\ram2port.v":68:2:68:7|Found inferred clock AR0331_CAM_TOP_FCCC_0_FCCC|GL1_net_inferred_clock which controls 1269 sequential elements including display_controller_0.video_fifo_0.ram2port_0.rd_addr_reg[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\svn_video_repository\releases\camera\new_ips\11.7_test\cam_vita2k_displayctrl_with_new_cam_v26\cam_vita2k\hdl\ar0330_parallel_if.v":264:1:264:6|Found inferred clock AR0331_CAM_TOP_FCCC_1_FCCC|GL0_net_inferred_clock which controls 284 sequential elements including AR0331_PRL_IF_0.AR0330_Parallel_IF_0.s_r_V_Counter[15:0]. This clock has no specified timing constraint which may adversely impact design performance. 
